GB2304244A

GB2304244A - Gated CMOS input buffer circuit

Info

Publication number: GB2304244A
Application number: GB9516396A
Authority: GB
Inventors: David William Howard
Original assignee: Advanced Risc Machines Ltd
Current assignee: ARM Ltd
Priority date: 1995-08-10
Filing date: 1995-08-10
Publication date: 1997-03-12
Anticipated expiration: 2015-08-10
Also published as: GB2304244B; GB9516396D0

Abstract

A CMOS input buffer 2 is connected to a bus and is disabled by a low level on signal line Enable when the bus signal 4 could be at a level not close to either supply rail. Without transistor 10, both input transistors 6 and 8 might then conduct simultaneously and an excessive supply current would be drawn. Transistor 12 ensures that the output of the buffer is at a stable high state when the buffer is disabled. The buffer may be inhibited when the circuit to which it supplies the output signal is not the intended recipient of the bus signal (figure 6). Alternatively, the buffer may be used to read the bit line in a cache memory (18, figure 5), wherein the buffer is enabled, and the sense amplifier (16) disabled, during second and subsequent read cycles from the same row, by which time the bit line will have stabilised near a supply rail.

Description

DATA PROCESSING SYSTEM SIGNAL RECEIVING BUFFERS This invention relates to the field of data processing. More particularly, this invention relates to signal receiving buffers of the type used to receive signals passed between circuit elements via a signal bus.

It is known to pass signals between circuit elements within a data processing system via a signal bus. Typically, a plurality of circuit elements are connected to the signal bus that may each act as either a signal receiver or a signal generator. For a given signal transfer desired, a bus controller will pass control to a given circuit to generate signals on the signal bus and render the one or more circuits intended to receive those signals responsive to them. Such a structure has many advantages and allows a system to be built up in a modular fashion with each element interconnected via a common signal bus.

It is an aim within data processing systems that power consumption should be reduced. Reducing power consumption reduces the amount of heat generated within a circuit, and so enables faster and more reliable operation with a more densely packed circuit. In addition, a low power consumption is particularly useful in portable devices for which the available battery power is at a premium.

Within a data processing system, there are some signals which do not switch state as rapidly as others during data processing operation. This relatively slow switching in state can be produced by the need to drive high capacitance signal lines with small and high impedance driving circuits. An example of such a situation arises in a cache memory. Within a cache memory, each bit cell is required to drive a complete bit line when it is selected in order to output the contents of that bit cell.

The transistors within a given bit cell will be made small so as to produce a tightly packed and low die area circuit element whilst the bit lines are comparatively long so as to span the full range of cache rows. An example of the signal produced upon a bit line by such a cache cell is indicated by waveform (A) in Figure 1 of the accompanying drawings.

Waveform (A) indicates a signal transition from a one (5V) to a zero (OV).

This transition may take approximately 10 nsec, which given the size and speed of operation of a modern integrated circuit is slow.

Given the presence of such signals having slow transitions within a data processing circuit, a problem arises at the circuits that receive the signals. It is usual to buffer the signals received from the signal bus with a circuit such as the inverters illustrated at the top of Figure 1. Buffering the bus signals in this way compensates for signal degradation that may have occurred along a long signal bus and allows a high impedance driver circuit to drive the signal bus without undue concern as to the impedance of the receiving circuit(s). However, whilst such buffer circuits operate well in most circumstances, a power consumption problem arises when such buffer circuits are driven by a signal which switches slowly between states.

The top portion of Figure 1 illustrates an inverter operating as a buffer circuit with its input switching from a "one" to a "zero". Whilst the input signal is transitioning between levels, both FETs are partially switched on leading to a low impedance path between the rail voltages. This results in a short circuit current ("crowbar current") of a magnitude of approximately 100A.

Given the above example, if one considers a 32-bit bus driving five such inputs with a chip operating at 40MHz and with a 5V rail voltage, then the power wasted by such crowbar currents is given by: Power = 32bits x 5loads x 100,u A x 5V x 10nsec/25nsec = 32mW This is a large amount of power to waste within a low-power chip design.

Viewed from one aspect the present invention provides an apparatus for processing data, said apparatus comprising: a signal bus; a signal generating circuit coupled to said signal bus for generating bus signals upon said signal bus; a signal receiving circuit coupled to said signal bus for receiving said bus signals from said signal bus, said signal receiving circuit including one or more signal receiving buffers for buffering bus signals received directly from said signal bus to generate buffered signals for processing by said signal receiving circuit; and a signal transfer controller for controlling transfer of signals between said signal generating circuit and said signal receiving circuit, said signal transfer controller acting to inhibit said one or more signal receiving buffers when said bus signals are not for processing by said signal receiving circuit such that, when inhibited, said signal receiving buffers do not change said buffered signals in response to changes in said bus signals.

The present invention recognises and solves the problem of excess power consumption due to crowbar currents in buffer circuits receiving signals from a signal bus. The invention solves this problem by inhibiting these buffers so as to be nonresponsive to signals on the signal bus when those signals are not intended for the circuit attached to those buffers. Thus, if there are five 32-bit loads, then only one need be switched on with the others being inhibited at the level of the buffers directly attached to the signal bus. Inhibiting the bus signals directly at the signal bus reduces the amount of circuitry responsive to a given signal compared to if the circuit was inhibited further downstream and so reduces the power consumption.

In the case of the example given, the present invention can produce a saving of 25.6 mW and reduce the power loss through crowbar currents in the input buffers from 32 mW to only 6.4 mW.

Whilst the present invention may be used with many different fabrication techniques, it is particularly useful in circumstances in which said one or more signal receiving buffers comprise a CMOS circuit.

The use of a CMOS circuit as a signal receiving buffer allows a small fabrication size to be achieved with a small number of individual circuit elements (e.g.

the two FETs of Figure 1), but does suffer from the disadvantage of being particularly prone to crowbar currents when switching between states.

In preferred embodiments of the invention, when inhibited, said one or more signal receiving buffers each output a buffered signal having a determined level.

When the buffer is inhibited, there is a possibility that the output of the buffer may become ill defined with the consequence that crowbar currents due to partially switched circuits may arise further downstream within the signal receiving circuit.

Accordingly, having the output of the buffer held at a determined level (irrespective of whether this is a "one" or "zero" or maintains its previous state) ensures that the signal receiving circuit adopts a well defined and low power consumption state when not in use.

The present invention may be used between any sort of signal generating circuit and signal receiving circuit coupled by a signal bus. However, the invention is particularly useful in embodiments in which said signal generating circuit is a memory circuit and said signal bus is bit lines for outputting stored data from said memory circuit.

The invention recognises that the circuits responsive to signal values on the bit lines of a memory circuit are particularly prone to crowbar currents since the bit lines have a high capacitance and are driven by high impedance bit cell elements.

The usefulness of the invention is particularly high in embodiments in which said signal generating circuit is a cache memory circuit and said signal receiving circuit is a word selecting circuit for selecting a word from a cache row of said cache memory circuit for output.

There is continuous pressure to make cache memory circuits have a higher storage capacity, and accordingly use smaller, higher impedance bit cells whilst increasing their speed of operation thereby making the time taken for the bit line to reach their final value more significant in the overall timing of the circuit. In addition, cache memory circuits are usually fabricated in close proximity to other circuit elements to increase their speed of use with the result that power consumption problems and associated heat generation become more significant.

Whilst it will be appreciated that the invention may be utilised in circuits composed of discrete components, the invention is particularly useful in integrated circuits. Integrated circuits operate at speeds with capacitance and switching times that make the present invention contribute significantly to reducing the power consumption of the overall device.

Viewed from another aspect the present invention provides a method of processing data, said method comprising the steps of: a signal bus; generating bus signals upon a signal bus with a signal generating circuit coupled to said signal bus; receiving said bus signals from said signal bus with a signal receiving circuit coupled to said signal bus, said signal receiving circuit including one or more signal receiving buffers for buffering bus signals received directly from said signal bus to generate buffered signals for processing by said signal receiving circuit; and controlling transfer of signals between said signal generating circuit and said signal receiving circuit with a signal transfer controller, said signal transfer controller acting to inhibit said one or more signal receiving buffers when said bus signals are not for processing by said signal receiving circuit such that, when inhibited, said signal receiving buffers do not change said buffered signals in response to changes in said bus signals.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 illustrates a buffer circuit suffering from a crowbar current; Figure 2 illustrates a buffer circuit modified so as to be inhibited when not in use; Figure 3 illustrates various operational states of the circuit of Figure 2; Figure 4 illustrates a portion of a cache circuit in which the present invention may be used; Figure 5 illustrates the circuit of Figure 4 modified in accordance with one embodiment of the invention; and Figure 6 illustrates a data processing system with a main signal bus in which each circuit receiving data from the main signal bus is modified in accordance with one embodiment of the invention.

Figure 2 illustrates signal receiving buffer 2 that receives a bus signal (In) at its input 4. This bus signal is connected to the gates of two transistors 6, 8. The transistors 6, 8 are equivalent to the transistors of the buffer shown in Figure 1.

An isolating transistor 10 is connected between the ground and the two transistors 6, 8. If the isolating transistor 10 is switched off, then it is not possible for a crowbar current to flow.

An output defining transistor 12 is connected to the output line 14 and drives the buffer signal (Out) to a defined level (5V) when the buffer 2 is inhibited.

Figure 3 illustrates the operation of the circuit of Figure 2 in more detail. In situation A, the buffer circuit 2 is inhibited and the inhibiting transistor 10 is switched off. At the same time, the output defining transistor 12 is switched on thereby forcing a buffered output signal of 5V. Since the isolating transistor 10 is switched off and the output defining transistor 12 is switched on, the two transistors 6, 8 can be either on or off without inducing a crowbar current or altering the buffered output signal.

Situation B illustrates the circumstance where the buffer circuit 2 is not inhibited and accordingly the isolating transistor 10 is switched on and the output defining transistor 12 is switched off. In this state, the two transistors 6, 8 act as a normal inverter and so a bus signal of OV will produce a buffered output signal of 5V with the transistor 6 switched on and the transistor 8 switched off.

Situation C is similar to that of situation B except that in this case the bus signal is 5V and the buffered output signal is OV with the transistor 6 switched off and the transistor 8 switched on.

Figure 4 illustrates a portion of a cache memory circuit. The cache memory circuit is composed of a plurality of cache cells 14 that each store one bit of information. When a particular cache cell 14 is selected (as part of an entire cache row), its stored bit is output to the main and complementary bit lines (bit, nbit). The bit lines are input to a sense amplifier 16 in which any difference between them is amplified to a full rail voltage so that the cache may be more rapidly read. The sense amplifier 16 consumes a disadvantageously large amount of current and so for subsequent read cycles from the same cache row, the sense amplifier 16 is disabled since the bit lines will already have reached their static levels and will be read by a buffer 18 and a logic circuit 20 (together forming a signal receiving circuit).The selection of output between the logic circuit 20 and the sense amplifier 18 is performed by a multiplexer 22.

In the circuit of Figure 4, whilst the bit lines from the cache memory are reaching their full rail voltages, they are supplied to the buffer 18 which will suffer from a disadvantageous crowbar current.

Figure 5 illustrates a modification of the circuit of Figure 4. In this circuit, the buffer 18 of Figure 4 is replaced with a buffer such as that illustrated in Figure 3. In this case whilst the sense amplifier 16 is active during a first read from a cache row, the buffer 18 is disabled. Upon subsequent read cycles from the same cache row, the buffer 18 is enabled. A cache controller 24 sequences the reading of words from a cache row when each cache row stores a plurality of such words. The cache controller can also inhibit the respective buffers 18 when they are not required.

Figure 6 illustrates another embodiment of the invention. In this case, the invention is utilised at a higher level where the signal bus concerned is the main signal bus 26 of a microprocessor 28. The microprocessor 28 is composed of standard functional units, such as a central processing unit 30, a random access memory 32, a floating point unit 34, a cache memory 36 and a memory management unit 38. A bus controller 40 is utilised to co-ordinate the access afforded to each of the units connected to the signal bus 26 so that a particularly unit will be given control to write signals to the signal bus 26 and respective units in which it is desired to receive those signals will be so activated. In this context, enabling signals (En&num; O to En&num; 3) are supplied to each functional unit to switch signal receiving buffers associated with each bit of the main signal bus 26. The signal receiving buffers have the form illustrated in Figure 3. When a given signal receiving buffer is disabled, then the buffered output supplied to the functional unit will be held in a defined state by the output defining transistor 12 thereby reducing power consumption.

Claims

1. Apparatus for processing data, said apparatus comprising: a signal bus; a signal generating circuit coupled to said signal bus for generating bus signals upon said signal bus; a signal receiving circuit coupled to said signal bus for receiving said bus signals from said signal bus, said signal receiving circuit including one or more signal receiving buffers for buffering bus signals received directly from said signal bus to generate buffered signals for processing by said signal receiving circuit; and a signal transfer controller for controlling transfer of signals between said signal generating circuit and said signal receiving circuit, said signal transfer controller acting to inhibit said one or more signal receiving buffers when said bus signals are not for processing by said signal receiving circuit such that, when inhibited, said signal receiving buffers do not change said buffered signals in response to changes in said bus signals.

2. Apparatus as claimed in claim 1, wherein said one or more signal receiving buffers comprise a CMOS circuit.

3. Apparatus as claimed in any one of claims 1 and 2, wherein, when inhibited, said one or more signal receiving buffers each output a buffered signal having a determined level.

4. Apparatus as claimed in any one of claims 1, 2 and 3, wherein said signal generating circuit is a memory circuit and said signal bus is bit lines for outputting stored data from said memory circuit.

5. Apparatus as claimed in claim 4, wherein said signal generating circuit is a cache memory circuit and said signal receiving circuit is a word selecting circuit for selecting a word from a cache row of said cache memory circuit for output.

6. Apparatus as claimed in any one of the preceding claims, wherein said apparatus comprises an integrated circuit.

7. A method of processing data, said method comprising the steps of: a signal bus; generating bus signals upon a signal bus with a signal generating circuit coupled to said signal bus; receiving said bus signals from said signal bus with a signal receiving circuit coupled to said signal bus, said signal receiving circuit including one or more signal receiving buffers for buffering bus signals received directly from said signal bus to generate buffered signals for processing by said signal receiving circuit; and controlling transfer of signals between said signal generating circuit and said signal receiving circuit with a signal transfer controller, said signal transfer controller acting to inhibit said one or more signal receiving buffers when said bus signals are not for processing by said signal receiving circuit such that, when inhibited, said signal receiving buffers do not change said buffered signals in response to changes in said bus signals.

8. Apparatus for processing data substantially as hereinbefore described with reference to Figures 2 to 6 of the accompanying drawings.

9. A method of processing data substantially as hereinbefore described with reference to Figures 2 to 6 of the accompanying drawings.