GB2295722A - Packaging integrated circuits - Google Patents
Packaging integrated circuits Download PDFInfo
- Publication number
- GB2295722A GB2295722A GB9424178A GB9424178A GB2295722A GB 2295722 A GB2295722 A GB 2295722A GB 9424178 A GB9424178 A GB 9424178A GB 9424178 A GB9424178 A GB 9424178A GB 2295722 A GB2295722 A GB 2295722A
- Authority
- GB
- United Kingdom
- Prior art keywords
- integrated circuit
- polymer material
- package
- flag
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
An integrated circuit (12) is mounted on a flag portion (11) of a leadframe. The leadframe also includes lead posts (10) to which are connected electrical connectors or bond wires (13) extending between the posts (10) and the integrated circuit (12). A plastic package (A) is moulded around the lead posts (10), the flag (11), the integrated circuit (12) and the bond wires (13). A polymer material is coated on all surfaces exposed prior to moulding of the package (A). The polymer material used for this encapsulation is is of very low molecular weight and viscosity and provides protection of the integrated circuit from corrosion by being chemisorbed onto its surface. This effectively seals any problem in the integrity of the passivation layer preventing moisture ingress, collection and therefore corrosion. <IMAGE>
Description
METHOD OF PACKAGING INTEGRATED CIRCUITS
Field Of The Invention
This invention relates to a method of packaging integrated circuits, and more particularly to a method of encapsulating integrated circuits in plastics packages.
Background Of The Invention
Plastic packaged semiconductor devices whilst being markedly less expensive than hermetically packaged alternatives have historically being hindered by drawbacks such as increased susceptibility to moisture induced corrosion and damage caused by temperature cycling. More recently with the advent of thinner packages the phenomenon of "pop-corn" has forced extra processing steps on semiconductor manufacturers and restrictions on those who mount the devices onto printed circuit boards.
In plastic assembled packages moisture can penetrate directly through the epoxy leading to corrosion of the metallisation layer of the integrated circuit. Corrosion occurs particularly on the bond pads, but if there are problems in the integrity of the passivation layer then the entire integrated circuit is at risk, even in the absence of delamination of the interface between the plastic package and the integrated circuit. Slight delamination, even if not leading to non-functionality, can lead to increased susceptibility to moisture ingress and so corrosion.
Delamination of any of the interfaces between the plastic package and the integrated circuit, connecting medium (ie. bond wires) and leadframe (ie.
the bonding flag and the lead posts) can create a moisture path which increases corrosion susceptibility.
The most common problem that occurs as a result of moisture in plastic packaged semiconductor devices is due to the soldering processes used in connecting the component onto a printed circuit board. Certain package types and lead frame / die size combinations are more susceptible to the problem, but in simple terms, moisture absorbed by the the package is made to rapidly expand by the sharp rise in temperature experienced in all forms of soldering. The resulting pressure causes the interfaces between the plastic package and the integrated circuit, leadframe and connecting medium to experience a stress. If the adhesion between any, or all, of the before mentioned interfaces is not sufficiently robust then they can delaminate, ie. the plastic package and the substrate become separated. This effect is commonly known as "popcorn".At present packages which are susceptible to this problem are given an extra bake and then dry-packed to prevent moisture ingress. However, the time between removing the package from dry pack and performing the solder process must be controlled to prevent a level of moisture building up which can cause "popcorn". The "popcorn" issue can give functional failure of the device due to forces exerted on the connecting medium, ie. the bond wires.
In plastic packaged integrated circuits there is an inherent mismatch between the coefficients of thermal expansion of the plastic package and the integrated circuit, leadframe and connecting medium.
This mismatch creates stress on the integrated circuit when the package experiences any form of temperature cycling. This stress can crack the integrated circuit causing reliability issues which can lead to nonfunctionality.
Another form of damage which can also occur is caused by the filler particles in the plastic material used to create the package. Although essential to the physical properties of the plastic package they can damage the passivation layer of the integrated circuit.
Techniques have been employed to tackle to above problems with degrees of success. However, at present there is no single solution which deals with all the problems effectively. Modified leadframes have been employed to reduce the risks of delamination of the bonding flag underside.
Polyimide top layers on integrated circuits do provide protection against the problems associated with the different thermal expansion coefficients of the plastic package and integrated circuit. Polyimide is also an effective barrier which prevents damage from the filler particles contained in the package plastic and delamination of the integrate circuit to package interface is also less likely to occur. However, the bond pads are still exposed to moisture and hence corrosion.
The polyimide layer discussed above is produced during the wafer fabrication process and the production of this layer requires a photolithography step and an etching step. Both of these involve volatile materials which require special handling. The etching process clears the bond pads of polyimide to allow the integrated circuit to be tested at probe and bonded during assembly. In EPROM devices full testing takes place at probe and to return the devices to their unprogrammed state by erasing them using ultra violet (UV) light. This erase step is not possible through the polyimide and therefore two sets of tests must be carried out at probe, one prior to polyimide deposition and the other after. This involves moving the wafers in and out of the wafer fab which can create difficulties.
It is therefore an object of the present invention to mitigate the abovementioned disadvantages of known packaging techniques.
Brief Summary Of The Invention
Accordingly, the invention provides a method of packaging an integrated circuit, comprising the steps of:
bonding an integrated circuit die on to a flag portion of a lead frame;
connecting at least one conductor between the integrated circuit die and a post portion of the lead frame;
covering the integrated circuit die, the flag portion, the conductor and the post portion in a fluid polymer material;
at least partly curing/solidifying the polymer material so as to encapsulate the integrated circuit die, the flag portion, the conductor and the post portion;
forming a plastics package around the encapsulated integrated circuit die, flag portion, conductor and post portion.
In a preferred embodiment, the plastics package extends completely over the polymer material.
The polymer material is preferably an epoxy or epoxy acrylate materiheferably, the polymer material is only partly cured so that it provides a surface with good adhesive properties for the plastics package to attach to.
Brief Description Of The Drawings
One embodiment of the invention will now be more fully described, by way of example, with reference to the drawings, of which:
FIG. 1 shows a flow diagram of a packaging process according to the invention; and
FIG. 2 shows a cross-sectional schematic view through an integrated circuit packaged using the process of FIG. 1.
Detailed Description
Referring firstly to FIG.2, a schematic cross sectional view of the packaged integrated circuit 12 is shown. The integrated circuit 12 is mounted on a flag portion 11 of a leadframe. The leadframe also includes lead posts 10 to which are connected electrical connectors or bond wires 13 extending between the posts 10 and the integrated circuit 12. A plastic package A is shown moulded around the lead posts 10, the flag 11, the integrated circuit 12 and the bond wires 13. A polymer material is coated on all surfaces exposed prior to moulding of the package A. The material thus coats the flag 11, as shown at 14, the integrated circuit 12, as shown at 16, the bond wires 13, as shown at 15, and the lead posts 10, as shown at 17.
The material extends only to the edge of the plastic package A.
Thus, as shown FIG. 1, the assembly operation involves the steps of die bonding 1 the integrated circuit die 12 to the flag 11 of the leadframe; electrically connecting the die 12 to the leadframe by way of a wire bond operation 2, performing a pre mould encapsulation process 3, followed by a package moulding operation 4. This is followed by a thermally cured post mould operation 5, after which plating 6 of the exposed leadframe takes place. Package marking 7 then takes place, and finally a trim and form operation 8 shapes the package to it's final state.
The pre mould encapsulation step 3 provides the integrated circuit 12 including the bond pads, the bond wires 13, and the post 10 and flag 11 portions of the leadframe with a coating of polymer material prior to moulding of the plastic package A. In a preferred embodiment the polymer coating is of very low molecular weight and viscosity and wets the integrated circuit, flag and post portions of the leadframe and the bond wires easily. The coating material provides protection of the integrated circuit from corrosion by being chemisorbed onto its surface. This effectively seals any problem in the integrity of the passivation layer preventing moisture ingress, collection and therefore corrosion. The bond pads and bond wires are also protected in a similar way. This protection is not offered by any current technique.
The mould compound used in the production of plastic coated integrated circuits contains various waxes which ensure that the package is easily removed from the mould tool. These waxes coat all metal surfaces which the molten plastic contacts and prevents it adhering to them when cured. The leadframe flag, bond wire and posts are all metal and therefore coated by these waxes preventing good adhesion between them and the plastic package. By coating all metal surfaces contained within the package using the polymer material prior to the moulding process taking place, the waxes contained in the molten plastic do not coat the metal surfaces allowing a good adhesive joint to be created.
In a preferred embodiment the coating is only partially cured prior to moulding and is therefore adhesive in nature forming chemical and physical bonds with all of the coated surfaces. The completion of the curing of the coating occurs during the curing of the molten plastic used to create the package ensuring that a good chemical physical adhesive joint is created as the coating chemically bonds to the curing moulding plastic.
The greater adhesive strength of the interfaces between the plastic package and the leadframe flag, posts, and the bond wires provides much greater resistance to the "popcorn" phenomenon described earlier. Prevention of delamination of the posts and bond wires prevents any direct route for moisture ingress.
In a preferred embodiment the coating maintains a degree of flexibility after curing and during the formation of the plastic package.
The stress created by the difference in the thermal expansion coefficients of the plastic and the integrated circuit and the associated problems discussed earlier are therefore resolved in a similar way to the use of polyimide, that is the flexibility of the coating relieves the stress built up during any temperature cycling or increase that the package experiences.
However, since the pre mould encapsulation is part of the assembly flow and negates the need for a polyimide passivation layer, the problems discussed with the testing of EPROM devices earlier involving the return of wafers to the wafer fab after probe and erase are eliminated. The coating also provides protection of the integrated circuit from filler particle damage acting as a physical barrier in a similar way to a polyimide layer.
It will be appreciated that although only one particular embodiment of the invention has been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of the present invention.
Claims (5)
1. A method of packaging an integrated circuit, comprising the steps of:
bonding an integrated circuit die on to a flag portion of a lead frame;
connecting at least one conductor between the integrated circuit die and a post portion of the lead frame;
covering the integrated circuit die, the flag portion, the conductor and the post portion in a fluid polymer material;
at least partly curing/solidifying the polymer material so as to encapsulate the integrated circuit die, the flag portion, the conductor and the post portion;
forming a plastics package around the encapsulated integrated circuit die, flag portion, conductor and post portion.
2. A method of packaging an integrated circuit according to claim 1, wherein the plastics package is formed so as to extend completely over the polymer material.
3. A method of packaging an integrated circuit according to either claim 1 or claim 2, wherein the polymer material is either an epoxy or epoxy acrylate material.
4. A method of packaging an integrated circuit according to any preceding claim, wherein the polymer material is only partly cured so that it provides a surface with good adhesive properties for the plastics package to attach to.
5. A method of packaging an integrated circuit substantially as hereinbefore described with reference to the drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9424178A GB2295722B (en) | 1994-11-30 | 1994-11-30 | Method of packaging integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9424178A GB2295722B (en) | 1994-11-30 | 1994-11-30 | Method of packaging integrated circuits |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9424178D0 GB9424178D0 (en) | 1995-01-18 |
| GB2295722A true GB2295722A (en) | 1996-06-05 |
| GB2295722B GB2295722B (en) | 1997-12-17 |
Family
ID=10765214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9424178A Expired - Fee Related GB2295722B (en) | 1994-11-30 | 1994-11-30 | Method of packaging integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2295722B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102668140A (en) * | 2009-12-18 | 2012-09-12 | 欧司朗光电半导体有限公司 | Optoelectronic component and method for producing an opto-electronic component |
| DE102014224628A1 (en) * | 2014-12-02 | 2016-06-02 | Ifm Electronic Gmbh | A method of manufacturing a plastic overmolded electronic assembly, such an electronic assembly, and a capacitive sensor |
| DE102015223668A1 (en) | 2014-12-02 | 2016-07-21 | Ifm Electronic Gmbh | Method for producing a molded plastic with plastic assembly, such electronic assembly, and a capacitive sensor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4163072A (en) * | 1977-06-07 | 1979-07-31 | Bell Telephone Laboratories, Incorporated | Encapsulation of circuits |
| EP0258098A1 (en) * | 1986-07-25 | 1988-03-02 | Fujitsu Limited | Encapsulated semiconductor device and method of producing the same |
| US4784872A (en) * | 1984-11-17 | 1988-11-15 | Messerschmitt-Boelkow-Blohm Gmbh | Process for encapsulating microelectronic semi-conductor and layer type circuits |
| US5019419A (en) * | 1988-11-30 | 1991-05-28 | Toshiba Silicone Co. Ltd. | Process for producing an electronic part |
| US5097317A (en) * | 1989-09-08 | 1992-03-17 | Mitsubishi Denki Kabushiki Kaisha | Resin-sealed semiconductor device |
-
1994
- 1994-11-30 GB GB9424178A patent/GB2295722B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4163072A (en) * | 1977-06-07 | 1979-07-31 | Bell Telephone Laboratories, Incorporated | Encapsulation of circuits |
| US4784872A (en) * | 1984-11-17 | 1988-11-15 | Messerschmitt-Boelkow-Blohm Gmbh | Process for encapsulating microelectronic semi-conductor and layer type circuits |
| EP0258098A1 (en) * | 1986-07-25 | 1988-03-02 | Fujitsu Limited | Encapsulated semiconductor device and method of producing the same |
| US5019419A (en) * | 1988-11-30 | 1991-05-28 | Toshiba Silicone Co. Ltd. | Process for producing an electronic part |
| US5097317A (en) * | 1989-09-08 | 1992-03-17 | Mitsubishi Denki Kabushiki Kaisha | Resin-sealed semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102668140A (en) * | 2009-12-18 | 2012-09-12 | 欧司朗光电半导体有限公司 | Optoelectronic component and method for producing an opto-electronic component |
| US9508903B2 (en) | 2009-12-18 | 2016-11-29 | Osram Opto Semiconductors Gmbh | Optoelectronic component and method for producing an optoelectronic component |
| US9768360B2 (en) | 2009-12-18 | 2017-09-19 | Osram Opto Semiconductors Gmbh | Optoelectronic component and method of producing an optoelectronic component |
| DE102014224628A1 (en) * | 2014-12-02 | 2016-06-02 | Ifm Electronic Gmbh | A method of manufacturing a plastic overmolded electronic assembly, such an electronic assembly, and a capacitive sensor |
| DE102015223668A1 (en) | 2014-12-02 | 2016-07-21 | Ifm Electronic Gmbh | Method for producing a molded plastic with plastic assembly, such electronic assembly, and a capacitive sensor |
| DE102014224628B4 (en) * | 2014-12-02 | 2020-12-24 | Ifm Electronic Gmbh | Method for producing an electronic assembly overmolded with plastic, an electronic assembly of this type, and a capacitive sensor |
| DE102015223668B4 (en) | 2014-12-02 | 2022-07-14 | Ifm Electronic Gmbh | Method for producing an electronic assembly overmoulded with plastic, such an electronic assembly, and a capacitive sensor |
| DE102015223668B8 (en) | 2014-12-02 | 2022-09-29 | Ifm Electronic Gmbh | Method for producing an electronic assembly encapsulated with plastic, such an electronic assembly, and a capacitive sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9424178D0 (en) | 1995-01-18 |
| GB2295722B (en) | 1997-12-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19981130 |