GB2293461A - Method for producing field effect transistor - Google Patents

Method for producing field effect transistor Download PDF

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Publication number
GB2293461A
GB2293461A GB9523245A GB9523245A GB2293461A GB 2293461 A GB2293461 A GB 2293461A GB 9523245 A GB9523245 A GB 9523245A GB 9523245 A GB9523245 A GB 9523245A GB 2293461 A GB2293461 A GB 2293461A
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Prior art keywords
photoresist
recess
gate
pattern
mask
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GB9523245A
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GB9523245D0 (en
GB2293461B (en
Inventor
Mitsunori Nakatani
Yoshiki Kojima
Hiroyuki Minami
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority claimed from JP4354580A external-priority patent/JPH06188270A/en
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Publication of GB2293461A publication Critical patent/GB2293461A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A method for producing a field effect transistor comprises: depositing a positive photoresist 2 a semiconductor substrate 1; imagewise exposing the positive photoresist 2; converting the positive photoresist 2 into a negative photoresist and developing to form a pattern 2a having an aperture 3; wet etching the semiconductor substrate 1 using the photoresist pattern 2a as a mask to form a first recess 4; further developing the photoresist pattern 2a to remove areas 21; using the photoresist pattern 2a with the increased overhanging portions as a mask, wet etching the semiconductor substrate 1 to increase the width of the first recess 4 and to form a second recess 4a; and depositing a gate metal to form a gate electrode 5 in the second recess 4a. <IMAGE>

Description

METHOD FOR PRODUCING FIELD EFFECT TRANSISTOR FIELD OF THs INVENTION The present invention relates to a method for producing a field effect transistor (hereinafter referred to as FET) and, more particularly, to a method for producing a recess gate using an asymmetric mask pattern. The invention also relates to a pattern transfer mask used for forming the asymmetric mask pattern.
BACKGROUND OF THE TNVENTTON Figures 9(a) to 9(f) are sectional views illustrating process steps in a prior art method for producing an FET.
Initially, an image reversal photoresist film 2 about 0.6 pm thick is deposited on a semi-insulating GaAs substrate 1 about 600 pm thick including an active region (not shown) about 5000 A thick (figure 9(a)).
Using a mask shown in figures 1O(a)-lO(b), the photoresist film 2 is selectively exposed to light having a wavelength of 0.3 ' 0.4 pm (first exposure step), preferably by conventional photolithographic technique. Then, the photoresist film 2 is subjected to a reversal baking process and a whole surface exposure (second exposure step), whereby a part of the photoresist film 2 which is not exposed to light during the first exposure step is solubilized. This solubilized part is removed during development, resulting in a photoresist pattern 2a with an aperture 3 0.5 - 1 urn wide (figure 9(b)).
The image reversal process is a technique for producing a negative image using a positive photoresist. If a positive photoresist is exposed to light using the mask shown in figures 1O(a)-10(b), since the absorptance of the exposed portion is highest in the vicinity of the surface and gradually decreases with the thickness of the photoresist film, a trapezoid photoresist pattern remains after development. However, if the positive photoresist is reversed to a negative photoresist after the exposure step, the exposed portion remains during the development, resulting in a photoresist pattern having a trapezoid aperture as shown in figure 9(b).
In the step of figure 9(c), the substrate is wet etched with a mixture of phosphoric acid and hydrogen peroxide water or a mixture of tartaric acid and hydrogen peroxide water using the photoresist pattern 2a as a mask (first recess etching), forming a first gate recess 4 (figure 9(c)), Preferably, the first gate recess 4 has a width of 1.4 pm and a depth of 3000 A.
Thereafter, a dry etching is carried out using the photoresist pattern 2a as a mask (second recess etching), forming a second gate recess 4a in the center of the bottom surface of the first gate recess 4 (figure 9(d)).
Preferably, the second gate recess 4a has a width of 0.6 urn and a depth of 1000 A.
A gate metal 5a, such as Al, Ti, or Au, is deposited in the direction perpendicular to the surface of the substrate 1 (figure 9(e)), and the photoresist pattern 2a and the overlying portions 5a of the gate metal are removed by a lift-off technique, resulting in a gate electrode 5 in the second recess 4a (figure 9(f)). Preferably, the gate length is 0.5 pm.
In the above-described Schottky-gate field effect transistor, i.e., metal semiconductor field effect transistor (hereinafter referred to as MESFET), the gate electrode disposed in the recess is not adversely affected by a surface depletion layer due to surface states, reducing the source resistance. In addition, the electric field concentration between the gate and the drain is relaxed, increasing the drain breakdown voltage.
An offset arrangement of the gate electrode in the recess has been well known as a technique for further improving the recessed gate structure. That is, the gate electrode is disposed in the recess toward the source electrode. In this case, since the space between the gate and the source is narrowed, the source resistance is reduced. On the other hand, since the space between the gate and the drain is widened, the drain breakdown voltage is increased.
However, the offset arrangement of the gate electrode is impossible in the process steps illustrated in figures 9(a)-9(f). The reason will be described hereinafter.
Figures 10(a) and 10(b) illustrate a mask employed in the gate pattern transfer step in the above-described production process, in which figure 10(a) is a plan view of the mask and figure 10(b) is a sectional view taken along line B-B of figure 10(a). In the figures, reference numeral 6 designates a glass plate. A light shielding film 7 serving as a gate pattern transfer mask is disposed on a surface of the glass plate 6. Preferably, the light shielding film 7 is made of Cr. The light shielding film 7 includes a portion 7a corresponding to a gate finger (hereinafter referred to as gate finger portion). The width of the gate finger portion 7a is 2.5 - 5 iirn. Reference numerals 6a and 6b designate portions of the glass plate 6 at opposite sides of the gate finger portion 7a.In this gate pattern transfer process, the reduction ratio of the gate pattern transfer mask is 1/5.
Figure 10(c) illustrates an on-wafer intensity profile of light transmitted through the gate pattern transfer mask shown in figures 10(a)-1O(b) during the exposure process.
As shown in figure 10(c), a symmetric profile with the gate finger portion 7a as the center of symmetry is attained.
Figure lO(d) illustrates the relation between the exposure energy of the exposure apparatus and the overhang of the image reversal photoresist pattern 2a in the aperture 3. As shown in figure 10(d), the overhang is approximately in inverse proportion to the exposure energy in a limited range of the exposure energy. An increase in the exposure energy increases the absorptance at the lower part of the photoresist film 2 and decreases the overhang of the photoresist pattern 2a. That is, sufficient exposure energy produces almost vertical side surfaces of the photoresist pattern 2a in the aperture 3.
As described above, when the photoresist pattern of the gate electrode is formed using the pattern transfer mask with the symmetric light shielding film shown in figure 10(a), the photoresist pattern 2a with the symmetric overhanging portions in the aperture 3 is attained.
Therefore, the offset arrangement of the gate electrode in the recess is impossible.
A variety of methods for the offset arrangement of the gate electrode have been proposed. Some of them will be described hereinafter.
In Japanese Published Patent Application No. 2-25039, a photoresist pattern for a gate electrode is formed on a substrate with an active region and source and drain electrodes, and a wet etching is carried out after removing a portion of the photoresist pattern on the drain electrode.
Since the etching rate on the drain electrode side is increased, the width of the recess on the drain electrode side is increased. In this method, however, it is difficult to control the etching rates in the perpendicular and transverse directions during the wet etching and, therefore, the recess shape after the wet etching unfavorably varies, resulting in a variation in the offset position of the gate electrode.
In Japanese Published Patent Application No. 64-86564, a photoresist film is deposited on a substrate having an active region and source and drain electrodes, and an Al film with an aperture of a prescribed width is formed on the photoresist film. Using the Al film as a mask, an energy beam is obliquely applied to the photoresist film, forming a photoresist pattern with asymmetric overhanging portions.
Then, the substrate is selectively etched using the photoresist pattern as a mask, forming in a gate recess having an asymmetric width with respect to the aperture of the Al film. In this method, however, the formation of the mask for the energy beam irradiation, i.e., the Al film with the aperture, complicates the production process. In addition, if a common drain structure is employed, the focusing of the exposure energy beam is difficult, resulting in a variation in the recess shape.
In Japanese Published Patent Applications Nos. 2 267945, 3-145738, and 3-293733, a mask pattern having asymmetric overhanging portions in its aperture is formed on a substrate using a plurality of materials, and the substrate is etched using the mask pattern to form a recess having an asymmetric width with respect to the aperture of the mask. In this method, however, the mask formation process is complicated and the precision in forming the overhanging portions in the aperture of the mask is poor.
In the above-described prior art methods for offset arranging the gate electrode in the recess, the recess etching is not controlled with high precision. In addition, the offset position of the gate electrode in the recess unfavorably varies due to the increased and complicated process steps.
SUMMARY OF TR INVENTION An object of the present invention is to provide a method for producing an FET in which an asymmetric photoresist mask pattern for forming a gate electrode is formed in a relatively simple process and the gate electrode is produced with high stability.
Another object of the present invention is to provide a pattern transfer mask for forming the asymmetric photoresist pattern.
Still another object of the present invention is to provide a relatively simple method for producing a MESFET without using an asymmetric pattern transfer mask, in which the breakdown voltage of the MESFET is increased and a gate electrode is formed with high stability.
Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
According to a first aspect of the present invention, in a method for producing a field effect transistor, a positive photoresist is deposited on a surface of a semiconductor substrate, the positive photoresist is exposed to light having an asymmetric intensity profile with a region of the semiconductor substrate where a gate electrode is to be formed as a center of asymmetry, the positive photoresist is converted into a negative photoresist, the negative photoresist is developed to form a pattern having an aperture opposite the gate electrode formation region of the substrate and asymmetric overhanging portions in the aperture, the semiconductor substrate is wet etched using the photoresist pattern as a mask to form a first recess in the semiconductor substrate, and a gate metal is deposited using the photoresist pattern as a mask to form a gate electrode in the first recess.Therefore, only one exposure process provides the photoresist pattern having asymmetric overhanging portions in the aperture of the pattern.
According to a second aspect of the present invention, a pattern transfer mask comprises a transparent substrate, a linear light shielding film pattern disposed on the transparent substrate, and means for reducing the intensity of light transmitted through a part of the mask on either side of the light shielding film pattern. Therefore, the light applied through the mask to the surface of the photoresist film has an asymmetric intensity profile with the gate electrode formation region as the center of asymmetry.
According to a third aspect of the present invention, in a method for producing a field effect transistor, a positive photoresist is deposited on a surface of a semiconductor substrate, a region of the positive photoresist film opposite to a region of the substrate where a gate electrode is to be formed is exposed to light, the positive photoresist is converted into a negative photoresist, the negative photoresist is developed to form a pattern having an aperture opposite the gate electrode formation region of the substrate and symmetric overhanging portions in the aperture, the semiconductor substrate is wet etched using the photoresist pattern as a mask to form a first recess in the semiconductor substrate, the photoresist pattern is developed to increase the overhanging portions in the aperture, the semiconductor substrate is wet etched using the photoresist pattern with the increased overhanging portions as a mask to increase the width of the first recess and to form a second recess in the first recess, and a gate metal is deposited using the photoresist pattern as a mask to form a gate electrode in the second recess. Therefore, the width of the recess is increased in the relatively simple method.
BRIEF flCRIPTTON OF THE DRAWINGS Figures l(a)-l(e) are sectional views illustrating process steps in a method for producing an FET in accordance with a first embodiment of the present invention.
Figures 2(a) and 2(b) are a plan view and a sectional view illustrating a pattern transfer mask employed in the production process of the first embodiment of the present invention, and figure 2(c) is a diagram illustrating an onwafer intensity profile of light transmitted through the pattern transfer mask of figures 2(a)-2(b).
Figures 3(a)-3(f) are sectional views illustrating process steps in a method for producing an FET in accordance with a second embodiment of the present invention.
Figure 4 is a plan view illustrating a pattern transfer mask in accordance with a third embodiment of the present invention.
Figure 5 is a plan view illustrating a pattern transfer mask in accordance with a fourth embodiment of the present invention.
Figures 6(a) and 6(b) are a plan view and a sectional view illustrating a pattern transfer mask in accordance with a fifth embodiment of the present invention.
Figures 7(a) and 7(b) are a plan view and a sectional view illustrating a pattern transfer mask in accordance with a sixth embodiment of the present invention.
Figures 8(a)-8(g) are sectional views illustrating process steps in a method for producing an FET in accordance with a seventh embodiment of the present invention.
Figures 9(a)-9(f) are sectional views illustrating process steps in a method for producing an FET in accordance with the prior art.
Figures 10(a) and 10(b) are a plan view and a sectional view illustrating a pattern transfer mask employed in the production process of figures 9(a)-9(f), figure 10(c) is a diagram illustrating an on-wafer intensity profile of light transmitted through the pattern transfer mask, and figure 10(d) is a diagram illustrating the relation between the exposure energy and the overhang.
DETAILED DESCRTPTION OF THR PRWFFERD EMBODIMENTS Figures l(a)-l(e) are sectional views illustrating process steps in a method for producing an FET in accordance with a first embodiment of the present invention. Figures 2(a) and 2(b) are a plan view and a sectional view illustrating a gate pattern transfer mask used in the production of the FET, and figure 2(c) illustrates an onwafer intensity profile of light transmitted through the mask of figures 2(a)-2(b). In this first embodiment of the present invention, the overhanging portion 2b2 of the photoresist pattern 2b on the right side of the aperture 3 is larger than the overhanging portion 2b1 on the left side of the aperture 3, the gate recess 40 is wider than the gate recess 4 shown in figure 9(c).
In figure 2(a), the light shielding film 7 has a plurality of projections 7b on a side of the gate finger portion 7a. The space between adjacent projections is about 1 pm and the width of each projection is about lpm. The reduction ratio of the gate pattern transfer mask is 1/5.
A description is given of the production method.
Initially, as illustrated in figure l(a), an image reversal photoresist film 2 about 0.6 pm thick is deposited on a semi-insulating GaAs substrate 1 about 600 pm thick including an active region (not shown) about 5000 A thick.
Using the gate pattern transfer mask shown in figures 2(a)-2(b), the photoresist film 2 is exposed to light by a reducing projection exposure process, such as photolithography (first exposure step). Then, the photoresist film 2 is subjected to a reversal baking process and the whole surface is exposed to light (second exposure step), whereby a portion of the photoresist film 2 that is not exposed to light during the first exposure step, i.e., a portion masked with the light shielding film 7, is solubilized. The solubilized portion of the photoresist film 3 is removed during development, resulting in a gate electrode photoresist pattern 2b with an aperture 3 (figure 2(b)). The width of the aperture 3 is 0.5 - 1 pm.
Since the projections 7b are present on the right side of the gate finger portion 7a of the light shielding film 7, the light intensity on a region of the wafer opposite to the projections 7b of the mask is lowered as shown in figure 2(c).
Therefore, in the photoresist film 2 during the first exposure step, the exposure energy applied to the portion of the photoresist film 2 opposite to the projections 7b of the mask decreases downward, resulting in a difference in the exposures between the upper portion and the lower portion of the photoresist film 2. When the photoresist film 2 is developed after the reversal baking and the second exposure, a portion not exposed to light during the first exposure is solubilized and removed, resulting in the photoresist pattern 2b having the left side overhanging portion 2b1 of about 0.15 pm and the right side overhanging portion 2b2 of about 0.25 - 0.3 pm.
In the step of figure l(c), using the photoresist pattern 2b as a mask, the substrate 1 is wet etched with a mixture of phosphoric acid and hydrogen peroxide water or a mixture of tartaric acid and hydrogen peroxide water, forming a gate recess 40 having a width of 1.5 - 1.55 pm and a depth of about 3000 A.
In the step of figure l(d), a gate metal, such as Al, Ti, or Au, is deposited perpendicularly to the surface of the substrate 1. Thereafter, the photoresist pattern 2b and the overlying portions 5a of the gate metal are removed by a lift-off technique, forming a gate electrode 5 about 0.5 um wide in the recess 40 (figure l(e)).
According to the first embodiment of the present invention, the exposure of the photoresist film 2 is performed using the asymmetric mask pattern shown in figures 2(a)-2(b) that provides the asymmetric intensity profile of the light incident on the photoresist film 2 shown in figure 2(c), thereby forming the photoresist pattern 2b having the asymmetric overhanging portions 2bl and 2b2 in the aperture 3. Therefore, the gate electrode photoresist pattern 2b is produced in the relatively simple process with high precision and high reproducibility, resulting in a MESFET with a reliably offset gate electrode and a high drain breakdown voltage.
Figures 3(a)-3(f) are sectional views illustrating process steps in a method for producing an FET in accordance with a second embodiment of the present invention.
While in the above-described first embodiment the single-stage gate recess is employed, in this second embodiment a two-stage gate recess is employed, i.e., a second gate recess 40a is formed in the first gate recess 40.
The steps illustrated in figures 3(a)-3(c) are identical to those already described with respect to figures 2(a)-2(c) and, therefore, do not require repeated description.
After forming the first gate recess 40 as shown in figure 3(c), a portion of the substrate 1 is dry etched from the bottom surface of the first gate recess 40 using the photoresist pattern 2b as a mask, forming the second gate recess 40a (figure 3(d)). The second gate recess 40a has a width of about 0.6 pm and a depth of about 1000 A.
In the step of figure 3(e), a gate metal, such as Al, Ti, or Au, is deposited perpendicularly to the surface of the substrate 1, and the photoresist pattern 2b and the overlying portions 5a of the gate metal are removed by a lift-off technique, forming a gate electrode 5 0.5 pm wide in the second recess 40a (figure 3(f)).
This two-stage gate recess structure increases the gate breakdown voltage in addition to the effects of the first embodiment of the present invention.
While in the above-described first and second embodiments the gate pattern transfer mask shown in figures 2(a)-2(b) is employed for producing the gate electrode photoresist pattern 2b with the asymmetric overhanging portions 2b1 and 2b2 in the aperture 3, other masks described in the following may be employed with the same effects as described above.
Figure 4 is a plan view illustrating a gate pattern transfer mask according to a third embodiment of the present invention. In this third embodiment, an auxiliary pattern 8 comprising Cr or the like is disposed on the right side of the gate finger portion 7a of the light shielding film 7 parallel to and spaced apart from the gate finger portion 7a. The width of the auxiliary pattern 8 is 1 urn and the space 6a between the gate finger portion 7a and the auxiliary pattern 8 is 1 urn.
Since light incident on the mask of figure 4 is diffracted at the space 6a between the auxiliary pattern 8 and the gate finger portion 7a, the intensity of the light applied to a part of the photoresist film 2 opposite the space 6a of the mask is lowered, resulting in the asymmetric intensity profile on the photoresist film 2 shown in figure 2(c).
Figure 5 is a plan view illustrating a gate pattern transfer mask according to a fourth embodiment of the present invention. In this fourth embodiment, an opaque region 9 about 2 urn wide is formed in the glass substrate 6 along the right side of the gate finger portion 7a of the light shielding film 7. Preferably, the opaque region 9 is formed by selectively implanting Ga ions into that region of the glass substrate 6 using focused ion beam.
When the photoresist film 2 is exposed to light transmitted through the mask of figure 5, since the intensity of the light applied to a part of the photoresist film 2 opposite the opaque region 9 of the mask is lowered, the asymmetric intensity profile of figure 2(c) is attained on the photoresist film 2.
Figures 6(a) and 6(b) are a plan view and a sectional view illustrating a gate pattern transfer mask according to a fifth embodiment of the present invention. In this fifth embodiment, the gate finger portion 7a of the light shielding film 7 has a step portion 7c on its right side.
The step portion 7c is about 2 pm wide and about 500 A thick.
Usually the light shielding film 7 comprising Cr completely shuts off light with the thickness of about 1000 A. The step portion 7c about 500 A thick has the transmissivity of about the half of the transmissivity of the glass substrate 6. Therefore, the asymmetric intensity profile shown in figure 2(c) is attained on the photoresist film.
Figures 7(a) and 7(b) are a plan view and a sectional view illustrating a gate pattern transfer mask according to a sixth embodiment of the present invention. In this sixth embodiment, a semi-transparent film 10 is adhered to the right side of the light shielding film 7a so that a portion of the film 10 lies on the light shielding film 7a. The semi-transparent film 10 has a width of about 2 pm except the overlying portion and does not invert the phase of incident light. Preferably, the semi-transparent film 10 comprises photoresist.
The transmissivity of the semi-transparent film 10 is made about the half of the transmissivity of the glass substrate 6 by appropriately selecting the material and the thickness of the film 10. Also in this case, the asymmetric intensity profile shown in figure 2(c) is attained on the photoresist film 2.
Figures 8(a)-8(g) are sectional views illustrating process steps in a method for producing a MESFET with high drain breakdown voltage. In this method, the conventional gate pattern transfer mask shown in figures 10(a)-10(b) is used in the exposure process.
The steps illustrated in figures 8(a)-8(b) are identical to those already described with respect to figures 9(a)-9(c) and, therefore, do not require repeated description.
After the formation of the first gate recess 4, the photoresist pattern 2a with the aperture 3 is subjected to development again (second development). The lower edge portions 21 of the photoresist pattern 2a are easily solubilized after the reversal baking process because light is not sufficiently absorbed in these portions during the first exposure step. Therefore, these portions 21 are selectively removed during the second development and the opposite overhanging portions of the photoresist pattern 2a in the aperture 3 are increased each by 0.1 - 0.15 pm (figure 8(d)).
Using the photoresist pattern 2a as a mask, the substrate 1 is wet etched to increase the width of the first gate recess 4 and to form a second gate recess 4a in the first gate recess 4 (figure 8(e)). The width of the first gate recess 4 after the wet etching is 1.5 - 1.55 pm. The width and depth of the second gate recess 4a are about 0.6 pm and 1000 A, respectively.
Thereafter, a gate metal 5a, such as Al, Ti, or Au, is deposited perpendicularly to the surface of the substrate 1 (figure 8(f)), and the photoresist pattern 2a and the overlying portions of the gate metal are removed by a liftoff technique, producing a gate electrode 5 about 0.5 urn wide in the second recesS 4a (figure 6(g)).
According to the seventh embodiment of the present invention, since the opposite overhanging portions of the photoresist pattern 2a are increased in the second development performed after the formation of the first gate recess 4 and, thereafter, the width of the first gate recess 4 is increased and the second gate recess 4a is formed by the wet etching. Therefore, an MESFET with a high drain breakdown voltage and a wide gate recess is achieved in the relatively simple production process.
In the above-described embodiments of the present invention, source and drain electrodes are formed on prescribed portions of the substrate 1 before the deposition of the image reversal photoresist. If high impurity ion concentration source and drain regions are previously formed in the substrate, the source and drain electrodes may be formed after the formation of the gate electrode.
While in the above-described embodiments the reducing projection exposure method is employed, the methods and the pattern transfer masks of the present invention may be applied to an equi-magnification exposure method.

Claims (2)

1. A method for producing a field effect transistor comprising: depositing a positive photoresist on a surface of a semiconductor substrate exposing a region of the positive photoresist opposite to a region of the substrate where a gate electrode is to be formed; converting the positive photoresist into a negative photoresist and developing the negative photoresist to form a pattern having an aperture opposite the gate electrode formation region of the substrate and symmetric overhanging portions in the aperture wet etching the semiconductor substrate using the photoresist pattern as a mask to form a first recess in the semiconductor substrate developing the photoresist pattern to increase the overhanging portions in the aperture using the photoresist pattern with the increased overhanging portions as a mask, wet etching the semiconductor substrate to increase the width of the first recess and to form a second recess in the first recess ; and depositing a gate metal using the photoresist pattern as a mask to form a gate electrode in the second recess.
2. The method of claim 1 wherein said positive photoresist is an image reversal photoresist.
GB9523245A 1992-12-15 1993-11-08 Method for producing field effect transistor Expired - Fee Related GB2293461B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4354580A JPH06188270A (en) 1992-12-15 1992-12-15 Manufacture of field effect transistor and pattern transfer mask
GB9322945A GB2273578B (en) 1992-12-15 1993-11-08 Method for producing field effect transistor and pattern mask therefor

Publications (3)

Publication Number Publication Date
GB9523245D0 GB9523245D0 (en) 1996-01-17
GB2293461A true GB2293461A (en) 1996-03-27
GB2293461B GB2293461B (en) 1996-06-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB9523245A Expired - Fee Related GB2293461B (en) 1992-12-15 1993-11-08 Method for producing field effect transistor

Country Status (1)

Country Link
GB (1) GB2293461B (en)

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GB9523245D0 (en) 1996-01-17
GB2293461B (en) 1996-06-12

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