GB2290207A

GB2290207A - Image display system

Info

Publication number: GB2290207A
Application number: GB9508846A
Authority: GB
Inventors: Hiroshi Hattori
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1994-06-09
Filing date: 1995-05-01
Publication date: 1995-12-13
Anticipated expiration: 2015-05-01
Also published as: GB2290207B; GB9508846D0; JPH07334138A

Abstract

An image display system includes an image drawing buffer (13) having a random access port and a serial output port, and a display buffer (14) having two sets of serial ports which can be used for serial input and serial output. An image drawing circuit (12) writes image data into the image drawing buffer (13) via the random access port to effect the initialization of and image drawing of an image for the image drawing buffer (13). A control circuit (11) controls the operations and timings of initialization of and image drawing of an image for the image drawing buffer (13), transfer of image data from the image drawing buffer (13) to the display buffer (14) and transfer of image data from the display buffer (14) to a display (15). The initialization of and the image drawing for the image drawing buffer (13) are alternately and repeatedly effected and transfer of image data from the image drawing buffer to the display buffer (14) is effected before the next initialization effected after completion of the image drawing. Further, image data transferred to the display buffer (14) is repeatedly transferred to the display (15) substantially at all times and displayed thereon. <IMAGE>

Description

IMAGE DISPLAY SYSTEM This invention relates to an image display technique in a computer system, for example, and more particularly to an image display system suitable for image display which requires high-speed display such as image display, motion picture image display or 3-dimensional graphics display in a work station.

For example, in an image display system used for image display in a computer system, it is sometimes required to effect the graphics display such as motion picture image display or animation display, image display or 3-dimensional graphics display, particularly, in a work station at high speed.

in the above image display system for high-speed graphics display, a double buffer system which does not display an image which is now drawn in order to prevent disturbance of the display image and which uses two image buffers is used. The double buffer system uses two image buffers and displays the content of one of the two image buffers while an image is being created and set into the other image buffer. When the drawing process for the latter image buffer is completed, it switches the modes of the image buffers, that is, it sets the latter image buffer for which the image drawing process is completed into a display buffer mode and clears the content of the former image buffer which has been used for display to initialize the same and starts the next image drawing process for the former image buffer.

This type of double buffer system is explained in detail below.

The construction of the double buffer system in a general graphics device is shown in FIG. 1.

A display system shown in FIG. 1 includes a control circuit 1, image drawing circuit 2, first buffer 3, second buffer 4, first switch 5, second switch 6 and display 7. Each of the first and second buffers 3 and 4 is a frame buffer used as an exclusive-use memory into which image drawing data is written and from which image data is read out for display. Generally, each of the first and second buffers 3 and 4 has a random access port and a serial port. Initialization (clearing of image information) and drawing and writing of image data for the first or second buffer 3 or 4 are effected via the random access port thereof and readout of the image data from the first or second buffer 3 or 4 for display is effected via the serial port thereof.

The first switch 5 selects one of the first and second buffers 3 and 4 into which image drawing data is written by the image drawing circuit 2. The second switch 6 selects one of the first and second buffers 3 and 4 from which a display output supplied to the display 7 is read out. The switching operations of the first and second switches 5 and 6 are alternately controlled in a complementary manner by the control circuit 1. That is, the control circuit 1 controls the switching operations such that the second switch 6 selects the second buffer 4 when the first switch 5 selects the first buffer 3 and the second switch 6 selects the first buffer 3 when the first switch 5 selects the second buffer 4.The control circuit 1 controls the image drawing circuit 2 in connection with the operation of the first switch 5 so as to effect the initialization process and image drawing process for the first or second buffer 3 or 4 selected by the first switch 5. The display 7 is a display unit constructed by, for example, a CRT (cathode ray tube) or liquid crystal display panel to display image data as a visible image.

The timing relation between the initialization, image drawing and display of the first and second buffers 3 and 4 is shown in FIG. 2. As shown in FIG. 2, when the first switch 5 selects the first buffer 3 under the control of the control circuit 1, the image drawing circuit 2 effects the initialization process and then image drawing process for the first buffer 3. While the initialization process or image drawing process for the first buffer 3 is being effected, the second switch 6 selects the second buffer 4 under the control of the control circuit 1 and the display output is derived from the second buffer 4 and displayed on the display 7.

When the image drawing process for the first buffer 3 is completed, the control circuit 1 controls the first switch 5 to select the second buffer 4 which has been used for display and the image drawing circuit 2 effects the initialization process and then image drawing process for the second buffer 4. While the initialization process or image drawing process for the second buffer 4 is being effected, the second switch 6 selects the first buffer 3 for which the image drawing process is already completed under the control of the control circuit 1 and the display output is derived from the first buffer 3 and displayed on the display 7.

When the image drawing process for the second buffer 4 is completed, the first buffer 3 which has been used for display is selected by the first switch 5 and the initialization process and image drawing process are effected for the first buffer 3. While the initialization process or image drawing process for the first buffer 3 is being effected, a display output is derived from the second buffer 4 for which the image drawing process is already completed and displayed on the display 7. In the same manner, the operations described above are alternately and repeatedly effected to cyclically effect the initialization, image drawing and display for the buffer. Therefore, the state in which an image is being drawn is not displayed.

As described above, since the first and second buffers 3 and 4 alternately effect the same operations, memories with substantially the same function and construction are used.

However, image data display in the conventional system has the following problem.

Recently, the capacity of image data such as 3-dimensional graphics data or video data used for display becomes larger with an increase in the resolution and, for example, it is required to switch displays of a large number of images such as animation display at a higher speed. For the high-speed display of the images, it is desired to reduce time for initialization (that is, clearing of image information) and image drawing process for the image buffer to minimum and reduce the influence on the image display by the image drawing time. In order to cope with this, for example, the initialization and image drawing operation is independently effected so as not to overlap the display operation as in the double buffer system shown in FIGS. 1 and 2.

In order to attain the still higher speed display of image in the above system, it is considered to use three sets of buffers to construct a triple buffer system. In this case, as shown in FIG. 3, display for the first buffer and initialization are effected while the image drawing process is being effected for the third buffer. Since the initialization for the second buffer is completed while the image drawing process is being effected for the third buffer, the buffer switching operation is effected to permit display for the third buffer and image drawing process for the second buffer when the image drawing process for the third buffer is completed and initialization for the first buffer is effected while the image drawing process is being effected for the second buffer. In this case, since the three operations of image drawing, initialization and display are effected in parallel by use of the three buffers, the higher speed display can be attained, but in general, a video-RAM (random access memory), that is, V-RAM which is a memory used as an image buffer for display is expensive. Further, in a work station dealing with data of high resolution, for example, the capacity and the number of necessary V-RAMs are markedly increased and the occupied area of the buffer in the whole system becomes extremely large.

In a case of a model or system in which the high speed operation is not particularly required, it is sometimes impossible to prepare two V-RAMs of the same specification because of the price thereof and the number of memories even when it is desired to use the double buffer construction to at least stabilize the display. In such a case, it is desired to attain the high-speed operation and stability corresponding to those of the double buffer construction using two V-RAMs of the same specification by use of a device which is less expensive than the V-RAM.

A first aspect of an image display system esxByL2g this invention comprises an image drawing section for drawing image data; a first image buffer for image drawing having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data, image data being drawn and created in the first image buffer by the image drawing section via the random access port; a second image buffer for display having first and second serial ports which can be used for serial input and serial output of image data, for receiving image data stored in the first image buffer for image drawing and transferred from the serial output port via the first serial port; and a display section for receiving image data stored in the second image buffer for display and transferred via the second serial port and displaying the received image data.

In the above image display system, initialization of the first image buffer for image drawing, image drawing and creation of image data, and data transfer from the first image buffer for image drawing to the second image buffer for display may be cyclically effected and image display based on data transfer from the second image buffer for display to the display section may be effected between the initialization of the first image buffer for image drawing after the data transfer and the image drawing and creation of image data for the first image buffer. Further, the data transfer speed for input and output of the second image buffer for display may be set to correspond to the display scanning speed of the display section.

The first image buffer for image drawing may be constructed by a plurality of image buffers for which the image drawing and creation of image data is alternately effected in a complementary manner.

A second aspect of an image display system frt)odyingthis invention comprises an image drawing section for drawing image data; a display section for displaying an image; a first image buffer for image drawing having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data; a second image buffer for display having first and second serial ports which can be used for serial input and serial output of image data; and a control section for controlling the image drawing section to draw and create image data in the first image buffer for image drawing via the random access port, transferring image data stored in the first image buffer for image drawing from the first serial port to the second image buffer for display via the serial output port, and transferring image data stored in the second image buffer for display from the second serial port to the display section and displaying the transferred image data.

The control section may effect the control operation to cyclically repeat initialization of the first image buffer for image drawing, image drawing and creation of image data, and data transfer from the first image buffer for image drawing to the second image buffer for display and effect the data transfer for display from the second image buffer for display to the display section between the initialization of the first image buffer for image drawing after the data transfer and the image drawing and creation of image data for the first image buffer. Further, the control section may have a function of setting the data transfer speed for input and output of the second image buffer for display to correspond to the display scanning speed of the display section.

A third aspect of an image display system embodying this invention comprises an image drawing section for drawing image data; a first image buffer for image drawing having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data, image data being drawn and created in the first image buffer by the image drawing section via the random access port; a second image buffer for image drawing having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data, the first and second image buffers for image drawing being alternately used and image data being drawn and created in the second image buffer by the image drawing section via the random access port; a third image buffer for display having first and second serial ports which can be used for serial input and serial output of image data, for receiving image data items stored in the first and second image buffers for image drawing and alternately transferred from the serial output port via the first serial port when data writing via the random access port is not effected; and a display section for receiving image data stored in the third image buffer for display and transferred via the second serial port and displaying the received image data.

It is possible to effect the operation of transferring image data from the second image buffer for image drawing to the third image buffer for display and initializing the second image buffer for image drawing while image data is being drawn and created for the first image buffer for image drawing, effect the operation of transferring image data from the first image buffer for image drawing to the third image buffer for display and initializing the first image buffer for image drawing while image data is being drawn and created for the second image buffer for image drawing, and alternately and repeatedly effect the above operations and effect the image display based on data transfer from the third image buffer for display to the display section between the periods of data transfer from the first or second image buffer for image drawing to the third image buffer for display. It is also possible to further provide a function of setting the data transfer speed for input and output of the third image buffer for display to correspond to the display scanning speed of the display section.

The image drawing section may include a first image drawing section for effecting the initialization and image drawing for the first image buffer and a second image drawing section for effecting the initialization and image drawing for the second image buffer.

A fourth aspect of an image display system rodyingthis invention comprises an image drawing section for drawing image data; a display section for displaying an image; first and second image buffers for image drawing each having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data; a third image buffer for display having first and second serial ports which can be used for serial input and serial output of image data; and a control section for controlling the image drawing section to alternately draw and create an image in the first and second image buffers for image drawing via the random access port, alternately transferring image data stored in the first and second image buffers for image drawing from the first serial port to the third image buffer for display via the serial output port when data writing from the random access port is not effected, and transferring image data stored in the third image buffer for display from the second serial port to the display section and displaying the transferred image data.

The control section may effect the operation of transferring image data from the second image buffer for image drawing to the third image buffer for display and initializing the second image buffer for image drawing while image data is being drawn and created for the first image buffer for image drawing, effect the operation of transferring image data from the first image buffer for image drawing to the third image buffer for display and initializing the first image buffer for image drawing while image data is being drawn and created for the second image buffer for image drawing, and alternately and repeatedly effect the above operations and effect the image display based on data transfer from the third image buffer for display to the display section between the periods of data transfer from the first or second image buffer for image drawing to the third image buffer for display.Further, the control section may have a function of setting the data transfer speed for input and output of the third image buffer for display to correspond to the display scanning speed of the display section.

In one image display system embodying this invention, at least one image buffer for image drawing having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data and an image buffer for display having first and second serial ports which can be used for serial input and serial output of image data are used to draw and create image data in the image buffer for image drawing via the random access port, transfer image data stored in the image buffer for image drawing from the serial output port to the image buffer for display via the first serial port and transfer image data stored in the image buffer for display to the display section via the second serial port and display the transferred image data, and as a result, the system can be made in a simple construction by use of an inexpensive device, the scale of the buffer in the system can be suppressed and the high-speed operation and high stability can be effectively attained.

That is, the image buffer for display can be formed by use of a small-sized and compact memory which is less expensive than the V-RAM generally used for the image buffer and having only a sequential input/output port like a so-called field memory, and a function substantially equivalent to the function of, for example, the conventional double buffer or triple buffer using only the V-RAM can be attained.

Reference will now be made, by way of example only, to the accompanying drawings, in which: FIG. 1 is a block diagram showing the general construction of an image display system using a previously considered double buffer system; FIG. 2 is a schematic diagram for illustrating the timing of the operation of the image display system of FIG. 1; FIG. 3 is a schematic diagram for illustrating the timing of the operation of an image display system which can be generally designed by use of a triple buffer system; FIG. 4 is a block diagram showing the principle construction of a first embodiment of an image display system embodying-this invention; FIG. 5 is a schematic diagram for illustrating the timing of the operation of the image display system of FIG. 4;; FIG. 6 is a schematic diagram showing a preceding image for illustrating the image display in a case wherein the transfer speed is higher than the display scanning speed in the image display system of FIG. 4; FIG. 7 is a schematic diagram showing a new image for illustrating the image display in a case wherein the transfer speed is higher than the display scanning speed in the image display system of FIG. 4; FIG. 8 is a schematic diagram showing a display image for illustrating the image display in a case wherein the transfer speed is higher than the display scanning speed in the image display system of FIG. 4; FIG. 9 is a schematic diagram showing the data transfer timing for illustrating the image display in a case wherein the transfer speed is higher than the display scanning speed in the image display system of FIG. 4;; FIG. 10 is a schematic diagram showing the data transfer timing for illustrating the image display in a case wherein the transfer speed is the same as the display scanning speed in the image display system of FIG. 4; FIG. 11 is a block diagram showing the construction of a second embodiment of the present invention; FIG. 12 is a schematic diagram for illustrating the timing of the operation of the image display system of FIG. 11; FIG. 13 is a block diagram showing the construction of a third embodiment of the presen;.

invention; and FIG. 14 is a schematic diagram for illustrating the timing of the operation of the image display system of FIG. 13.

FIG. 4 shows the principle construction of an image display system according to a first embodiment of this invention.

The image display system of FIG. 4 is constructed as a double buffer system in a general graphics device and includes a control circuit 11, image drawing circuit 12, image drawing buffer 13, display buffer and display 15.

The image drawing buffer 13 is a buffer into which image data is directly written to draw and create an image and uses a general V-RAM as a frame buffer. That is, the image drawing buffer 13 has a random access port and a serial port. Initialization of the image drawing buffer 13 (clearing of image information) and the image data drawing and writing therefor are effected via the random access port and outputting of image data from the image drawing buffer 13 is effected via the serial port.

The display buffer 14 is a buffer for receiving image data created in the image drawing buffer 13 and transferred from the image drawing buffer 13 and outputting the image data for display and uses a smallsized and compact field memory which is less expensive than the normal V-RAM. That is, the display buffer 14 has two sets of serial ports respectively used as an input port and an output port. Inputting/outputting of image data to or from the display buffer 14 is effected via the serial port. Therefore, image data is transferred from the image drawing buffer 13 to the display buffer 14 via the serial port of the image drawing buffer 13 and the serial port of the display buffer 14.

The serial ports of the image drawing buffer 13 and the display buffer 14 are ports for sequentially inputting/outputting video data. Since the serial ports are generally used for display of video image, video data can be sequentially input or output according to the display scanning at high speed at the video display rate.

The image drawing circuit 12 writes image data into the image drawing buffer 13 via the random access port to effect the initialization of the image drawing buffer 13 and the image drawing therefor. The display 15 displays image data as a visible image by use of a display unit such as a CRT (cathode ray tube) or liquid crystal panel, for example.

The control circuit 11 controls the operations and timings of initialization of the image drawing buffer and the image drawing therefor by the image drawing circuit 12, transfer of image data from the image drawing buffer 13 to the display buffer 14, and transfer of image data from the display buffer 14 to the display 15. That is, the control circuit 11 alternately and repeatedly effects the initialization of the image drawing buffer 13 and the image drawing therefor and transfers image data from the image drawing buffer 13 to the display buffer 14 before the next initialization effected after completion of the image drawing process.

Further, the control circuit 11 repeatedly transfers image data transferred to the display buffer 14 to the display 15 at substantially all times to display the image data.

The timing relation between the initialization, image drawing, transfer and display of the image drawing buffer 13 and display buffer 14 is shown in FIG. 5. The control circuit 11 effects the control operation to effect the image drawing by first causing the image drawing circuit 12 to initialize the image drawing buffer 13 (write initialization data to clear image information) via the random access port and then write image data to create an image. When the image drawing and writing process for the image drawing buffer 13 via the random access port is completed, the written image data is transferred from the image drawing buffer 13 to the display buffer 14 via the serial port by the control of the control circuit 11.That is, image data is transferred from the image drawing buffer 13 to the display buffer 14 via the serial port of the image drawing buffer 13 (which is generally used for outputting image data for display in a frame buffer using a V-RAM or the like) and the serial port of the display buffer 14. Image data transferred to the display buffer 14 is transferred from the serial port of the display buffer 14 to the display 15 for display.

When image data of the image drawing buffer 13 is transferred to the display buffer 14, the image drawing buffer 13 is initialized to make ready for the next image drawing process and next image data is drawn in the image drawing buffer 13 after the initialization.

After this, the same operation is repeatedly effected.

The rate of data transfer from the image drawing buffer 13 to the display buffer 14 is sufficiently high in comparison with the rate of writing data from the random access port to the image drawing buffer 13 for initialization. For this reason, when an image on the entire image plane is sequentially updated, the initialization of the image drawing buffer 13 can be started only if image data of approximately at least first one line is transferred from the image drawing buffer 13 to the display buffer 14. Further, since transfer of image data to the display buffer 14 is effected at high speed and the image data can be displayed during the data transfer, transfer of image data from the display buffer 14 to the display 15 and display of the image data can be successively and repeatedly effected.

If data transfer is effected from the serial port, the data transfer can be effected at higher speed when the serial port of the image drawing buffer 13 is used than when the random access port of the image drawing buffer 13 is used. For this reason, when an image on the entire image plane is sequentially updated, the transfer and initialization can be effected partially in parallel as shown in FIG. 5. For example, if the transfer is sequentially effected from the top portion of the image plane, the initialization can be started from the first line from the random port side of the image drawing buffer 13 when data transfer of the first line is completed.

Transfer between the image drawing buffer 13 (frame buffer) and the display buffer 14 (field memory) can be terminated within approx. 1/60 second, for example, for each image plane (i.e., field or frame) since the transfer rate equivalent to the rate of output from the display buffer 14 to the display 15 can be attained.

However, if the rate of transfer from the image drawing buffer 13 to the display buffer 14 is set excessively high, an image drawing result for a next frame is output and displayed in the course of the scanning operation for displaying the image drawing result for the same frame, thereby momentarily causing a flicker on the image plane as shown in FIGS. 6 to 9.

That is, if an image next to the image of one frame as shown in FIG. 6 is an image of one frame as shown in FIG. 7, the image displayed on the display 15 is switched into the image of FIG. 7 in the course of display of the image of FIG. 6 and an image as shown in FIG. 8 is momentarily displayed. The relation between the line number of display data, the line number of transfer data and the content of display data displayed on the display 15 (in this example, preceding data previously written is "0" and new data newly written is "N") obtained at this time is shown in FIG. 9. As is seen from FIG. 9, the preceding data is displayed in an area from the first line to the fourth line, but when the fourth line is displayed, display image data is switched to newly transferred data and preceding data and new data are displayed in the same frame as shown in FIG. 8.

The presence of new image data and preceding image data in the same frame causes a flicker in the image, but it will not cause a serious problem when no significant difference lies between successive images varying at high speed like a certain type of animation display (motion picture image display). However, when an image output is recorded on a video tape recorder or the like or when the character display image is scrolled, it is generally preferable if such a flicker does not occur.

In order to prevent occurrence of such a flicker, transfer of image data from the image drawing buffer 13 to the display buffer 14 is effected in synchronism with and at the same rate as the display output from the display buffer 14. This causes the same image to be always displayed on the image plane during the scanning operation for each image plane, thus preventing different types of information from being displayed on half portions of the image plane.

If an image to be re-written is part of the image on the image plane, part of the image in the image drawing buffer 13 is initialized after transfer of the image data to the display buffer 14 is completed.

However, in this case, since the image area to be initialized is small and time for initialization is short, no significant influence is given to time for completing the initialization.

Thus, substantially the same display as that of the conventional double buffer construction can be attained by transferring image data from the image drawing buffer 13 to the display buffer 14 at the video display rate.

As an example of a V-RAM which can be used as the image drawing buffer 13, a 2-Mbyte V-RAM of model number of MB818251-70 (made by Fujitsu Ltd.) is available. In the case of this V-RAM, data can be written and read out at the access time of 70 ns for the random access port and 20 ns for the serial port.

Generally, since a display system used in the work station or the like has a vertical synchronization frequency of approx. 76 Hz, the number of scan lines transmitted to the display for every second is approx.

76 x (1024 + a) 80000 (lines/s) if the display resolution is 1280 x 1024, and the number of dots transmitted to the display for every second is approx.

80000 x (1280 + a) 11000000 (dots/s).

Therefore, time for display of each dot necessary for a dot clock for display, that is, display clock is 1/11000000 9.0 (ns/dot). Since a memory cell which can output data at the above rate is not available, it is generally designed to transmit 4 to 5 dots as one group. For example, the data rate becomes 9 x 4 = 36 (ns).

As an example of a field memory which can be used as the display buffer 14, a field memory of model number of HM530281 (made by Hitachi Co.) is available. In the case of this memory, the access time for the asynchronous input/output serial port is 20 ns.

In a case where the system of FIG. 4 is constructed by use of the above elements and if the serial port is operated at the rate of 4-dot clock (36 ns), transfer of image data on the entire image plane from the image drawing buffer 13 to the display buffer 14 can be effected at the same rate as transmission of image data for display and can be completed in 1/76 second.

As described above, in the image display system of FIG. 4, at least one image buffer for image drawing having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data and an image buffer for display having first and second serial ports which can be used for serial input and serial output of image data are used to draw and create image data in the image buffer for image drawing via the random access port by the image drawing section, transfer image data stored in the image buffer for image drawing from the serial output port to the image buffer for display via the first serial port and transfer image data stored in the image buffer for display to the display section via the second serial port and display the transferred image data.Therefore, an image display system which can be made in a simple construction by use of an inexpensive device and in which the scale of the buffer can be suppressed and the high-speed operation and high stability can be effectively attained can be provided.

That is, in the image display system of FIG. 4, the image buffer for display can be formed by use of a small-sized and compact memory which is less expensive than the V-RAM generally used for the image buffer and having only a sequential input/output port like a socalled field memory, and a function substantially equivalent to the function of, for example, the previously considered double buffer or triple buffer using only the V-RAM can be attained.

FIG. 11 shows the construction of an image display system according to a second embodiment of this invention.

The image display system of FIG. 11 is constructed as a triple buffer system and includes a control circuit 21, image drawing circuit 22, first image drawing buffer (which is hereinafter referred to as an "image drawing A buffer") 23, second image drawing buffer (which is hereinafter referred to as an "image drawing B buffer") 24, first switch 25, second switch 26, display buffer 27 and display 28.

Each of the image drawing A buffer 23 and image drawing B buffer 24 is a buffer for drawing and creating an image by directly writing image data therein by the image drawing circuit 21 and is constructed by use of a V-RAM as a field buffer. That is, each of the image drawing A buffer 23 and image drawing B buffer 24 has a random access port and a serial port. The operation of drawing and writing image data into the image drawing A buffer 23 and image drawing B buffer 24 is effected via the random access port and outputting of image data from the image drawing A buffer 23 and image drawing B buffer 24 is effected via the serial port.

For example, in some V-RAMs, initialization can be effected at high speed by use of the serial port by previously setting initialization data and supplying a clock. This type of V-RAM is used in the image drawing A buffer 23 and image drawing B buffer 24 of FIG. 11.

In this case, initialization (clearing of image information) of the image drawing A buffer 23 and image drawing B buffer 24 is effected via the serial port not by the image drawing circuit 22 but by the control circuit 21.

The first switch 25 selects one of the image drawing A buffer 23 and image drawing B buffer 24 for which the image drawing circuit 22 draws and creates an image. The second switch 26 selects one of the image drawing A buffer 23 and image drawing B buffer 24 from which a transfer output to the display buffer 27 is derived. The switching operations of the first and second switches 25 and 26 are alternately effected in substantially a complementary manner by the control circuit 21.

When the first switch 25 selects the image drawing A buffer 23, the control circuit 21 initializes the image drawing B buffer 24 at high speed after the second switch 26 selects the image drawing B buffer 24 to transfer image data therefrom. When high-speed initialization of the image drawing B buffer 24 is completed, the control circuit 21 switches the switching positions of the first and second switches 25 and 26 to respectively select the image drawing B buffer 24 and the image drawing A buffer 23. The control circuit 21 effects the control operation to cause the second switch 26 to select the image drawing A buffer 23 when the first switch 25 selects the image drawing B buffer 2.

That is, the control circuit 21 controls the image drawing circuit 22 in synchronism with the switching operation of the first switch 25 to effect the image drawing operation for one of the image drawing A buffer 23 and image drawing B buffer 24 which is selected by the first switch 25, causes image data of one of the image drawing A buffer 23 and image drawing B buffer 24 which is selected by the second switch 26 to be transferred to and displayed on the display buffer 27, and rapidly initializes one of the image drawing A buffer 23 and image drawing B buffer 24 in which data transfer is completed.

The display buffer 27 is a buffer for receiving image data drawn in the image drawing A buffer 23 or image drawing B buffer 24 and transferred from the image drawing A buffer 23 or image drawing B buffer 24 via the second switch 26, and outputting the received image data to be displayed. As the display buffer 27, a smallsized and compact field memory which is less expensive than the normal V-RAM is used. That is, the display buffer 27 has two sets of serial ports which can be respectively used as the input port and output port.

Inputting/outputting of image data of the display buffer 27 is effected via the serial port. Therefore, image data is transferred from the image drawing A buffer 23 or image drawing B buffer 24 to the display buffer 27 via the serial port of the image drawing A buffer 23 or image drawing B buffer 24, second switch 26 and the serial port of the display buffer 27 and is further transferred from the display buffer 27 to the display 28 via the serial port of the display buffer 27.

Video data can be sequentially input or output with respect to the serial ports of the image drawing A buffer 23, image drawing B buffer 24 and display buffer 27 at high speed at the video display rate according to the display scanning.

The image drawing circuit 22 writes image data into the image drawing A buffer 23 or image drawing B buffer 24 via the random access port to draw an image and writes the image into the image drawing A buffer 23 or image drawing B buffer 24. The display 28 displays the image data as a visible image by use of display unit such as a CRT (cathode ray tube) or liquid crystal panel, for example.

The control circuit 21 controls the operations and timings of switching of the switching positions of the first and second switches 25 and 26 as described before, drawing of an image into the image drawing A buffer 23 or image drawing B buffer 24 by the image drawing circuit 22, transfer of image data from the image drawing A buffer 23 or image drawing B buffer 24 to the display buffer 27, and transfer of image data from the display buffer 27 to the display 28.That is, the control circuit 21 alternately and repeatedly effects the drawing operation for the image drawing A buffer 23 and image drawing B buffer 24 and effects transfer of image data of one of the image drawing A buffer 23 and image drawing B buffer 24 to the display buffer 27 and initialization of the buffer while the drawing operation for the other of the image drawing A buffer 23 and image drawing B buffer 24 is being effected. Transfer of image data from the image drawing A buffer 23 or image drawing B buffer 24 to the display buffer 27 is effected before the next initialization effected after the drawing operation for the image drawing A buffer 23 or image drawing B buffer 24 is completed. Further, the control circuit 21 causes image data transferred to the display buffer 27 to be repeatedly transferred to the display 28 for display substantially at all times.

The timing relation between the initialization, image drawing, transfer and display of the image drawing A buffer 23, image drawing B buffer 24 and display buffer 27 is shown in FIG. 12. Indications "r" and "s" in the image drawing A buffer 23 and image drawing B buffer 24 respectively indicate the random access port and serial port and indications "i" and "o" in the display buffer 27 indicate the input and output serial ports. By the control operation of the control circuit 21, the image drawing circuit 22 first effects the image drawing operation by writing image data into the image drawing A buffer 23 via the random access port to create an image therein. During the image drawing operation, the control circuit 22 effects the high-speed initialization of the image drawing A buffer 23 by use of the serial port.When the image drawing operation for the image drawing A buffer 23 via the random access port is completed, the written image data is transferred from the image drawing A buffer 23 to the display buffer 27 via the serial port by the control operation of the control circuit 21. That is, image data is transferred from the image drawing A buffer 23 to the display buffer 27 via the serial port of the image drawing A buffer 23 and the serial port of the display buffer 27. Image data transferred to the display buffer 27 is transferred from the serial port of the display buffer 27 to the display 28 for display. When image data of the image drawing A buffer 23 is transferred to the display buffer 27, the image drawing A buffer 23 is initialized at high speed by use of the serial port for the next image drawing.In a period between the data transfer from the image drawing A buffer 23 and the initialization thereof, the image drawing operation for the image drawing B buffer 24 is effected. After the initialization of the image drawing A buffer 23, next image data is drawn into the image drawing A buffer 23.

After this, the same operation is repeatedly effected.

Since data transfer from the image drawing A buffer 23 or image drawing B buffer 24 to the display buffer 27 is effected at high speed and image data can be displayed during the data transfer, transfer of image data from the display buffer 27 to the display 28 and display of the image data are successively and repeatedly effected.

In the image display system of FIG. 11, it is possible to make a triple buffer construction by transferring outputs of the image drawing A buffer 23 and the image drawing B buffer 24 of the normal double buffer construction to the display 28 via the display buffer 27 and effect data transfer and high-speed initialization for one of the image drawing A buffer 23 and image drawing B buffer 24 during the image drawing operation for the other of the image drawing A buffer 23 and image drawing B buffer 24, thereby making it possible to enhance the performance of the entire system.

Initialization of the image drawing buffer using the serial port described above is suitable for a case wherein an image on the entire image plane is sequentially changed and displayed. However, in a case where part of an image on the image plane is re-written and displayed like a case wherein the content of part of the windows in a so-called multiwindow system is rewritten and displayed, initialization must be effected for a specified part of the image plane and it must be effected via the random access port. An embodiment suitable for the above case is explained below.

FIG. 13 shows the construction of a third embodiment of the present invention.

The image display system of FIG. 13 is constructed as a triple buffer system and includes a control circuit 31, first image drawing circuit (which is hereinafter referred to as an A-image drawing circuit) 32, second image drawing circuit (which is hereinafter referred to as a B-image drawing circuit) 33, first image drawing buffer (which is hereinafter referred to as an image drawing A buffer) 34, second image drawing buffer (which is hereinafter referred to as an image drawing B buffer) 35, switch 26, display buffer 27 and display 28. The switch 26, display buffer 27 and display 28 are substantially the same as the corresponding portions of FIG. 11.

Each of the image drawing A buffer 34 and image drawing B buffer 35 is a buffer into which image data is directly written by a corresponding one of the A-image drawing circuit 32 and B-image drawing circuit 33 to draw and create an image and is constructed by use of a normal V-RAM as a frame buffer. That is, each of the image drawing A buffer 34 and image drawing B buffer 35 has a random access port and a serial port. The operation of drawing image data into the image drawing A buffer 34 and image drawing B buffer 35 is effected via the random access port and outputting of image data from the image drawing A buffer 34 and image drawing B buffer 35 is effected via the serial port.In this case, initialization of the image drawing A buffer 34 and image drawing B buffer 35 (clearing of the image plane) is effected by directly writing initialization data by the A-image drawing circuit 32 and B-image drawing circuit 33 via the random access ports thereof like the image drawing operation.

Initialization of and data writing into the image drawing A buffer 34 and image drawing B buffer 35 by the A-image drawing circuit 32 and B-image drawing circuit 33 are effected under the control of the control circuit 31.

The switch 26 selects one of the image drawing A buffer 34 and image drawing B buffer 35 from which a transfer output to the display buffer 27 is derived.

The switching operation of the switch 26 is controlled by the control circuit 31.

When the control circuit 31 causes the A-image drawing circuit 32 to effect the image drawing operation for the image drawing A buffer 34, it sets the switch 26 to select the image drawing B buffer 35 and causes the image drawing B buffer 35 to transfer data to the display buffer 27, and then causes the B-image drawing circuit 33 to initialize the image drawing B buffer 35.

After initialization of the image drawing B buffer 35 by the B-image drawing circuit 33 is completed, the control circuit 31 causes the B-image drawing circuit 33 to effect the image drawing operation for the image drawing B buffer 35. Further, after initialization of the image drawing B buffer 35 by the B-image drawing circuit 33 is completed, the control circuit 31 changes the switching position of the switch 26 to select the image drawing A buffer 34 and causes the image drawing A buffer 34 to transfer the content thereof to the display buffer 27, and after completion of this transfer, it causes the A-image drawing circuit 32 to initialize the image drawing A buffer 34. The data transfer from and initialization of the image drawing A buffer 34 and the image drawing operation for the image drawing B buffer 35 are effected in the same period.

That is, the control circuit 31 controls the A-image drawing circuit 32, B-image drawing circuit 33, image drawing A buffer 34, and image drawing B buffer 35 so as to cause the A-image drawing circuit 32 and B-image drawing circuit 33 to alternately effect the image drawing operations for the respective image drawing A buffer 34 and image drawing B buffer 35, causes the switch 26 to select one of the image drawing A buffer 34 and image drawing B buffer 35 for which the image drawing operation is not effected and causes image data of the selected buffer to be transferred to the display buffer 27 for display via the switch 26, and causes the A-image drawing circuit 32 or B-image drawing circuit 33 to initialize a corresponding one of the image drawing A buffer 34 and image drawing B buffer 35 in which data transfer is completed.

The display buffer 27 is a buffer for receiving image data which is created by the image drawing A buffer 34 or image drawing B buffer 35 and transferred via the switch 26 and outputs the image data for display. As the display buffer 27, a small-sized and compact field memory which is less expensive than the normal V-RAM is used. That is, the display buffer 27 has two sets of serial ports which can be respectively used as the input port and output port.

Inputting/outputting of image data of the display buffer 27 is effected via the serial port. Therefore, image data is transferred from the serial port of the image drawing A buffer 34 or image drawing B buffer 35 to the display buffer 27 via the switch 26 and the serial port of the display buffer 27 and is further transferred from the display buffer 27 to the display 28 via the serial port of the display buffer 27. The serial ports of the image drawing A buffer 34, image drawing B buffer 35 and display buffer 27 can sequentially input or output video data at high speed at the video display rate according to the display scanning.

The A-image drawing circuit 32 and B-image drawing circuit 33 effect the initialization of and image data drawing operation for the image drawing A buffer 34 and image drawing B buffer 35 via the respective random access ports As described before, the control circuit 31 controls the operations and timings of switching of the switching position of the switch 26, drawing and writing of an image into the image drawing A buffer 34 and image drawing B buffer 35 by the A-image drawing circuit 32 and B-image drawing circuit 33, transfer of image data from the image drawing A buffer 34 or image drawing B buffer 35 to the display buffer 27, and transfer of image data from the display buffer 27 to the display 28.

That is, the control circuit 31 alternately and repeatedly effects the drawing operation for the image drawing A buffer 34 and image drawing B buffer 35 by the A-image drawing circuit 32 and B-image drawing circuit 33 and effects transfer of image data of one of the image drawing A buffer 34 and image drawing B buffer 35 to the display buffer 27 and initialization of the buffer while the drawing operation for the other of the image drawing A buffer 34 and image drawing B buffer 35 is being effected. Transfer of image data from the image drawing A buffer 34 or image drawing B buffer 35 to the display buffer 27 is effected before the next initialization effected after the drawing operation for the image drawing A buffer 34 or image drawing B buffer 35 is completed. Further, the control circuit 31 causes image data transferred to the display buffer 27 to be repeatedly transferred to the display 28 for display substantially at all times.

The timing relation between the initialization, image drawing, transfer and display of the image drawing A buffer 34, image drawing B buffer 35 and display buffer 27 is shown in FIG. 14. Indications "r" and "s" in the image drawing A buffer 34 and image drawing B buffer 35 respectively indicate the random access port and serial port and indications "i" and "o" in the display buffer 27 respectively indicate the input and output serial ports. The case of FIG. 14 is different from the case of FIG. 12 in that initialization of the image drawing A buffer 34 and image drawing B buffer 35 is effected not by use of the serial port but by use of the random access port.

If the range of the image plane to be re-written is part of the image plane, time for initialization and image drawing can be made short, and if the range of the image plane to be re-written is the entire portion on the image plane, time for initialization and image drawing will be made longer. Therefore, in this system, in a case where the range of the image plane to be rewritten is part of the image plane, re-writing and display of the image plane can be efficiently effected.

In the image display system of FIG. 14, it is possible to make a triple buffer construction by transferring outputs of the image drawing A buffer 34 and image drawing B buffer 35 of the normal double buffer construction to the display 28 via the display buffer 27 and enhance the performance of the entire system.

It is apparent that, in this invention, a wide range of different working modes can be formed based on the invention without deviating from the spirit and scope of the invention.

Claims

1. An image display system comprising: image drawing means for drawing image data; a first image buffer having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data, image data being drawn and created in said first image buffer by said image drawing means via the random access port; a second image buffer having first and second serial ports which can be used for serial input and serial output of image data, for receiving image data stored in said first image buffer and transferred from the serial output port via the first serial port; and display means for receiving image data stored in said second image buffer for display and transferred via the second serial port and displaying the received image data.

2. An image display system according to claim 1, wherein initialization of said first image buffer, image drawing and creation of image data, and data transfer from said first image buffer to said second image buffer are cyclically effected and image display based on data transfer from said second image buffer to said display means is effected between the initialization of said first image buffer effected after the data transfer and the image drawing and creation of image data for said first image buffer.

3. An image display system according to claim 2, further comprising means for setting the data transfer speed for input and output of said second image buffer to correspond to the display scanning speed of said display means.

4. An image display system according to claim 1, wherein said first image buffer is constructed by a plurality of image buffers for which the image drawing and creation of image data is alternately effected in a complementary manner.

5. An image display system comprising: image drawing means for drawing image data; display means for displaying an image; a first image buffer having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data; a second image buffer having first and second serial ports which can be respectively used for serial input and serial output of image data; and control means for controlling said image drawing means to draw and create image data in said first image buffer via the random access port, transferring image data stored in said first image buffer from the first serial port to said second image buffer via the serial output port, and transferring image data stored in said second image buffer from the second serial port to said display means and displaying the transferred image data.

6. An image display system according to claim 5, wherein said control means further includes means for effecting the control operation to cyclically and repeatedly effect initialization of said first image buffer, image drawing and creation of image data, and data transfer from said first image buffer to said second image buffer and effect the data transfer for display from said second image buffer to said display means between the initialization of said first image buffer effected after the data transfer and the image drawing and creation of image data for said first image buffer.

7. An image display system according to claim 6, wherein said control means further includes means for setting the data transfer speed for input and output of said second image buffer to correspond to the display scanning speed of said display means.

8. An image display system according to claim 5, wherein said first image buffer is constructed by a plurality of image buffers for which the image drawing and creation of image data is alternately effected in a complementary manner.

9. An image display system comprising: image drawing means for drawing image data; a first image buffer having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data, image data being drawn and created in said first image buffer by said image drawing means via the random access port; a second image buffer having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data, said first and second image buffers being alternately used and image data being drawn and created in said second image buffer by said image drawing means via the random access port;; a third image buffer having first and second serial ports which can be used for serial input and serial output of image data, for receiving image data items stored in said first and second image buffers and alternately transferred from the serial output ports thereof via the first serial port when data writing via the random access port is not effected; and display means for receiving image data stored in said third image buffer and transferred via the second serial port and displaying the received image data.

10. An image display system according to claim 9, wherein the operation of transferring image data from said second image buffer to said third image buffer and initializing said second image buffer is effected while image data is being drawn and created for said first image buffer, the operation of transferring image data from said first image buffer to said third image buffer and initializing said first image buffer is effected while image data is being drawn and created for said second image buffer, and the above operations are alternately and repeatedly effected and the image display based on data transfer from said third image buffer to said display means is effected between the periods of data transfer from said first or second image buffer to said third image buffer.

11. An image display system according to claim 10, further comprising means for setting the data transfer speed for input and output of said third image buffer to correspond to the display scanning speed of said display means.

12. An image display system according to claim 9, wherein said image drawing means includes first image drawing means for effecting initialization of and image drawing and creation for said first image buffer, and second image drawing means for effecting initialization of and image drawing and creation for said second image buffer.

13. An image display system comprising: image drawing means for drawing image data; display means for displaying an image; first and second image buffers each having at least a random access port which can be used for writing image data and a serial output port which can be used for serial output of image data; a third image buffer having first and second serial ports which can be used for serial input and serial output of image data; and control means for controlling said image drawing means to alternately draw and create an image in said first and second image buffers via the random access port, alternately transferring image data stored in said first and second image buffers from the first serial port to said third image buffer via the serial output port when data writing from the random access port is not effected, and transferring image data stored in said third image buffer from the second serial port to said display means and displaying the transferred image data.

14. An image display system according to claim 13, wherein said control means includes means for effecting the operation of transferring image data from said second image buffer to said third image buffer and initializing said second image buffer while image data is being drawn and created for said first image buffer, effecting the operation of transferring image data from said first image buffer to said third image buffer and initializing said first image buffer while image data is being drawn and created for said second image buffer, and alternately and repeatedly effecting the above operations, and means for effecting the image display based on data transfer from said third image buffer to said display means between the periods of data transfer from said first or second image buffer to said third image buffer.

15. An image display system according to claim 14, wherein said control means further includes means for setting the data transfer speed for input and output of said third image buffer to correspond to the display scanning speed of said display means.

16. An image display system substantially as herinbefore described with reference to the accompanying drawings ,