GB2247780A - Fabricating a bipolar transistor - Google Patents
Fabricating a bipolar transistor Download PDFInfo
- Publication number
- GB2247780A GB2247780A GB9100672A GB9100672A GB2247780A GB 2247780 A GB2247780 A GB 2247780A GB 9100672 A GB9100672 A GB 9100672A GB 9100672 A GB9100672 A GB 9100672A GB 2247780 A GB2247780 A GB 2247780A
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- forming
- layer
- oxide layer
- etching
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- 238000000151 deposition Methods 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- 230000008021 deposition Effects 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 13
- 238000000206 photolithography Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- -1 phosphorous ions Chemical class 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of making a bipolar transistor comprises forming a buried layer 5 and an epitaxial layer 6 on a silicon substrate, forming a well region 10 by ion implantation in the epitaxial layer, forming a diffusion layer 17 in the well region. forming a base region by ion implantation, depositing an oxide layer 21, forming a contact window by etching the oxide layer, forming a polysilicon layer by a temperature ramp-up process, forming an emitter region by ion implantation and forming the base 27 and emitter 28 simultaneously by diffusion of the implanted impurities. The contact window for forming the emitter is formed by reactive ion etching the oxide layer and the substrate surface damaged during the etching is subjected to plasma enhanced C.V.D. The polysilicon layer is then deposited by ramping up the temperature in the deposition apparatus to prevent the formation of oxide, thereby ensuring that the emitter resistance is kept low. <IMAGE>
Description
FABRICATING A POLYEMITTER BIPOLAR TRANSISTOR This invention relates to a
process for fabricating a polyemitter bipolar transistor with a low resistance. In particular, it relates to a process for decreasing the high resistance value produced when forming the polyemitter.
The polysilicon emitter is widely used in high performance and high speed bipolar transistors as well as in BI-CMOS devices.
In order to fabricate a bipolar transistor with a polyemitter structure, the oxide layer formed on a single crystal silicon substrate is removed and a polysilicon layer forming an electrode is deposited which contacts the substrate. However, two problems are encountered in oxide layer removal and polysilicon layer deposition.
First, the problem when removing the oxide layer formed on the single crystal Si substrate is that the oxide layer is removed by reactive ion etching, and thus the surface of the substrate is damaged, thereby increasing emitter resistance.
The problem encountered when depositing the polysilicon on the substrate will now be considered. Polysilicon layer deposition is achieved by a conventional deposition method or a ramp-up deposition method.
1. Conventional Deposition The conventional method is that the wafer is brought into a tube at a high temperature of 600-6500C for polysilicon deposition. An oxide layer grows on the single crystal Si substrate due to the high temperature of the tube. Hence, although the oxide layer has been removed from the substrate in the preceding step, the subsequent processing step for depositing a polysilicon causes an oxide layer to grow on the substrate, thus hindering contact of the polysilicon layer with the substrate. Furthermore, the oxide layer formed between the polysilicon layer and the substrate causes the emitter resistance to increase, so that characteristics of the transistor such as low operating speed and low transconOUctance deteriorate.
In order to remove the unwanted oxide layer formed during polysilicon deposition, a separate heat treatment is required, typically using a high tpamperature exceeding 9000C that employs a heat treatment step using, for example, a diffusion tube, a rapid thermal annealing step, or other means. However, the heat treatment employing the diffusion tube tends to deteriorate device performance because of the thermal energy resulting from the long duration of the high temperature process, while the rapid thermal annealing degrades the uniformity and productivity of the process despite the thermal energy applied to the device being low due to a relatively short processing time.
2. Ramp-Up Deposition This is a method more recently developed for preventing the oxide layer from growing while the wafer is brought into a high temperature diffusion tube. The temperature of the tube is maintained at room temperature when the wafer is brought into the polysilicon diffusion tube. The temperature is increased up to a high level of 600-6500C in order to deposit a polysilicon after the wafer has been completely brought into the tube. However, this method encounters a problem with the productivity due to the increase of the temperature-from low to high level.
An object of the present invention is to provide a process for fabricating a polyemitter bipolar transistor which can reduce the emitter resistance by etching the oxide layer present on the single crystal j -1 silicon substrate before depositing the polysilicon layer and then dry- etching by the plasma enhanced CVD method the single crystal silicon substrate damaged when etching the oxide layer.
Another object of the present invention is to provide a process for fabricating a polyemitter bipolar transistor which can reduce the emitter resistance by maintaining a temperature of a deposition tube at a low level by means of the ramp-up deposition method when the wafer is brought into the tube, and by depositing a polysilicon layer in an increased deposition temperature suitable for the polysilicon layer after the wafer has been completely brought into the tube in order to suppress the growth of an unwanted oxide layer.
According to the present invention, there is provided a process for fabricating a bipolar transistor with a low emitter resistance, comprising the steps of: forming an N+ buried layer and an N- type epitaxial layer on an Si substrate; forming an N- type well for the region of the bipolar transistor by performing ion implantation of an N- type impurity on the epitaxial layer; forming a field oxide layer by a conventional oxidation; forming an N+ diffusion layer in a collector region; forming an ion implanted layer for a base region by performing ion implantation of a Ptype impurity; depositing an oxide layer; forming a contact window by etching the oxide; forming a polypattern by patterning after depositing a polysilicon layer by ramp-up deposition processing; performing ion implantation on the substrate so as to form an emitter region; forming the base region and emitter region by diffusing the ion implanted impurities at the same time; forming an oxide layer and BPSG layer; forming a metal contact window by sequentially etching the BPSG and oxide layers by photolithography; and forming a metal electrode pattern by depositing a metal layer and patterning.
According to one embodiment of the present invention, the step for forming the contact window for contacting the single crystal Si substrate with the polysilicon layer comprises the substeps of: depositing a photoresist on the oxide layer, exposing a portion of the substrate for forming a contact window by etching the photoresist by photolithography; etching the oxide layer by reactive ion etch; and etching by the plasma CVD method the single crystal silicon substrate damaged during etching of the oxide layer.
According to another aspect of the present invention, when depositing the polysilicon, the temperature of a deposition tube is maintained so low as to be about 4000C while the wafer is brought into the tube, and after the wafer has been completely brought into the tube, the temperature is gradually increased up to the level of the normal polysilicon deposition temperature.
Embodiments of the invention will now be describe, by way of example only, with reference to the accompanying drawings in which:
Figures IA-1N illustrate a process for fabricating a polyemitter bipolar transistor.
Referring to Figure IA which illustrates a buried layer being formed, the starting material is a p-type Si substrate 1 with specific resistance of 5n.cm and crystal plane of <100>. On the substrate I are sequentially deposited a first oxide layer 2 and nitride layer 3.
Then, a photoresist is applied onto the nitride layer 3, and the substrate is subjected to a photolithography process to form a window 4 for ion implantation. N- type impurity As is then implanted through this window 4 at a dose of 5 x 1515 ions/cm2 to form an ion implanted layer 51 for an N+ buried layer. Then, the photoresist is 1 removed.
Referring to Figure 1B, the implanted ions are driven in a conventional oxidizing process for forming the N+ buried layer 5. The first oxide layer 2 and nitride layer 3 are then stripped off and epitaxial layer 6 with & thickness of about 1.5 gm is grown on the substrate.
Then, on the epitaxial layer 6 are sequentially deposited a second oxide layer 7 and nitride layer 8, and a photoresist is applied onto the nitride layer. The substrate is subjected to the photolithography process to form a window 9 for ion implantation to form a collector region.
N- type impurity of phosphorous (P) ion is then implanted through the window 9 at a dose of 1 x 1012 to 3 x 10 12 ions/cm2 to form an N- type well 10 where a bipolar transistor is formed, as shown in Figure 1C. Then, the photoresist applied to form the window 9 is removed, and a third oxide layer 11 and nitride layer 12 are sequentially formed to form a field oxide layer.
Referring to Figure 1D which illustrates the isolation of active element region by forming a field oxide layer, a photoresist 13 is applied onto the third nitride layer 12, which is subjected to the photolithography process to etch the portion of the nitride layer 12 where the field nitride is to be formed.
Referring to Figure 1E, after removing the photoresist 13, a conventional oxidation process is performed on the substrate to form the field oxide layer
14, then third nitride layer 12 is removed.
Referring to Figure 1F which illustrates the process for forming an N+ diffusion in the collector region 10, a photoresist 15 is again applied to the substrate, which in turn is subjected to the photolithograph process to form a window 16 for ion 1 implantation.
The phosphorous ions are implanted through the window 16 into the collector region 10 at a dose of 3 x 1015 - 5 x 1015 ions/C.M2 to form an N+ diffusion layer 17 for decreasing the collector resistance, and the photoresist 15 is removed.
Referring to Figure 1G which illustrates the process for forming a base region, a photoresist 18 is applied to the substrate, which in turn is subjected to the photolithography process to form a window 19. Boron (B) is then implanted at a dose of 1 x 1013 - 3 x 1013 ions/cM2 to form an ion implanted layer 20, and the photoresist 18 is removed.
Figures 1H and 1I show contact window formation process for contacting the single crystal silicon substrate with the polysilicon layer to be formed from the following process.
Referring to Figure IH, an oxide layer 21 and photoresist 22 are sequentially deposited on the substrate, which in turn is subjected to a photolithography process to etch the photoresist 22 so as to expose the portion of the oxide layer 21 where a contact window is to be formed.
Referring to Figure 1I, the portion of the oxide layer 21 is removed by reactive ion etch to form the contact window 23. At this time, the exposed portion of the single crystal Si substrate is damaged, which is indicated by the reference numeral 24.
Referring to Figure 1J which illustrates the h process for forming a polysilicon layer for emitter contact, the single crystal Si layer 24 in the contact window 23 is etched by a plasma enhanced WD method to expose an undamaged and clean portion 25, and the photoresist 22 is removed.
Thereafter, ramp-up processing is employed to w deposit a polysilicon layer 26 on the substrate. In this case, when the wafer is being brought into the deposition tube, the temperature of the deposition tube is maintained so low as to have about 4000C. After the wafer has been completely brought into the deposition tube, the temperature of the deposition tube is gradually increased to the normal polysilicon deposition temperature so as to properly deposit the polysilicon layer 26.
Referring to Figure 1K, the polysilicon layer 26 is patterned by the photolithography to form polypattern 261.
Thereafter, arsenic ions (As) to become the emitter source are implanted at a dose of 1 x 1016 - 2 x 1016 ions/CM2.
Referring to Figure 1L, the impurities implanted in the steps of Figures IG and 1K are simultaneously diffused to form base region 27 and emitter region 28.
Referring to Figure IM, oxide layer 29 and BPSG layer 30 are sequentially deposited on the wafer, a photoresist is laid over the BPSG layer 30 and oxide layers 29, 21 are sequentially etched by the photolithography to form a metal contact window 31.
Finally, the photoresist is removed, and a metal layer is placed on the wafer, which is then patterned to form a metal electrode pattern 32. Thus, there is obtained a polyemitter bipolar transistor with a low resistance.
As described above, according to the present invention, the surface of the single crystal silicon substrate damaged due to the removing of the oxide layer in order to contact the single crystal Si substrate with the polysilicon layer is dry-etched by the plasma enhanced CVD method so as to prevent the increase of the emitter resistance when forming the polyemitter.
Also, when the ramp-up process is employed to deposit the polysilicon layer on the wafer, the temperature of the deposition tube is maintained low during bringing the wafer into the tube, and after the wafer has been completely brought into the tube, the temperature is increased up to the level of the normal polysilicon deposition temperature, so that oxide layer forming is inhibited so as to produce a polyemitter bipolar transistor with a low resistance.
Claims (8)
1. A process for fabricating a polyemitter bipolar transistor comprising the steps of: forming a buried layer and an N-type epitaxial layer on an Si substrate; forming an N-type well for the region of said bipolar transistor by performing ion implantation of an N- type impurity on the epitaxial layer; forming a field oxide layer by oxidation; forming an N+ diffusion layer in a collector region; forming an ion implanted layer for a base region by performing ion implantation of a P- type impurity; depositing an oxide layer; forming a contact window by etching said oxide layer; forming a polypattern by patterning after depositing a polysilicon layer by ramp-up deposition processing; performing ion implantation on the substrate to form an emitter region; forming the base region and the emitter region by diffusing the ion implanted impurities at the same time; forming an oxide layer and BPSG layer; forming a metal contact window by sequentially etching the BPSG layer and oxide layer by photolithography; and forming a metal electrode pattern by depositing a metal layer and patterning.
2. A process as claimed in Claim 1, wherein said contact window contacts said single crystal Si substrate with said polypattern.
3. A process as claimed in Claim 1 or 2, wherein the step for forming the contact window comprises the substeps of: depositing a photoresist on said oxide layer; exposing a portion of the substrate for forming said contact window by etching said photoresist by photolithography; etching said oxide layer by reactive ion etch; and etching the portion of said single crystal silicon substrate damaged during etching of said oxide layer.
4. A process as claimed in Claim 3, wherein the 1 is damaged portion is etched by a plasma enhanced CVD method.
A process as claimed in any one of the preceding claims, wherein when depositing said polysilicon, the temperature of a deposition tube is maintained at about 4000C during the period the wafer is brought into the tube, and after the wafer has been completely brought into the tube, the temperature is gradually increased up to the level of the normal polysilicon deposition temperature.
6. A process as claimed in any one of the preceding claims, wherein said polypattern is the diffusion source of the emitter region.
7. A process for fabricating a bipolar transistor, substantially as hereinbefore described with reference to, and as illustrated by, the accompanying drawings.
8. A bipolar transitor, fabricated by a method as claimed in any one of the preceding claims.
Published 1992at7be Patent Office. Concept House, CardiffRoad, NewporL Gwent NP9 IRH. Further copies maybe obtained fmm Sales Branch. Unit 6. Nine Mile Point. Cwmfelinfach. Cross Keys. Newport. NP1 7HZ. Printed by Multiplex techniques ltd, St Mary Cray, Kent.
Z
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900013935A KR920007124A (en) | 1990-09-04 | 1990-09-04 | Manufacturing Method of Poly-Emitter Bipolar Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9100672D0 GB9100672D0 (en) | 1991-02-27 |
| GB2247780A true GB2247780A (en) | 1992-03-11 |
Family
ID=19303215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9100672A Withdrawn GB2247780A (en) | 1990-09-04 | 1991-01-11 | Fabricating a bipolar transistor |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH0629302A (en) |
| KR (1) | KR920007124A (en) |
| DE (1) | DE4103594A1 (en) |
| FR (1) | FR2666450A1 (en) |
| GB (1) | GB2247780A (en) |
| IT (1) | IT1245092B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995002898A1 (en) * | 1993-07-12 | 1995-01-26 | National Semiconductor Corporation | Process for fabricating semiconductor devices having arsenic emitters |
| US6249031B1 (en) * | 1998-02-09 | 2001-06-19 | Chartered Semiconductor Manufacturing Ltd. | High gain lateral PNP and NPN bipolar transistor and process compatible with CMOS for making BiCMOS circuits |
| US7737049B2 (en) | 2007-07-31 | 2010-06-15 | Qimonda Ag | Method for forming a structure on a substrate and device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4240738A1 (en) * | 1992-12-03 | 1993-08-26 | Siemens Ag | Bipolar transistor prodn. for long service life - by forming base in surface of substrate, short term temp. adjusting, and forming emitter |
| KR19980054454A (en) * | 1996-12-27 | 1998-09-25 | 김영환 | Polysilicon Cone Formation Method |
| KR100382725B1 (en) * | 2000-11-24 | 2003-05-09 | 삼성전자주식회사 | Method of manufacturing semiconductor device in the clustered plasma apparatus |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0062725B1 (en) * | 1981-04-14 | 1984-09-12 | Deutsche ITT Industries GmbH | Method of making an integrated planar transistor |
| EP0099878B1 (en) * | 1981-12-31 | 1989-03-22 | International Business Machines Corporation | Method for reducing oxygen precipitation in silicon wafers |
| DE3304642A1 (en) * | 1983-02-10 | 1984-08-16 | Siemens AG, 1000 Berlin und 8000 München | INTEGRATED SEMICONDUCTOR CIRCUIT WITH BIPOLAR TRANSISTOR STRUCTURES AND METHOD FOR THEIR PRODUCTION |
| DE3580206D1 (en) * | 1984-07-31 | 1990-11-29 | Toshiba Kawasaki Kk | BIPOLAR TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF. |
| KR880000483B1 (en) * | 1985-08-05 | 1988-04-07 | 재단법인 한국전자통신 연구소 | Fabricating semiconductor device with polysilicon protection layer during processing |
| US4693782A (en) * | 1985-09-06 | 1987-09-15 | Matsushita Electric Industrial Co., Ltd. | Fabrication method of semiconductor device |
| DE3787110D1 (en) * | 1986-03-21 | 1993-09-30 | Siemens Ag | Method of manufacturing a bipolar transistor structure for high speed switching. |
| JPS6353928A (en) * | 1986-08-22 | 1988-03-08 | Anelva Corp | Dry etching |
| US4839302A (en) * | 1986-10-13 | 1989-06-13 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating bipolar semiconductor device |
| JPS63182860A (en) * | 1987-01-26 | 1988-07-28 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JP2654011B2 (en) * | 1987-03-31 | 1997-09-17 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPH01157565A (en) * | 1987-12-14 | 1989-06-20 | Nec Corp | Manufacture of bi-mos integrated circuit device |
| JPH0736389B2 (en) * | 1988-11-10 | 1995-04-19 | 三菱電機株式会社 | Method for forming electrode wiring of semiconductor device |
-
1990
- 1990-09-04 KR KR1019900013935A patent/KR920007124A/en not_active Application Discontinuation
-
1991
- 1991-01-04 FR FR9100086A patent/FR2666450A1/en active Granted
- 1991-01-11 IT ITMI910068A patent/IT1245092B/en active IP Right Grant
- 1991-01-11 GB GB9100672A patent/GB2247780A/en not_active Withdrawn
- 1991-02-04 DE DE4103594A patent/DE4103594A1/en not_active Ceased
- 1991-09-04 JP JP3253022A patent/JPH0629302A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995002898A1 (en) * | 1993-07-12 | 1995-01-26 | National Semiconductor Corporation | Process for fabricating semiconductor devices having arsenic emitters |
| US6249031B1 (en) * | 1998-02-09 | 2001-06-19 | Chartered Semiconductor Manufacturing Ltd. | High gain lateral PNP and NPN bipolar transistor and process compatible with CMOS for making BiCMOS circuits |
| US7737049B2 (en) | 2007-07-31 | 2010-06-15 | Qimonda Ag | Method for forming a structure on a substrate and device |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2666450B1 (en) | 1993-02-26 |
| GB9100672D0 (en) | 1991-02-27 |
| KR920007124A (en) | 1992-04-28 |
| ITMI910068A0 (en) | 1991-01-11 |
| ITMI910068A1 (en) | 1992-07-11 |
| FR2666450A1 (en) | 1992-03-06 |
| JPH0629302A (en) | 1994-02-04 |
| DE4103594A1 (en) | 1992-03-05 |
| IT1245092B (en) | 1994-09-13 |
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