GB2244596A - Semiconductor memory device with stacked capacitor - Google Patents

Semiconductor memory device with stacked capacitor Download PDF

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Publication number
GB2244596A
GB2244596A GB9016673A GB9016673A GB2244596A GB 2244596 A GB2244596 A GB 2244596A GB 9016673 A GB9016673 A GB 9016673A GB 9016673 A GB9016673 A GB 9016673A GB 2244596 A GB2244596 A GB 2244596A
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layer
over
bit line
capacitor
polysilicon
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GB9016673A
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GB9016673D0 (en
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Tae-Hyuk Ahn
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A DRAM cell comprises a semiconductor substrate (10), an element isolating oxide layer (11), a plurality of word line electrodes (14, 15, 16), a source region (12), drain region (13), an insulating layer (17) laid over the word line electrodes, a bridge electrode layer (18) laid over the element isolating oxide layer (11) and contacting the source region (12), a bit line layer (21) extended parallel to the substrate above the bridge electrode (18) and contacting the drain region (13), a first polysilicon layer (24) extending above the bit line layer (21) and connected with the bridge electrode layer (18), a dielectric layer (25) covering the whole surface of the substrate including the upper surface of the first polysilicon layer (24), a second polysilicon layer (26) extending above the bit line layer (21) and covering the dielectric layer (25), and insulating interlayers (20, 22) for isolating the bit line layer (21) from the bridge electrode layer (18), first polysilicon layer (24) and dielectric layer (25). The structure of the stacked capacitor 24-26 enables a large capacitance to be achieved. <IMAGE>

Description

SEMICONDUCTOR MEMORY DEVICE WITH STACKED CAPACITOR The present invention relates to a semiconductor memory device, and particularly to a DRAM (Dynamic Random Access Memory) cell having a stacked-capacitor, and to a manufacturing process therefor.
Nowadays, with increasing necessity for high levels of integration and large memory storage capacities in semiconductor memory devices, it is essential to use advanced technology to minimize the area occupied by individual memory cells in memory devices whilst maximizing the memory storage capacity thereof.
Conventionally, for a DRAM cell composed of a transistor and a capacitor, there have been proposed a variety of capacitor structures which are aimed at being applied to achieve a memory storage capacity of 4 or 16 Mega bytes or higher. For example, one of these structures uses a V- or U-shaped trench formed in a substrate, where the walls of the trench serve as a capacitive charge storage area.
Another structure has a stacked capacitor extending over a substrate.
Because the stacked capacitor is formed by stacking polysilicon in three dimensions, it may achieve as large a capacity as the trench capacitor. However, the limitations of etching processes used in the fabrication of such structures makes it difficult to increase the capacity.
Referring to Figs. 1 and 2 of the accompanying drawings illustrating the layout of a conventional stacked capacitor DRAM cell array, a storage electrode 6 and a plate electrode 8 of a capacitor are formed in a space near an intersection of word lines 2, 3 with a bit line 9. The storage electrode 6 is connected to a source region, of a transistor through an aperture 4, a bit line 9 is connected to a drain region of the transistor, through an aperture 5.
In Figure 2, there is illustrated a cross sectional view of the conventional stacked capacitor DRAM cell, taken along the line a-b of Figure 1. The conventional stacked DRAM capacitor cell, as described in the drawing, includes the storage electrode 6 laid over and between the two word line electrodes 2 and 3 in contact with the source of the transistor, the plate electrode 8 and a dielectric layer 7 covering the storage electrode 6 and extending over an element isolating oxide layer (11 in figure 1), a bit line layer 9 extending over the plate electrode 8 and contacting with the drain of the transistor, insulating interlayers 10, 11 for isolating the plate electrode 8, the bit line layer 9, and a metal electrode 12 from each other, and an element protecting layer 13 laid over the metal electrode 12.
In such a conventional stacked capacitor DRAM cell as shown in Figs. 1 and 2, because the bit line 9 is usually formed after forming the plate electrode 8 of the capacitor, it is only possible to change the pattern size of the plate electrode 8 in parts other than where the bit line 9 must contact with the drain of the transistor. Hence, the capacity of the capacitor may not be increased owing to the limitation of the etching pattern.
It is accordingly an object of preferred embodiments of the present invention to provide a semiconductor memory device having a capacitor adapted for a large capacity memory.
It is another object of preferred embodiments of the present invention to provide a DRAM cell having a larger area stacked capacitor, without a corresponding increase in cell size.
It is a further object of preferred embodiments of the present invention to provide a method of manufacturing a semiconductor memory device, wherein a capacitor of a large charge capacity is obtained without being unduly affected by an etching pattern limitation.
It is still another object of preferred embodiments of the present invention to provide a method of manufacturing a stacked capacitor for a DRAM cell, wherein the capacitor is formed over bit lines.
According to a first aspect of the present invention there is provided a semiconductor memory cell array having at least one bit line, a plurality of word lines intersecting said bit line, at least one capacitor, at least one MOS transistor having a gate, and a drain and a source connected between said capacitor and said bit line, wherein said semiconductor memory cell array further includes: a bridge electrode for connecting said capacitor to the source or drain of said MOS transistor; a contacting aperture formed on or in a region of said bridge electrode and in an area which is not covered by a said bit line; a storage electrode connected to said bridge electrode through said contacting aperture, and having a portion which extends over said bit line; and a plate electrode formed over said storage electrode and extending over a substantial area of said substrate.
Preferably, said bridge electrode is extended over a nonactive region of said MOS transistor.
Preferably, said contacting aperture is formed on said bridge electrode over an active and/or nonactive region of said MOS transistor.
According to a second aspect of the present invention, there is provided a dynamic random access memory (DRAM) cell having a semiconductor substrate, a plurality of word line electrodes, a transistor having a source region and a drain region, an element isolating oxide layer, an insulating layer laid over said word line electrodes, said DRAM cell further comprising:: a bridge electrode layer connected to said source or drain region, and extending over said element isolating oxide layer; a bit line layer connected to said source or drain region, said bit line layer extending above said bridge electrode a first polysilicon layer connected to said bridge electrode layer, said first polysilicon layer extending over said bit line layer; a dielectric layer covering an upper surface of said first polysilicon layer, and extending over a substantial area of said substrate; a second polysilicon layer extending over said bit line layer, and over said dielectric layer; and one or more insulating interlayers for isolating said bit line layer from said bridge electrode layer, said first polysilicon layer and said dielectric layer.
Preferably, said first polysilicon layer is a storage electrode of a capacitor.
Preferably, said second polysilicon layer is a plate electrode of said capacitor.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: applying an insulating layer to a semiconductor substrate having an element isolating oxide layer, word line electrodes, and a sosurce and a drain; etching a portion of said insulating layer over said source or drain so as to expose a surface thereof to form a first contacting aperture; forming a bridge electrode layer over said element isolating layer and the surface of said source or drain exposed through said first contacting aperture; forming a polysilicon oxide layer over the surface of said bridge electrode layer by a thermal oxidation process; applying a first insulating interlayer to cover a substantial area of said substrate; ; performing an etching through portions of said first insulating interlayer and insulating layer positioned over said source or drain so as to expose a surface of said drain or source to form a second contacting aperture; applying a bit line layer over said substrate to form a given bit line pattern, and applying a second insulating interlayer over said substrate; performing an etching through portions of said second insulating interlayer, said first insulating interlayer and said polysilicon oxide layer positioned over said bridge electrode layer, so as to expose a surface of said bridge electrode layer to form a third contacting aperture; applying a first polysilicon layer over said substrate, to form an electrode pattern; applying a dielectric layer over said substrate; and forming a second polysilicon layer over said dielectric layer.
Preferably, said first and second polysilicon layers extend over said bit line layer.
Preferably, said dielectric layer is any one or more of the following: an oxide layer, a mixture of an oxide layer and nitride layer, tantalum oxide.
Preferably, said first polysilicon layer forms a storage electrode of a capacitor.
Preferably, said second insulating interlayer isolates said bit line layer from said storage electrode.
Preferably, said second polysilicon layer forms a plate electrode of a capacitor.
Preferably, said third contacting aperture is formed anywhere over said bridge electrode layer.
In a semiconductor memory cell, DRAM cell, method of manufacture of a semiconductor device, or a method of preparing a capacitor according to any of the above aspects of the invention, a bridge electrode layer and/or a bit line or bit line layer may be of polysilicon, or of a mixture of polysilicon and a high melting point material.
Preferably, said first and second polysilicon layers extend over said bit line layer.
Preferably, said first polysilicon layer forms a storage electrode of said capacitor.
Preferably, said second polysilicon layer forms a plate electrode of said capacitor.
According to a fourth aspect of the present invention, there is provided a method of preparing a capacitor of a Dynamic Random access memory (DRAM) cell on a semiconductor substrate having a MOS transistor having a gate, source and drain, said method comprising the steps of: exposing a surface of a source or drain of said MOS transistor so as to form a bridge electrode layer in contact with said source or drain; exposing a surface of a drain or source of said MOS transistor for contacting a bit line layer with said drain or source; exposing a surface of said bridge electrode layer for contacting a first polysilicon layer with said bridge electrode layer; forming a dielectric layer over said first polysilicon layer; and forming a second polysilicon layer over said dielectric layer.
In a semiconductor memory cell, DRAM cell, method of manufacture of a semiconductor device, or a method of preparing a capacitor, according to any of the above aspects of the invention, said high melting point material may be a metal and/or any one or more of, or any combination of the following materials; W, Ti, Mo.
According to a fifth aspect of the present invention, there is provided a semiconductor memory cell array having a substrate, a semiconductor device provided on said substrate, word and/or bit lines overlying said device and substrate, and a capacitor connected to said device and having at least one plate which overlies at least one of said word and/or bit lines such that said one line is disposed between said one plate and said substrate.
Such an array may incorporate one or more of the features of any of the preceding aspects of the invention.
Preferred embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which; Figure 1 is a partial plan view of a conventional DRAM cell; Figure 2 is a cross-sectional view taken along the line a - b of Figure 1; Figure 3 is a partial plan view of a DRAM cell according to a preferred embodiment of the present invention; Figure 4 is a cross-sectional view taken along the line x-y-z of Figure 3; and Figs. 5A - 5E illustrates processing steps for manufacturing a stacked capacitor cell according to a preferred method of the present invention.
Referring to Figures 3 and 4 of the accompanying drawings, on a semiconductor substrate 10 are formed an element isolating oxide layer 11, a transistor having source and drain regions 12 and 13 respectively, word line electrodes 14, 15, 16, and an insulating layer 17 covering the above elements.
Contacted with the source region 12 is a bridge electrode layer 18 covering the element isolating oxide layer 11. Contacted with the drain region is bit line layer 21 extending parallel to the substrate and over the bridge electrode layer 18.
Connected with the bridge electrode layer 18 is a first polysilicon layer 24 which extends over the bit line layer 21.
Dielectric layer 25 covers the substrate and all of the above mentioned elements, layers and regions including the upper surface of the first polysilicon layer 24. The dielectric layer 25 is covered by a second polysilicon layer 26 extending over the bit line layer 21. The second polysilicon layer is isolated from the bridge electrode layer 18, the first polysilicon layer 24 and the dielectric layer 25 by first and second insulating interlayers 20 and 22.
laid over the second polysilicon layer 26 are a third insulating interlayer 27, metal electrodes 28 and element protecting layer 29.
The first and second polysilicon layers 24 and 26 form respectively the storage and plate electrodes of capacitor.
Referring to Figure 3, of the accompanying drawings, shown in a plan view of the DRAM cell array is a first contacting aperture 52 which is formed for contacting between the bridge electrode layer 18 and the source layer 12 in active region 30 of the transistor positioned below the bit line 21. The active region 30 perpendicularly intersects the word line layers 14, 15, 16, and a second contacting aperture 54 which is formed for contacting between the bit line layer 21 and the drain region 13, of the transistor.
The bridge electrode layer 18 connects with the source region 12 through the first contacting aperture 52 and is connected with the third contacting aperture 56 below the storage electrode 24 formed over the bit line layer 21.
In effect, the bridge electrode layer 18 connects the source region 12 of the transistor to the storage electrode 24 formed over the bit line layer 21, thus avoiding a pattern limitation due to the second contacting aperture 54 for contacting with the bit line layer 21.
Also, it will easily be appreciated by one skilled in this technical field that the bridge electrode layer 18 may be easily arranged symmetrically and repeatedly around a given axis in an array of multiple cells, and the position of the third contacting aperture 56 may be changed according to the extension of the storage electrode 24. Moreover, because the plate electrode 26 of the capacitor occupies the whole upper surface of the cell array, a considerable increase of the storage capacity may be obtained compared to a conventional structure.
Hereinafter, a preferred process for manufacturing a stacked capacitor of a DRAM cell according to a preferred embodiment of the present invention will now be described with reference to Figs. SA-SE of the accompanying drawings.
Referring to Figure SA, a first photomask pattern 51 is formed on a semiconductor substrate 10 of a semiconductor wafer having an element isolating oxide layer 11, word line electrodes 14, 15, 16, source and drain regions 12 and 13 of a MOS transistor, and an insulating layer 17 covering the substrate. Then, the first contacting aperture 52 is formed to expose the source region 12, and thereafter the first photomask pattern 51 is removed. The first contacting aperture 52 in the DRAM cell is to allow the transistor to connect with a capacitor.
Referring to Figure SB, over the whole surface of the substrate is deposited polysilicon or a mixture of polysilicon and a metal having a high melting point (W, Ti, Mo, etc.) with a thickness of 500-2,000A. Then, the polysilicon or mixture thereof which covers all regions except for the source region 12 and the element isolating oxide layer 11, are etched to form bridge electrode layer 18 contacting with the source region 12. The surface of the bridge electrode layer 18 is then thermally oxidized to form a polysilicon oxide layer 19 thereonto.
Then, as shown in Figure 5C, to the whole surface of the substrate 10 is applied a first insulating interlayer 20 and a second photomask pattern 53, in which portions of the first insulating interlayer 20 and the insulating layer 17 over the drain region 13 are anisotropically and sequentially etched to form a second contacting aperture 54, and thereafter the second photomask pattern 53 is removed.
The second contacting aperture 54 is to allow a bit line to connect with the transistor in the DRAM cell.
Subsequently, as shown in Figure 5D, over the whole area of the substrate is applied a mixture of polysilicon and a metal having a high melting point such as, for example, W, Ti, Mo, etc., to form a bit line layer 21, although it is to be appreciated that bit lines according to the invention are not restricted to such a mixture or to one of such metals. The mixture is patterned to form the bit line layer 21 contacting with the drain region 13 through the second contacting aperture 54.
Then, to the whole area of the substrate is applied a second insulating interlayer 22, to which in turn is applied a third photomask pattern 55 to form a third contacting aperture 56 by etching the second insulating interlayer 22, first insulating interlayer 20 therebelow and polysilicon oxide layer 19, so as to expose a portion of the bridge electrode layer 18 formed over the element isolating oxide layer 11. Thereafter, the third photomask pattern 55 is removed.
In a step as shown in Figure 5E, to the whole area of the substrate is applied polysilicon by using conventional methods of ion implantation and POCL, deposition. The first polysilicon layer 24 is patterned to form a storage electrode.
Then, to the whole area of the substrate including the upper surface of the first polysilicon layer 24, is applied a dielectric layer 25, to which in turn is applied a second polysilicon layer 26 to form a plate electrode by patterning. The dielectric layer 25 may be for example, a high dielectric substance such as an oxide layer, or a composite of an oxide layer and nitride layer or tantalum oxide (tea205). Although it is in no way intended that the invention is restricted to the use of these examples.
Subsequent processing steps may be performed conventionally, to accomplish the structure as shown in Figures 3 and 4 of the accompanying drawings.
According to the above preferred process for manufacturing DRAM cells, the position of the third contacting aperture 56 for connecting the bridge electrode layer 18 to the first polysilicon layer 24 for the charge storage electrode of the capacitor, may be changed in position according to the extension of the storage electrode, so that problems due to the limitation of the etching pattern do not occur as in the prior art.
As stated above, in the preferred embodiment of a DRAM cell, the capacitor is formed over the bit line and the connection between the capacitor and the active region of the transistor is accomplished by employing a bridge electrode, thus resolving a limitation of the pattern due to the existence of the bit line contacting region. Additionally, since in the preferred embodiment of a DRAM cell, a capacitor is formed over a bit line, the capacitor may occupy a larger area without any increase in cell size.
The preferred embodiments of the present invention may improve the reliability of a semiconductor device having a high degree of integration and a large storage capacity.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s).
The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (23)

1. A semiconductor memory cell array having at least one bit line, a plurality of word lines intersecting said bit line, at least one capacitor, at least one MOS transistor having a gate, and a drain and a source connected between said capacitor and said bit line, wherein said semiconductor memory cell array further includes: a bridge electrode for connecting said capacitor to the source or drain of said MOS transistor; a contacting aperture formed on or in a region of said bridge electrode and in an area which is not covered by a said bit line; a storage electrode connected to said bridge electrode through said contacting aperture, and having a portion which extends over said bit line; and a plate electrode formed over said storage electrode and extending over a substantial area of said substrate.
2. A semiconductor memory cell array as claimed in Claim 1, wherein said bridge electrode is extended over a nonactive region of said MOS transistor.
3. A semiconductor memory cell array as claimed in Claim 1 or 2, wherein said contacting aperture is formed on said bridge electrode over an active and/or nonactive region of said MOS transistor.
4. A Dynamic random access memory (DRAM) cell having a semiconductor substrate, a plurality of word line electrodes, a transistor having a source region and a drain region, an element isolating oxide layer, an insulating layer laid over said word line electrodes, said DRAM cell further comprising: a bridge electrode layer connected to said source or drain region, and extending over said element isolating oxide layer a bit line layer connected to said source or drain region, said bit line layer extending above said bridge electrode; a first polysilicon layer connected to said bridge electrode layer, said first polysilicon layer extending over said bit line layer; a dielectric layer covering an upper surface of said first polysilicon layer, and extending over a substantial area of said substrate;; a second polysilicon layer extending over said bit line layer, and over said dielectric layer; and one or more insulating interlayers for isolating said bit line layer from said bridge electrode layer, said first polysilicon layer and said dielectric layer.
5. A DRAM cell according to claim 4, wherein said first polysilicon layer is a storage electrode of a capacitor.
6. A DRAM cell according to claim 4 or 5, wherein said second polysilicon layer is a plate electrode of said capacitor.
7. A method of manufacturing a semiconductor device comprising the steps of: applying an insulating layer to a semiconductor substrate having an element isolating oxide layer, word line electrodes, and a source and a drain; etching a portion of said insulating layer over said source or drain so as to expose a surface thereof to form a first contacting aperture; forming a bridge electrode layer over said element isolating layer and the surface of said source or drain exposed through said first contacting aperture; forming a polysilicon oxide layer over the surface of said bridge electrode layer by a thermal oxidation process; applying a first insulating interlayer to cover a substantial area of said substrate;; performing an etching through portions of said first insulating interlayer and insulating layer positioned over said source or drain so as to expose a surface of said drain or source to form a second contacting aperture; applying a bit line layer over said substrate to form a given bit line pattern, and applying a second insulating interlayer over said substrate; performing an etching through portions of said second insulating interlayer, said first insulating interlayer and said polysilicon oxide layer positioned over said bridge electrode layer, so as to expose a surface of said bridge electrode layer to form a third contacting aperture; applying a first polysilicon layer over said substrate, to form an electrode pattern; applying a dielectric layer over said substrate; and forming a second polysilicon layer over said dielectric layer.
8. A method of manufacturing a semiconductor device according to claim 7, wherein said first and second polysilicon layers extend over said bit line layer.
9. A method of manufacturing a semiconductor device according to claim 7 or 8 wherein said dielectric layer is any one or more of the following: an oxide layer, a mixture of an oxide layer and nitride layer, tantalum oxide.
10. A method of manufacturing a semiconductor device according to any one of claims 7, 8 or 9 wherein said first polysilicon layer forms a storage electrode of a capacitor.
11. A method of manufacturing a semiconductor device according to claim 10, wherein said second insulating interlayer isolates said bit line layer from said storage electrode.
12. A method of manufacturing a semiconductor device according to any one claims 7 to 11, wherein said second polysilicon layer forms a plate electrode of a capacitor.
13. A method of manufacturing a semiconductor device according to any one of claims 7 to 12, wherein said third contacting aperture is formed anywhere over said bridge electrode layer.
14. A semiconductor memory cell, DRAM cell, method of manufacture of a semiconductor device, or a method of preparing a capacitor according to any one of the preceding claims 1 to 13, wherein a bridge electrode layer and/or a bit line or bit line layer is of polysilicon, or of a mixture of polysilicon and a high melting point material.
15. A method of preparing a capacitor of a DRAM cell as claimed in Claim 14, wherein said first and second polysilicon layers extend over said bit line layer.
16. A method of preparing a capacitor of a DRAM cell according to claim 14 or 15 wherein said first polysilicon layer forms a storage electrode of said capacitor.
17. A method of preparing a capacitor of a DRAM cell according to claim 14, 15 or 16, wherein said second polysilicon layer forms a plate electrode of said capacitor.
18. A method of preparing a capacitor of a Dynamic Random access memory (DRAM) cell on a semiconductor substrate having a MOS transistor having a gate, source and drain, said method comprising the steps of: exposing a surface of a source or drain of said MOS transistor so as to form a bridge electrode layer in contact with said source or drain; exposing a surface of a drain or source of said MOS transistor for contacting a bit line layer with said drain or source; exposing a surface of said bridge electrode layer for contacting a first polysilicon layer with said bridge electrode layer; forming a dielectric layer over said first polysilicon layer; and forming a second polysilicon layer over said dielectric layer.
19. A semiconductor memory cell, DRAM cell, method of manufacture of a semiconductor device, or a method of preparing a capacitor, according to any of the preceding claims, wherein said high melting point material is a metal and/or is any one or more of, or any combination of the following materials; W, Ti, Mo.
20. A semiconductor memory device constructed or arranged substantially as herein described with reference to Figures 3 to 5 of the accompany drawings.
21. A method of manufacturing or preparing a semiconductor memory substantially as herein described, with reference to Figures 3 to 5 of the accompanying drawings.
22. A semiconductor memory cell array having a substrate, a semiconductor device provided on said substrate, word and/or bit lines overlying said device and substrate, and a capacitor connected to said device and having at least one plate which overlies at least one of said word and/or bit lines such that said one line is disposed between said one plate and said substrate.
23. An array according to claim 22 and incorporating one or more of the features of any of claims 1 to 21.
GB9016673A 1990-05-31 1990-07-30 Semiconductor memory device with stacked capacitor Withdrawn GB2244596A (en)

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KR1019900008069A KR920009748B1 (en) 1990-05-31 1990-05-31 Stacked capacitor cell and method for producing the same

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GB2244596A true GB2244596A (en) 1991-12-04

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TWI679662B (en) * 2019-08-01 2019-12-11 力晶積成電子製造股份有限公司 Capacitor integrated structure and its capacitor and manufacturing method thereof

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Also Published As

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CN1056946A (en) 1991-12-11
KR910020903A (en) 1991-12-20
IT9048191A1 (en) 1991-12-01
JPH0435062A (en) 1992-02-05
DE4023153A1 (en) 1991-12-05
GB9016673D0 (en) 1990-09-12
KR920009748B1 (en) 1992-10-22
IT9048191A0 (en) 1990-07-31

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