GB2243716A - Self-aligned, planar heterojunction bipolar transistor and method of forming the same - Google Patents
Self-aligned, planar heterojunction bipolar transistor and method of forming the same Download PDFInfo
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- GB2243716A GB2243716A GB8924432A GB8924432A GB2243716A GB 2243716 A GB2243716 A GB 2243716A GB 8924432 A GB8924432 A GB 8924432A GB 8924432 A GB8924432 A GB 8924432A GB 2243716 A GB2243716 A GB 2243716A
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- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 10
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- 229910052751 metal Inorganic materials 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000010953 base metal Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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Abstract
The transistor is formed with self-aligned base-emitter 6, 4 and base-collector 6, 8 junctions by forming a two-level mask (Fig 4) over a doped base layer, sequentially forming openings in registration (Figs 4, 5) through the two mask layers, and using the opening in one mask layer to define the collector region 8 and the opening in the other mask layer to define the emitter base 6. A buried conductive layer (16 Fig 3) formed by a dopant implant establishes an electrical contact to the collector region and connects to the surface via another conductive implant (20 Fig 3) that extends through a lateral extension of the collector region. The collector region itself is formed by a high energy silicon dopant implant, while the active base region which forms junctions with the emitter and collector is etched thinner than the remainder of the base layer. The latter feature reduces the resistivity associated with connections to lateral base contacts. Parasitic capacitances are minimized when the collector and buried conductive layers are implanted into a semi-insulating substrate such that only the active junction regions overlap, enabling high speed operation. The collector (24) and emitter (32) contact regions are opposite each after (Fig 1), the base contact regions (26) being lateral to them both. <IMAGE>
Description
SELF-ALIGNED, PLANAR HETEROJUNCTION BIPOLAR TRANSISTOR
AND METHOD OF FORMING THE SAME BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to the structure and fabrication of heterojunction bipolar transistors, and more particularly to the use of selective area ion implantation in the formation of such transistors.
Descri tion of the Related Art
Heterojunction bipolar transistors (HBTs) are attracting interest currently because of their potential for high speed and high frequency applications. Perhaps the two most popular current fabrication techniques for high speed HBTs are described in the following articles: the first by Chang et al., "AlGaAs/GaAs Heterojunction Bipolar
Transistors Fabricated Using a Self-Aligned Dual-Lift-Off
Process", IEEE Electron Device Letters, Vol. EDL-8, No. 7,
July 1987, pages 303-5; and the second by Nakajima et al., "High Speed AlGaAs/GaAs HBTs with Proton Implanted Buried
Layers", IEDM Tech. Diq., December 1986 (Los Angeles), pages 266-269. In these techniques the HBTs are fabricated by mesa etching of epitaxially grown device structures.Deep mesas are required for collector contacts and possibly for device isolation, making it difficult to fabricate high density integrated circuits. More importantly, the devices also exhibit considerable parasitic capacitances, thus retarding their speed below their ultimate potential. Also, they are not readily compatible for integration with other GaAs devices such as metalsemiconductor-field-effect-transistors (MESFETs). While the emitter is self-aligned with the base, the collector is not truly self-aligned with either the emitter or base, -and-the base-collector overlap area is approximately three times the emitter-base junction area in the state-of-theart HBTs. This increases the base-collector capacitance, thereby severely limiting the maximum operating frequency of the device.It is also difficult during fabrication to control the uniformity of the depth of the etch step to the base, which results in a poor yield. Another problem is that, since the emitter is only a little over a micron wide, the emitter contact tends to lap over and. may short to the base contact. Finally, the device is non-planar because the collector contact is considerably below the level of the emitter contact.
The device discussed above is grown entirely by molecular beam epitaxy (MBE) or chemical vapor deposition (CVD), acting upon the surface. Another type of HBT is fabricated with a process that utilizes a two-step epitaxial deposition with an intervening selective ion implant of bases. It is described in Tully et al., "A Fully
Planar Heterojunction Bipolar Transistor", IEEE Electron
Device Letters, Vol. EDL-7, No. 11, November 1986, pages 615-17. While the surface of this device is substantially planar, the base and collector are not self-aligned. It is also relatively slow because of a high base-collector capacitance, and has a high resistance collector contact.
A fully planar HBT in an "emitter-down" configuration is disclosed in S. Evans et al., "GaAs HBT LSI/VLSI Fabrication Technology", 1987 GaAs IC Svm#osium Tech. Digest, 1987, pages 109-112. In this inverted device the base is doped by ion implantation through a top collector layer, with the emitter formed on the underside of the HBT. It is intended for high density digital logic applications where switching speeds are considerably slower than the state-of-the-art. It is not self-aligned, and is characterized by a high capacitance that makes it slow in speed.
SUMMARY OF THE INVENTION
In view of the above problems, the present invention seeks to provide a high speed, self-aligned HBT which is also substantially planar, can be used in high density integrated circuits, and is fully compatible with GaAs
MESFET fabrication. The invention also seeks to provide an improved fabrication technique for such a device.
In accordance with the invention, a transistor base layer of one type doping is formed on a semi-insulating substrate, and an emitter of opposite type doping is established over the base layer. The emitter forms a junction with the base layer over a defined area. A collector region of opposite type doping to the base layer is fabricated below the base layer so as to form a junction therewith over a defined area which is substantially aligned with the base-emitter junction. A buried conductive layer within the substrate establishes an electrical connection with the collector region. Base and emitter contacts are then provided, and a collector contact is made to the collector region via the buried layer, lateral to the collector region.
In the preferred embodiment the collector region is lightly doped, while the buried layer is of the same type doping but heavily doped, and contacts the underside of the collector region. An extension of the collector region extends laterally over the buried layer, such that the collector contact establishes an electrical. contact with the buried layer through the collector region extension. That extension includes a generally conductive ion implant region (either an actual implant or a diffused region) which extends from the collector contact down to the buried layer.
A substantially planar surface is established by providing the collector contact as a generally conductive layer of semiconductor material of substantially equal thickness to the emitter, surmounted by a metallic contact. This allows the thickness of the collector region to be substantially greater than either the base layer or the emitter, without degrading the planarity.
The base layer preferably has an active region which forms the base-emitter and base-collector junctions, together with an extension which extends laterally from the active region to the base contact. The base extension is substantially thicker and has a substantially lower resistivity in the lateral direction than the active base region.
In the preferred method of forming the HBT, the doped base layer is formed in a selective area on the semiinsulating semiconductor substrate. The aligned baseemitter and base-collector junctions are defined by an opening in a mask placed over the doped base layer.
Dopant particles of opposite type doping to the base doping are implanted into the substrate immediately below the base layer through the junction defining opening to establish the collector region. An emitter is then formed over the base through the same mask opening. The mask comprises a bottom electrically insulative layer surmounted by an implant absorbing layer. The junction defining opening is formed in the implant absorbing layer for implantation of the collector region, while the junction defining opening is formed in the insulative layer in registration with the opening in the implant absorbing layer for formation of the emitter. The implant absorbing layer may be removed prior to formation of the emitter, which may be either epitaxially grown or deposited by chemical vapor deposition over the base layer.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which:
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view showing the layout of a HBT in accordance with the invention;
FIGs. 2 and 3 are sectional views of the HBT of FIG.
1, taken along section lines 2-2 and 3-3, respectively; and
FIGs. 4-8 are sectional views showing successive steps in the fabrication of the HBT shown in FIGs. 1-3.
DETAILED DESCRIPTION OF THE INVENTION
The basic configuration of a preferred embodiment of the invention is shown in FIGs. 1-3. An HBT is formed on a semi-insulating substrate 2, preferably GaAs. The device consists of a vertical arrangement of an emitter 4 over an active base region 6, below which a collector region 8 is formed in the substrate. The active base region 6 is part of a larger base layer 10 which extends further over the substrate, but the active region has a lesser thickness than the remainder of the base layer.
The active base region 6 is bounded and defined along its longer sides by the inner opposed walls of a pair of insulative blocks 12. A base-emitter junction 13 is formed between insulating blocks 12, and is vertically aligned with the base-collector junction 14. The baseemitter and base-collector junctions are thus substantially aligned with each other, resulting in a significant increase in the operating speed of the HBT compared to prior devices that were not fully aligned. The only significant area of non-alignment occurs at the left end of the junction area (best shown near the center in FIG.
3), where the active base region 6 overlaps on the collector region 8 slightly beyond the limit of emitter 4. This overlap is deliberately provided during processing to assure that the emitter does not extend beyond the base and contact the collector due to processing tolerances.
However, the amount of overlap is relatively small (about 1-2 microns) compared to the total length of the active base region (typically about 30 microns). Together with the fact that the active base region is much longer than it is wide (typically about 30 microns long vs. 1-2 microns wide), the actual amount of misalignment between the base-emitter and base-collector junctions is #quite small, and does not substantially detract from the operating advantages of a device with absolute alignment.
The collector region 8 is relatively lightly doped.
Electrical contact with it is made via a buried layer 16 of higher doping concentration and conductivity. Buried- layer 16 contacts the underside of collector region 8 and extends laterally from the transistor junction, under a lateral extension 18 of the collector region. A highly doped implant 20 projects downward through the collector extension to contact the buried layer 16. Implant 20 is doped sufficiently to be substantially conductive, and thereby provides an electrical connection between the surface and the underside of collector 8 via buried layer 16.
To enhance the planarity of the device, an n-doped layer 22 identical to emitter 4 is grown over the conductive implant 20. This tends to reduce the variation in height of the various device elements over the surface of the substrate, especially when compared to the total depth of the device. A metallic collector contact pad 24 is formed over n-type layer 22. The metallic base contact pad 26 is provided over the portions of the base layer 10 lateral to active region 6. Collector contact pad 24 establishes an electrical contact with the collector region via the generally conductive n-doped region 22, the implant 20, and the buried layer 16. The base contact pad 26 makes electrical contact with the active base region 6 via the lateral portions of base layer 10, which it will be remembered are thicker and have a lower resistivity than the active base region.
To establish an emitter contact, an extension 30 of the emitter projects along the substrate surface on the opposite side of the device from the collector contact.
Both the emitter 4 and its extension 30 are surmounted by a conductive metal layer 32 which serves as a low resistance ohmic contact to the semiconductor. Thus the same semiconductor 4,30 and metal contact 32 that forms the emitter structure also forms the collector contact structure 22,24 over the vertical highly conductive channel 20 to the buried collector 16. The base contact is selfaligned to the emitter stripe 4 and emitter contact 32 along the length of the active region 6, as explained below.
Typical specifications for the device, which are by way of example only and are not to be taken as limiting, are as follows. The active base region 6 may be about 0.08 microns thick, the lateral portions of base layer 10 about 0.2 microns thick, the emitter 4 about 0.5 microns, the collector region 8 and the buried layer 16 about 0.7 microns each, and the planar assist layer 22 of equal thickness to the emitter at about 0.5 microns. Typical doping ranges are: 1-10x1019/cm3 for the active base region 6, 3-5x1017/cm3 for the emitter 4 and layer 22, 1 5x1016/cm3 for the collector region 8, and 1018/cm3 for the buried layer 16 and implant 20.
The preferred process for fabricating the HBT of
FIGs. 1-3 is illustrated in FIGs. 4-8. FIG. 4 shows an initial stage of the fabrication. The p+ GaAs base layer 10 is first epitaxially grown over the GaAs substrate 2, using either molecular beam epitaxy or metal organic chemical vapor deposition. At this point the active base region has not yet been formed. The desired dimensions of the base layer are achieved by a selective mask and etch ing process. Next, an insulating layer 36 such as SiO2 is deposited over the entire surface. This is followed by a layer of photoresist 38 over the insulating layer.An opening 40 is formed in the photoresist by standard photolithographic techniques immediately over the area intended for the-emitter-base and base-collector junqtions. A high energy silicon implant is next made through opening 40 to form the collector region 8 and buried layer 16. In one example this implant was performed at 1 MeV. The photoresist 38 surrounding opening 40 prevents penetration by the implant ions, thereby confining the implant to the desired regions within the substrate. Collector contact implant 20 (FIGs. 1, 3) is made through a separate opening in the photoresist.
Insulating layer 36 and photoresist layer 38 may collectively be considered to form a mask for processing the device. Once the collector region 8 and buried layer 16 have been implanted, opening 40 in the photoresist layer is extended through the oxide layer 36 by a plasma etch. The photoresist is then stripped off, leaving the oxide layer with an alignment opening 42 as shown in FIG.
5. At this point the implants are annealed to make them electrically active dopants by heating the wafer, according to one technique, to 850'C for 30 minutes with an arsine (AsH3) overpressure.
The active base region is then etched to thin it, using the existing oxide layer 36 as a mask. Wet chemical etching can be used to controllably.thin the active base region to about 800 Angstroms, for example. A proper orientation of the oxide mask to the crystallographic planes of the underlying material will yield sloped side walls 44 as shown in FIG. 6. In the next step, also shown in FIG. 6, an epitaxial emitter structure is grown over the entire wafer, using either molecular beam epitaxy or metal organic chemical vapor deposition. Emitter layer 46 is nominally Al.3Ga.7As. At the same time, the planar assist layer 22 is grown over the collector contact implant 20 through another opening in the oxide layer. A conventional cap is then grown on top of the emitter material.The cap may comprise a thin layer (about 300
Angstroms) of GaAs which compositionally grades to a layer of InGaAs with the same high n+ doping. The InGaAs layer is on the order of 1,000 Angstroms thick, and permits very low resistance, non-alloyed emitter contacts to be formed subsequently. The same cap structure is also applied over the layer 22 for the collector contact.
The result of the next several steps is illustrated in FIG. 7. First, a metallic layer such as tungsten is sputter deposited over the entire surface. This forms the metallization for the emitter and collector contacts to be defined subsequently. Next, a photoresist 48 is laid down over the entire surface and a selective photolithography process used to mask the emitter 4,30 and collector 22 contact areas. A plasma etch is performed to define the metal contact 32 for the emitter from the tungsten deposit, and a similar contact (element 24 in FIGs. 1 and 3) for the collector. The emitter 4 is defined by a wet chemical etch down to the oxide layer, after which the oxide layer is plasma etched away down to the base layer 10, except under the emitter area which is masked by photoresist section 48.The plasma etch leaves the oxide blocks 12 defining the opposite edges of the active base area.
Referring now to FIG. 8, after the emitter structure has been formed a positive photoresist 50 and selective photolithography is used to define the outer boundaries 52 for the base metal ohmic contacts, followed by the evaporation of Au/Mn or other suitable p-type ohmic contact metal 54 to form the base contact 26. The self-alignment between the base contact pad 26 and the emitter stripe 4 and emitter contact 32 results from an undercut in photoresist 48 masking the emitter structure 4,32. The ledge on the top of photoresist 48 shadow masks the base metal deposition to create the gap 56 between the inner base metal edges 58 and insulative blocks 12. The outer boundaries 52 of the base metal are defined by the separate photoresist layer 50.
Finally, the metal at areas removed from the desired contacts is lifted off by dissolving the underlying photoresist, and the wafer undergoes a rapid thermal anneal (for example 400-C for 30 seconds) to sinter the metal contacts for good ohmic behavior. The result is the planar self-aligned HBT depicted in FIGs. 1-3.
Since the base-collector junction is defined by the opening 40 in photoresist layer 38 (FIG. 4) and the baseemitter junction is defined by the opening 42 in oxide layer 36 (FIG. 6), with openings 42 and 44 in direct registration with each other, the two transistor junctions are automatically self-aligned. The resulting HBT is substantially planar, minimizes extrinsic capacitances and base resistance to enhance the high speed operation, is suitable for high density integrated circuits, and is also fully compatible with GaAs MESFET fabrication techniques.
GaAs MESFET fabrication also relies upon silicon ion implantation into semi-insulating GaAs substrates and refractory metals such as tungsten for their gate electrodes.
While several illustrative embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art, without departing from the spirit and scope of the invention. These may include semiconductor compositional variations, including the use of InP or other III
IV compound semiconductor materials as the semi-insulating substrate. When InP is used for the substrate, a narrower bandgap GaxIn1#xAs base layer is preferred, along with a Alylni-yAs emitter layer having a wider bandgap than the base layer. Accordingly it is intended that within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described.
Claims (16)
1. A self-aligned, heterojunction bipolar transistor (HBT), comprising:
a semi-insulating substrate,
a transistor base layer of one type doping on the substrate,
an emitter formed over the base layer of opposite type doping to said base layer, said emitter forming a junction with the base layer over a defined junction area,
a doped collector region formed in the substrate below the base layer and of opposite type doping to said base layer, said collector region forming a junction with the base layer over a defined junction area which is substantially aligned with said base-emitter junction,
base and emitter contacts on said base layer and emitter, respectively, establishing electrical contacts with said base layer and emitter,
a buried conductive layer in said substrate establishing an electrical connection with said collector region, and
a collector contact lateral to said collector region establishing an electrical contact with said buried layer, and thereby with said collector region.
2. The HBT of claim 1, wherein said collector region is lightly doped, and said buried conductive layer is a heavily doped layer of. same type doping as said collector region, said buried layer contacting the underside of said collector region.
3. The HBT of claim 2, further comprising an extension of said collector region extending laterally from the collector region over said buried conductive layer, said collector contact establishing an electrical contact with said buried layer through said collector region extension.
4. The HBT of claim 3, wherein said collector extension includes a generally conductive ion implant region extending from the collector contact at the substrate surface to said buried layer.
5. The HBT of claim 1, wherein said emitter contact comprises a metallic layer over the emitter, said collector contact comprises a generally conductive layer of semiconductor material of substantially equal thickness and of substantially equal composition and doping to said emitter and a metallic layer over said semiconductor layer of substantially equal thickness to said emitter contact metallic layer, whereby the surface of said HBT is substantially planar with respect to its depth.
6. The HBT of claim 1, said base layer comprising an active region forming said base-emitter and basecollector junctions, and a lateral extension of said active region to said base contact, said base extension being substantially thicker and having a substantially lower resistivity in the lateral direction than said active base region.
7. A self-aligned, heterojunction bipolar transistor (HBT), comprising:
a semi-insulating semiconductor substrate,
a transistor base layer of one type doping on the substrate, said base layer having an active region of reduced thickness compared to the remainder of the base layer,
a set of insulative regions on said base layer bounding said active region,
an emitter formed over said base layer and of
opposite type doping to said base layer, said emitter
forming a junction with said active base region and being
defined by said insulative regions,
a doped collection region formed in the sub
strate below the base and of opposite type doping to said
base layer, said collector region forming a junction with
said active base region in substantial alignment with said
base-emitter junction,
base and emitter contacts on said base layer and
emitter, respectively, establishing electrical contacts
with said base layer and emitter,
a buried conductive layer in said substrate
below said collector region of same type but heavier
doping as said collector region, said buried layer estab
lishing an electrical contact with said collector region,
and
a collector contact lateral to said collector
region establishing an electrical contact with said buried
layer, and thereby with said collector region.
8. The HBT of claim 7, wherein said collector
contact comprises a conductive contact pad and an ion
implant region in the substrate establishing an electrical
connection between said pad and said buried layer.
9. The HBT of claim 8, wherein said emitter contact
comprises a conductive layer over the emitter, said col
lector contact includes a conductive layer of substan -tially equal thickness to said emitter surmounted by said
contact pad, and the thickness of said collector region is
substantially greater than the thickness of either said
base layer or said emitter, whereby the surface of said
HBT is substantially planar with respect to its depth.
10. A method of forming a self-aligned heterojunction bipolar transistor (HBT), comprising:
forming a selective area base layer over a semiinsulating semiconductor substrate,
doping said base layer to one type doping,
masking said base layer with a mask having a junction defining opening,
implanting dopant particles of opposite type doping to said base doping into said substrate immediately below said base layer through said junction defining opening to establish a collector region in the substrate, said collector region forming a junction with the base layer which is aligned with said junction defining opening,
forming an emitter on said base through said opening, said emitter establishing a junction with said base which is defined by said opening and substantially aligned with the base-collector junction, and
establishing base, collector and emitter contacts.
11. The method of claim 10, said mask comprising a lower electrically insulative layer surmounted by an implant resistant layer, wherein said junction defining opening is formed in said implant resistant layer for implantation of said collector region, and extends through said insulative layer in registration with the opening in said implant resistant layer for formation of said emitter.
12. The method of claim 11, wherein said implant resistant layer is removed prior to formation of said emitter.
13. The method of claim 10, wherein said emitter is epitaxially grown over the base layer.
14. The method of claim 10, wherein said collector contact is formed above the substrate surface lateral to said junctions, and said collector contact is connected to the collector region by a lateral extension of the collector which extends through the substrate to the collector contact.
15. A method of forming a heterojunction bipolar transistor (HBT), comprising:
forming a doped base layer of one type doping over a semi-insulating substrate,
defining an active region in said base layer,
implanting dopant particles of opposite type doping to said base doping into said substrate below said active base region and extending laterally therefrom, said implant being performed at a concentration and energy level to form a doped collector region immediately below said active base region which establishes a junction with the base region, and a more heavily doped buried conductive layer below and in contact with said collector region,
forming an emitter over said active base region which is substantially aligned therewith and with said collector region, and
forming base and emitter contacts respectively on said base and emitter, and a collector contact to said buried layer.
16. The method of claim 15, wherein said collector contact is formed by implanting charged particles into the substrate to establish an electrical connection to said buried layer lateral to said active region.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26627888A | 1988-11-02 | 1988-11-02 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8924432D0 GB8924432D0 (en) | 1991-08-21 |
| GB2243716A true GB2243716A (en) | 1991-11-06 |
| GB2243716B GB2243716B (en) | 1993-05-05 |
Family
ID=23013915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8924432A Expired - Lifetime GB2243716B (en) | 1988-11-02 | 1989-10-31 | Self-aligned,planar heterojunction bipolar transistor and method of forming the same |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2243716B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2010580A (en) * | 1977-11-14 | 1979-06-27 | Tokyo Shibaura Electric Co | Method for manufacturing a semiconductor device |
| EP0004292A2 (en) * | 1978-03-27 | 1979-10-03 | International Business Machines Corporation | Process of making a MESA bipolar transistor with self-aligned base and emitter regions |
| EP0199497A2 (en) * | 1985-04-10 | 1986-10-29 | Fujitsu Limited | Process for fabricating a self-aligned bipolar transistor |
| EP0206787A2 (en) * | 1985-06-21 | 1986-12-30 | Matsushita Electric Industrial Co., Ltd. | Heterojunction bipolar transistor and method of manufacturing same |
| GB2179792A (en) * | 1985-08-28 | 1987-03-11 | Mitsubishi Electric Corp | Bipolar transistor |
| US4683487A (en) * | 1984-11-09 | 1987-07-28 | Hitachi, Ltd. | Heterojunction bipolar transistor |
| EP0255882A2 (en) * | 1986-08-07 | 1988-02-17 | Siemens Aktiengesellschaft | Npn bipolar transistor with extremely thin emitter/base structure and method for manufacturing the same |
| EP0289343A1 (en) * | 1987-04-30 | 1988-11-02 | Sony Corporation | Heterojunction bipolar transistors |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3877121D1 (en) * | 1987-10-23 | 1993-02-11 | Siemens Ag | METHOD FOR PRODUCING A PLANAR SELF-ADJUSTED HETEROBIPOLAR TRANSISTOR. |
| JP2851044B2 (en) * | 1988-03-30 | 1999-01-27 | 株式会社東芝 | Method for manufacturing semiconductor device |
| US4935797A (en) * | 1988-10-31 | 1990-06-19 | International Business Machines Corporation | Heterojunction bipolar transistors |
-
1989
- 1989-10-31 GB GB8924432A patent/GB2243716B/en not_active Expired - Lifetime
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2010580A (en) * | 1977-11-14 | 1979-06-27 | Tokyo Shibaura Electric Co | Method for manufacturing a semiconductor device |
| EP0004292A2 (en) * | 1978-03-27 | 1979-10-03 | International Business Machines Corporation | Process of making a MESA bipolar transistor with self-aligned base and emitter regions |
| US4683487A (en) * | 1984-11-09 | 1987-07-28 | Hitachi, Ltd. | Heterojunction bipolar transistor |
| EP0199497A2 (en) * | 1985-04-10 | 1986-10-29 | Fujitsu Limited | Process for fabricating a self-aligned bipolar transistor |
| EP0206787A2 (en) * | 1985-06-21 | 1986-12-30 | Matsushita Electric Industrial Co., Ltd. | Heterojunction bipolar transistor and method of manufacturing same |
| GB2179792A (en) * | 1985-08-28 | 1987-03-11 | Mitsubishi Electric Corp | Bipolar transistor |
| EP0255882A2 (en) * | 1986-08-07 | 1988-02-17 | Siemens Aktiengesellschaft | Npn bipolar transistor with extremely thin emitter/base structure and method for manufacturing the same |
| EP0289343A1 (en) * | 1987-04-30 | 1988-11-02 | Sony Corporation | Heterojunction bipolar transistors |
Non-Patent Citations (2)
| Title |
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| Applied physics letter, Vol.52 No10, 7 March 1988,pp822-824. * |
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Also Published As
| Publication number | Publication date |
|---|---|
| GB2243716B (en) | 1993-05-05 |
| GB8924432D0 (en) | 1991-08-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PE20 | Patent expired after termination of 20 years |
Expiry date: 20091030 |