GB2243702A

GB2243702A - Processing failure information

Info

Publication number: GB2243702A
Application number: GB9105577A
Authority: GB
Inventors: Brian Jerrold Arkin; Benjamin Joseph Brown; Richard Addison Reichert
Original assignee: Teradyne Inc
Current assignee: Teradyne Inc
Priority date: 1990-03-16
Filing date: 1991-03-15
Publication date: 1991-11-06
Anticipated expiration: 2011-03-15
Also published as: GB9105577D0; FR2659745B1; JPH05126905A; FR2659745A1; DE4108594C2; CA2038295A1; GB2243702B; JP2635229B2; DE4108594A1

Abstract

Failure information received from a node 20 of a circuit 22 under test is stored in a plurality of fail memories 76, 78. A failure information storage sequence is tracked 80, 82 as the information is stored in the fail memories, to allow the failure information sequence to be reconstructed. <IMAGE>

Description

!. z., PROCESSING FAILURE INFORMATION This invention relates to the

processing of failure information. More particularly it provides an apparatus and method f or processing f ailure information received from a node of a circuit under test.

It has previously been suggested to generate patterns which may be used in automatic test equipment by providing a high speed pattern generator which generates address sequences which are sent to a plurality of local generator circuits. Each local generator circuit includes a high speed local memory, a multiplicity of timing generators, a multipilicity of corresponding interpolators, a high speed f ormatter and a high speed fail processor. The timing generators and interpolators run in an interleaved fashion, with one timing generator/ interpolator set receiving and generating all even cycle information and the other set receiving and generating all odd information.

According to a first aspect of the present invention, there is provided an apparatus adapted for processing failure information operatively received from a node of a circuit under test, comprising: a fail processor configured operatively to receive test data from said node and adapted operatively to generate failure data based upon said test data; a plurality of fail memories, each fail memory being configured operatively to receive and to store certain said failure data; and a sequence memory configured operatively to store sequence information, said sequence information indicating in what order said failure data is stored in said plurality of fail memories.

In a second and alternative aspect thereof, the invention provides a method of processing failure information received from a node of a circuit under test, the method comprising the steps of: storing failure information from said node in a plurality of fail memories; and tracking a failure information storage sequence as said failure information is. stored in said plurality of fal memories to allow said failure information storage sequence to be reconstructed.

The invention is hereinafter more particularly described by way of example only with reference to the accompanying drawings, in which:- Fig. 1 is a schematic-block diagram of an embodiment of apparatus according to the present invention; and Figs. 2-4 are examples showing how failure information may be stored in the Fig. 1 apparatus.

Referring tp Fig. 1, test pat-&'--ern generator circuit 12, distribution circuit 14 and a plurality of local generator circuits 16. Each local generator circuit provides a signal at node 20 Ito a circuit under test (CUT) 22.

Pattern generator circuit 12 includes conventionally designed high speed pattern generator 30 which provides address patterns at a frequency or is 122.0703125 MHz (generally, and hereinafter, refferrecd to as "120 MHz", and its half as "60 MHz") and frequency divider circuit 32 which receives the high frequency patte-rns generated by pattern generator 30 and provides a pair of lower frequency addresses which are haff the frequency (i.e., 60 MHz) of the high frequency addresses generated by pattern generator 3 0.

14 includes a wair of DistributLon-circuit signal distribution paths 40, 42. Each signal distribution path 40, 42 includes a parallel-multibit bus which simultaneously provides the lower frequency address to a plurality of local generator circuits 16.

Each local generator circuit 16 includes a pair of signal generating circuits 50, 52. Signal generating circuit 50 includes local memory 54, which 40 and receives information from distribution path provides a data output to timing generator generator 56 which receives the data output anc- provides a timing generator output to interpolator circuit 58. Likewise, signal path '52 includes local memory 60, which receives information from distribution path 42, timing generator 62, which receives information from local memory 60, and interpolator circuit 64, which receives information from timing generator 62.

Interpolator circuits 58 and 64 provide signals to high speed fcrmat-ier 66. Formatter 66 is a conventional emitter coupled logic (ECL) high speed formatter which receives timing pulses and data and provides a two bit waveform indicating level and tristate at a particular time - Driver 68 receives these signals, and provides an output to node 20 having the is correct voltage levels and tri-state conditions for the particular CUT.

Dual detector 70 is also connected to node 20; dual detector 70 receives signals from node 20 and provides an output to high speed formatter 66.

High speed formatter 66 is also connected to a pair of fail processors 72, 74. Fail processors 72, 74 include respective fail mnemories 76, 78. Each fail memory 76, 78 includes sequence memory portion 80, 82.

Referring to Fig. 1, apparatus 10 both provides signals to and detects information from node 20 of'a CUT. More specifically, when providing signals to node 20, pattern generator 30 generatas address patterns at a frequency of 120 MHz. This inforiration is provided to frequency divider circui-,- 32 which receives the 120 MHz address patt-ern and provides two alternating cycles of half sDeed (i.e., 60 MHz) \1 address patterns to signal distribution paths 40, 42, respectively. Alternate cycles move respectively over lines 40 and 42, even over the former and odd over the latter; and successive cycles are 4 f i e d. by their leading edges. Because the ident.

pattern is frequency divided prior to transmission to local generators 16, signal distribution paths 40, 42 need only be appropriate_for transmitting signals having a.frequency of 60 MHz rather than signals having a frequency of 120 MHz.

At power-up and at che start-ulD ofeach pattern burst. Apparatus 10 is resynchronized. More specifically, frequency divider circuit 32 is con-.

figured so that at Dower-up, as well as when it is resynchronized, the next signal provided by frequency divider circuit 32 is over signal path 40.

it 14 provides the two Distribution circui half speed address patterns generated by divider circuit 32 to 5124 channels. Each channel includes a local generator circuit16, as shown in Ficj. 1.

Each local generator circuit 16 provides a high f.requency signal to, and detects a high frequency signal from, node 20. When detecting sig nals from node 20, dual detector receives the high frequency signal and provides the high frequency signal to formatter 66. Formatter 66 provides two half speed signals to fail processors 72, 74; the half speed signals correspond to the cycles of the half speed address patterns. Fail processors store the failure information in fail memories 76, 78, which function independently at half the speed of 1 1-1 formatter 66. Because fail memories 76, 78 function at half the speed of formatter 66, lower cost memories may be used.

Information may be stored in fail memories 76, 78 inone of three modes of operation. In a store all (Store All) mode, failure information is continually, alternately written into successive locations of fail memories 76, 78. Fig. 2 shows an example of how the failure information is-stored in the Store All mode. In a store this vector (STV) mode, failure written into the fail mem of avector bit. In a.

failure information is 76, 78 on cycles which may be chosen a combined shows an examDle of how stored in fail memories 76, 78 for the STV mode and the SOF mode. It is apparent from Fig. 3 that in the STV mode and the SOF mode the failure information is stored in the fail memory which corresponds to the cycle in which the information was generated. Accordingly, to recon struct the sequence in which the failur.e information was stored in fail memories 76, 78 further information.

is necessary. - In order to reconstruct the failure infor mation storage sequence, fail memories 76, 78 use respective sequence memory portions 80, 82. Fia.4 shows an example of how the failure and sequence in formation is stored in fail memories 76, 78 and information is selectively cries based upon the value store only fail (SOF) mode, written into fail memories contain a fail. or, there STV and SOF mode. Fig. 3 the failure information is 1 is sequence memory portion.s 80, 82. Sequence memory portions 80, 82 allow the failure information storage sequence to be reconstructed by traC_king the failure information as the information is stored. More specifically, a low isstored in a respective sequence memory portion if the previous write wasin the same path. A high is stored in a resDect-4ve sequence memory portion if he previous write was in the other path. By using this information, the failure information storage sequence can be easily reconstructed.

Fail processors 72, 74 may be connected. to a common sequence memory. By centrally storing the sequence information, the fail memories may operate independently. Additionally, because -the :sequence information is centrally stored, fail memories 72, 74 may be distribute without providing local means for determining the sequence of stored bits.

Additionally, while the preferred embod iment includes two signal generation paths, '-he system may operate with one signal generation path but a plurality of fail processors. In such a syste.n, the failure information may be stored at a lower frequency L-han the generated patterns.

Ad ditionally, while the pref erred embod--:np-nt includes two fail processors and two fail memor-ies, the systeri may also operate with one fail processor.and two fail nemorfes. In such a system, the failure information may be stored at a lower frequency than that at which the fail processor opezatcs.

J 1 If 1 1 v 7 - Additionally, while the preferred embodiment shows two fail memories, the number of fail memories may be increased simply by providin5 more bits to a sequence memory; the bits indicate where in which memory previous write is located.

1

Claims

1. An apparatus adapted for processing failure information operatively received from a node of a circuit under test, comprising: a fail processor configured operatively to receive test data from said node and adapted operatively to generate failure data based upon said test data; a plurality of fail memories, each fail memory being configured operatively to receive and to store certain said failure data; and a sequence memory configured operatively to store sequence information, said sequence information indicating in what order said failure data is stored in said plurality of fail memories.

2. Apparatus according to Claim 1, wherein said sequence information is arranged to be stored as said failure information is stored.

3. Apparatus according to Claims 1 or 2, wherein a plurality of said fail processors are provided, said apparatus further comprising a formatter configured operatively to receive said test data from said node and adapted operatively to provide a plurality of test data signals to respective said fail processors.

4. Apparatus according to Claim 3, wherein said plurality of fail processors correspond to said plurality of fail memories.

5. Apparatus according to any preceding claim, wherein said sequence memory allows said fail memories to function asynchronously.

6. Apparatus according to any preceding claim, wherein a plurality of said sequence memories are provided, each said sequence memory corresponding to a particular fail memory.

7. A method of processing failure information received from a node of a circuit under test, the method comprising the steps of: storing failure information from 1 J a 1 1 1 h said node in a plurality of fail memories; and tracking a failure information storage sequence as said failure information is stored in said plurality of fail memories to allow said failure information storage sequence to be reconstructed.

8. A method according to Claim 7, wherein said failure information includes a storage vector, and said failure information is stored in said failure memories on cycles in which said storage vector indicates to do so.

9. A method according to Claims 7 or 8, further comprising providing a fail processor configured to receive said failure information and to determine whether said failure information indicates a fail condition at said node, and storing only failure information which corresponds to a fail condition (STV, SOF, or both) in said plurality of memories.

10. A method of processing failure information received from a node of a circuit under test, substantially as hereinbefore described with reference to the accompanying drawings.

11. Apparatus adapted for processing failure information received from a node of a circuit under test, the apparatus being substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

12. A circuit comprising at least one node and an apparatus according to any of Claims 1 to 6 or 11, said apparatus being coupled to said node in order operatively to receive failure information therefrom.

Published 1991 at The Patent Office, Concept House, Cardiff Road, Newport, Gwent NP9 IRH. Further copies may be obtained from Sales Branch. Unit 6. Nine Mile Point, Cwnifelinfach, Cross Keys, Newport, NP I 7HZ. Printed by Multiplex techniques ltd. St Mary Cray, Kent.