GB2214339A

GB2214339A - Data input

Info

Publication number: GB2214339A
Application number: GB8901038A
Authority: GB
Inventors: Hitoshi Inaba
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1988-01-22
Filing date: 1989-01-18
Publication date: 1989-08-31
Anticipated expiration: 2009-01-18
Also published as: GB8901038D0; DE3901636C2; KR890012212A; JPH0628020B2; KR920001960B1; US5057836A; DE3901636A1; GB2214339B; JPH01187622A

Description

A 2214339 "DATA INPUT APPARATUS HAVING A MICROCOMPUTER" The present

invention relates to a data input apparatus which is simple in structure and has a key matrix and means capable of easily detecting which keys of the key matrix have been operated.

As is known in the art, electronic apparatuses such as TV receivers and video tape recorders comprises a data input apparatus which has a key matrix and a microcomputer and is designed to detect which keys of a key matrix have been operated.

The data input apparatus has a key matrix and a microcomputer. The key matrix comprises N lines of a first group, M lines of a second group, and M N key switches. The lines of the first group extend parallel to one another. The lines of the second group extend parallel to one another, and intersect at right angles with the lines of the first group. The key switches are located at the intersections of the lines of the first group and the lines of the second group. The microcomputer has M input ports and N output ports. The N output ports are connected to the lines of the first group, and the M input ports are connected to the lines of the second group. The microcomputer outputs, at the output ports, drive signals which are usually at a high level and periodically at a low level. The microcomputer is designed to output one low-level signal at a time. In other words, it sequentially outputs low-level i signals from the output ports to N lines of the first group.

If any one of the key switches is turned on, the microcomputer receives a low-level input signal at the input port connected to the line of the second group, which in turn is coupled to the key switch, and at the same time the microcomputer outputs a low-level drive signal to the line of the first group, which is coupled to this switch. Therefore, the microcomputer can determine which key switch has been turned on by detecting which input port receives a low-level input signal and when it receives the signal.

To determine which key switch has been turned on, the microcomputer needs to have M + N ports, i.e., M input ports and N output ports. The more ports a microcomputer has, the more difficult it is to manufacture the microcomputer in the form of an LSI circuit. Generally, a microcomputer requires 2./K-- or more ports when it is used in combination with a key matrix having K key switches.

An data input apparatus is known which has a microcomputer having only one input port and N output ports. This microcomputer can, therefore, be readily made in the form of an LSI circuit. It is combined with a key matrix, thus forming a data input apparatus. The key matrix comprises N lines of a first group, extending parallel to one another, and M lines of a second group, t1 Y extending parallel to one another and intersecting with the lines of the first group at right angles, and key switches located at the intersections of the lines of the first group and lines of the second group. The N lines of the first group are connected to the N output ports of the microcomputer. Each key switch is connected, at one end, to one line of the first group. Resistors are provided on each line of the first group, and located between the connecting points of the line and the key switches. The M lines of the second group are connected to the sole input port of the microcomputer and to one end of a resistor which is coupled at the other end to a constant-voltage terminal. A DC voltage is applied to this terminal.

The output ports of the microcomputer are usually open. The microcomputer is designed to output low-level signals sequentially, not simultaneously, through put ports. In other words, the low-level signals are supplied to the line of the first group, one after another. Further, the microcomputer can convert the voltage, which has been applied to the input port, into digital data representing this voltage.

If any of the key switches is turned on, the voltage identifying the key switch is applied to the input port of the microcomputer at the same time a low-level signal is output from any output port of the microcomputer. The microcomputer can therefore 4 - determine which key switch has been turned on, in accordance with the level of the input voltage and the time of outputting the low-level signal.

This data input apparatus is advantageous in that the microcomputer requires only one input port. The number J of all ports which the microcomputer must have in this case is given:

J = 1 + W(I + 1)1 where K is the number of key switches of the key matrix, and I is the number of resistors connected on a single line of the first group.

When the key matrix has 32 key switches, seven resistors are connected on the line of the first group. Hence, the number J of ports required is:

1 = 1 + 32/(7 + 1)1 = 5 That is, the microcomputer requires one input port and four output ports in this instance.

Although the microcomputer has less ports, it re quires more resistors than in the conventional data input apparatus. Consequently, this data input appara tus is, after all, as complex as the conventional one.

Generally, data input apparatuses of this type require more than H resistors, H being given:

H = I (L/(I + 1)) + 1 For example, when the key matrix of the apparatus has 32 key switches, seven resistors must be connected on the line of the first group. Hence, the number H of resistors is:

H = 7{32/(7+1)} + 1 = 29 As can be understood above, the conventional data input apparatus must be provided with a microcomputer which has many ports. To reduce the required number of ports which the microcomputer needs, the microcomputer must have more resistors.

The object of the present invention is to provide a data input apparatus having a microcomputer which requires only a small number of ports and also a small number of resistors, and is therefore simple in structure.

According to the present invention, there is provided a data input apparatus comprising a first group of lines extending parallel to one another, a second group of lines extending parallel to one another and intersecting with the lines of the first group at right angles, groups of key switches, the key switches being located at the intersections of the lines of the first group and the lines of the second group, for connecting the lines of the first group to the lines of the second group, pulse-supplying means for supplying periodic pulses to the lines of the first group at different times, a serial circuit comprised of a first group of resistors connected among the lines of the second group, a constant-voltage source connected to one end of the serial circuit by means of a second resistor, and detector means coupled to the pulse-supplying means and the connecting point of the serial circuit and the second resistor, for detecting the potential at this connecting point and for determining which key switch of any group has been operated, in accordance with this potential and also the times at which pulses have been supplied to the lines of the first group from the pulsesupplying means.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

Fig. 1 is a circuit diagram showing the data input apparatus according to a first embodiment of the present invention; Fig. 2 is a timing chart illustrating when the output ports of the microcomputer incorporated in the apparatus shown in Fig. 1 output low- level signals; Fig. 3 is a diagram showing how the reference voltage changes with time in the apparatus shown in Fig. 1; Figs. 4A to 4C are a flow chart explaining how the CPU used in the apparatus shown in Fig. 1 operates during a period TL1; Fig. 5 is a circuit diagram showing the data input apparatus according to a second embodiment of the present invention; and Fig. 6 is a timing chart illustrating when the output ports of the microcomputer incorporated in the apparatus shown in Fig. 5 output high-level signals.

Fig. 1 shows a first embodiment of the present invention, i.e., a data input apparatus which comprises key-matrix circuit 31 and microcomputer 44. Key-matrix circuit 31 has 32 key switches, or four groups of key switches 31a to 31d, each including eight key switches. More specifically, first group 31a has key switches 31al to 31a8; second group 31b has key switches 31bl to 31b8; third group 31c has key switches 31cl to 31c8; and fourth group 31d has key switches 31C to 31d8.

Key-matrix circuit 31 has two further groups of lines, i.e., the first group including four lines 32 to 35, and the second group including eight lines 36 to 43.

Lines 32 to 35 of the first group extend parallel to one another. Lines 36 to 43 of the second group also extend parallel to one another, and intersect with lines 32 to 35 at right angles. Key switches 31al to 31a8, 31bl to 31b8, 31cl to 31c8, and 31dl to 31d8 are arranged at the intersections of lines 32 to 35 of the first group and lines 36 to 43 of the second group. To be more precise, key switches 31al to 31a8 of first group 31a are connected to one end to line 32, and at the other end to lines 36 to 43, respectively. Similarly, key switches 31bl to 31bB of second group 31b are connected at one end to line 33, and at the other end to lines 36 to 43, respectively; key switches 31cl to 31c8 of third group 31c are coupled at one end to line 34, and at the other end to lines 36 to 43, respectively; key switches 3ldl to 31d8 of fourth group 31d are coupled at one end to line 35, and at the other end to lines 36 to 43, respectively.

Microcomputer 44 has four output ports 01 to 04 and one input port Iin. Lines 32 to 35 of the first group are connected to output ports 01 to 04, respectively.

Resistors Rl to R7 are connected among lines 36 to 43 of the second group, thus forming a serial circuit 45. One end of this serial circuit 45 is connected by resistor R8 to constant-voltage terminal 46. A DC voltage VDD is applied to this terminal 46. The connecting point of line 36 of the second group, resistor Rl, and resistor R8 is coupled to the input port Iin of microcomputer 44.

Microcomputer 44 comprises CPU 47, two output registers 48, 49, input register 50, internal bus 51, four FETs Ql to Q4, digital/analog (D/A) converter 52, and comparator 53. CPU 47 is connected by internal bus 51 to output registers 48 and 49 and also input register 50. Output register 48 is connected by FETs Ql to Q4 to output ports 01 to 04, respectively. Output register 48 turns on FET Ql, Q2, Q3 or Q4 in accordance with the 4-bit data supplied from CPU 47. Any of output ports 01 to 04 outputs a low-level pulse when the FET, which is S R coupled to the output port, is turned on. In other words, output port 01 to 04 perform an open-output function. As is shown in Fig. 2, output ports 01 to 04 are usually open, and sequentially output low-level pulses. More precisely, port 01 first supplies a lowlevel pulse, port 02 then outputs a low-level pulse, port 03 outputs a low-level pulse next, and, finally, port 04 supplies a low-level pulse. In Fig. 2, TL1, TL2, TL3, and TL4 are periods during which the signals output from output ports 01 to 04 remain at the low level.

Output register 49 supplies D/A converter 52 with the digital data supplied from CPU 47. D/A converter 52 converts the digital data into analog data, or a voltage. This voltage is applied, as a reference voltage Vref, to the first input to comparator 53. The voltage applied to input port Iin is applied to the second input of comparator 53. Comparator 53 compares the voltage applied to input port Iin, with the reference voltage Vref output by D/A converter 52, thus outputs a high-level data or a low-level data in accordance with the comparation result. The data representing the comparation result is stored in input register 50. From the data stored in input register 50, CPU 47 determines which key switch has been turned on.

CPU 47 detects the voltage applied to Iin during periods TL1, TL2, TL3, and TL4, input port when the pulse signals output from output ports 01, 02, 03, and 04 are at the low level. In other words, CPU 47 incre ments the data stored in output register 49, thereby raising the reference voltage Vref (i.e., the output of D/A converter 49). That is, CPU 47 raises the voltage Vref step by step, from the minimum value MIN (=O) to the maximum value MAX (=VDD). (Alternatively, CPU 47 can lower the reference voltage Vref from maximum value MAX to the minimum value MIN.) Whenever the reference voltage Vref rises above the voltage applied to input port Iin, that is, the data output by comparator 53 becomes a high-level data from a low-level data, the voltage input to microcomputer 44 can be detected. As is shown in Fig. 3, the reference voltage Vref is raised seven times and has eight different values during the period any pulse signal output by microcomputer 44 remains at the low level, each time by 1/8 VDD. This because each group of key switches inxcludes eight key switches in this embodiment. (According to the inven- tion, the number of different values which the voltage Vref can have is equal to the number of the key switches forming each group.) In Fig. 3, VK1 to VK8 are the voltages which are applied to input port Iin when one key switch of any group is operated.

Resistors Rl to R8 have such resistances that voltages VK1 to VK8 are applied to input port Iin of microcomputer 44. The resistances of resistors R1 to R8 9 - 11 are determined by the resolution of D/A converter 51. In the first embodiment, the resistances are given by solving the following simultaneous equations:

1 VDD < W2 < 9 VDD < VK3 < VDD < W4 < 2 8 2_ 8 VDD < W5 <.1 VDD 8 VDD < VK6 < VDD 8 VDD < VK7 < VDD VK2 Rl R1+R8 R1+R2 R1+R2_+R8 R1+R2+R3 R1+R2+R3+R8 VK5 R1+R2+R3+R4 R1+R2+R3+M+R8 VK6 R1+R2+R3+R4+RS R1+R2+R3+R4+R5+Rg R1+R2+R3+R4+R5+R6 R1+R2+R3+R4+R5+R6+R8 7 VDD < W8 < VDD VK8 R1+R2+R3+R4+R5+R6+R7 J Rl+R2+R3+R4+R5+R6+R7+i-8 In order to determine which of the key switches coupled to line 32, which in turn are connected to output port 01, i.e., key switches 31al to 31a8 of the first group, has been turned on, CPU 47 checks how the voltage applied to input port Iin during the period TL1. Hence, CPU 47 determines that the key switch which is connected at one end to line 32 coupled to output port 01, and at the other end to one of lines 36 to 43 which applies the voltage checked by CPU 47, has been turned on. More specifically, if the voltage applied to input port Iin is lower than 1/8 VDD, CPU 47 determines that key switch 31al which is connected to line 32 of the first group and line 36 of the second group, has been VDD VK3 = VDD VK4 = 1 VDD 8 VK7 = 12 - turned on; if said voltage is lower than 2/8 VDD, CPU 47 determines that key switch 31a2 which is coupled to line 32 of the first group and line 37 of the second group, has been turned on; and so forth. And, if said voltage is lower than VDD, CPU 47 determines that key switch 31a8 which is coupled to line 32 of the first group and line 43 of the second group, has been turned on.

Figs. 4A to 4C are a flow chart explaining how CPU 47 operates during the period TL1.

To determine which one of those key switches coupled to lines 33 to 35 which in turn are connected to output ports 02 to 04, CPU 47 also detect the level of the voltage applied to input port Iin during periods TL2 to TL4. For this purpose, CPU 47 operates almost in the same way as is explained by the flow chart of Figs. 4A to 4C. More specifically, when any of key switches 31al to 31a8, 31bl to 31bB, 31cl to 31c8, and 3ldl to 3ld8 is turned on, a voltage of the level identifying the operated key switch is applied to input port Iin at the every time a low-level pulse is output from one of out put ports 01 to 04. Thus, CPU 47 of microcomputer 44 can determine which key switch has been turned on, in accordance with the level of the voltage applied to input port Iin and the time of the application of when the voltage was applied to input port Iin.

In the case of a data input apparatus of the struc ture similar to that shown in Fig. 1, the microcomputer must have J ports, and H resistors must be used. J and H are given as follows:

j = 1 + {K/(I + 1)} H = I + 1 In the above equations, K is the number of key switches used in key matrix 31, and I is the number of resistors forming serial circuit 45.

In the case of the embodiment shown in Fig. 1, K = and I = 7. Hence, the required number J of ports, the required number H of resistors are:

J 1 + {32/(7 + 1)l = 5 H 7 + 1 = 8.

Hence, it suffices for the embodiment to have only five ports and only eight resistors.

Fig. 5 shows a second embodiment of the present in vention, i.e., a data input apparatus having microcompu ter 44' whose output ports are usually closed. Namely, the second embodiment identical to the first embodiment, except that transistors Q11, QP, W', and 03' are pro vided outside microcomputer 441, not within a microcom puter as in the first embodiment (Fig. 1).

In the data input apparatus shown in Fig. 5, micro computer 441 outputs high-level pulses, sequentially via four output ports 01', OV, OV, and OV, as is shown in Fig. 6. Output ports oll, 021, 031, and 04' are coupled to the bases of NPN transistors Ql', Q21, Q3', and QV, respectively. The emitters of these transistors are 32, an - 14 connected to the ground. The collectors of these transistors are coupled to lines 32 to 35 of the first group, respectively. Hence, lines 32, 33, 34, and 35 can be sequentially set at a low potential, usually in their open state. The data input apparatus can operate in the same way as the first embodiment (Fig. 1).

In either embodiment, when two or more key switches of the same group are operated simultaneously, that one through which the lowest voltage is applied to the input port Iin of the microcomputer is regarded as has been operated. In other words, the greatest priority is given to the key switches coupled to line 36; the second priority to those connected to line 37; the third priority to those coupled to line 38, and so forth. And the least priority to the key switches connected to line 43. Thus, it is advisable to assign high priorities to the important key switches such as the key switch for inputting a power-supply command which should be correctly input by all means.

As has been described in detail, the present inven tion can provide a data input apparatus which requires only a relatively small number of ports and a relatively small number of resistors even if provided with a great number of key switches. The data input apparatus according to the invention can be useful as a machine interface containing a microcomputer. Moreover, the number of the lines connecting the key matrix to the microcomputer which is located away from the matrix can be small.

1

Claims

Claims:

1. A data input apparatus comprising:

a first group of lines extending parallel to one another; a second group of lines extending parallel to one another and intersecting with the lines of the first group at right angles; groups of key switches, said key switches being located at the intersections of the lines of the first group and the lines of the second group, for connecting the lines of the first group to the lines of the second group; pulse-supplying means for supplying periodic pulses to the lines of said first group at different times; a serial circuit comprised of a first group of resistors connected among the lines of the second group; a constant-voltage source connected to one end of said serial circuit by means of a second resistor; and detector means, coupled to said pulse-supplying means and the connecting point of said serial circuit and said second resistor, for detecting the potential at this connecting point and for determining which key switch of any group has been operated, in accordance with this potential and also the times at which pulses have been supplied to the lines of said first group from said pulse-supplying means.

2. The apparatus according to claim 1, wherein 1.

S 4 1 - 17 said pulse-supplying means includes a low-level pulse supplying means for holding the lines of said first group usually in open condition and for supplying periodic low-level pulses to these lines at different times.

3. The apparatus according to claim 2, wherein said low-pulse supplying means includes:

a plurality of switching means connected to the lines of said first group, for holding these lines usually in open condition and for connecting hese lines to the ground; and switch control means for causing said switching means to connect the lines of said first group to the ground periodically at different times.

4. The apparatus according to claim 3, wherein said switching means, said switch control means, and said detector means are formed as a single large-scale integration circuit.

5. The apparatus according to claim 4, wherein said detector means includes:

potential-discriminating means for discriminating the potential at the connecting point of said serial circuit and said second resistor, by comparing this potential with a reference voltage changing step by step; and key-detecting unit for detecting which key switch of any group has been operated, in accordance with the p a potential discriminated by said potential-discriminating means and also with which said switch control means connects line of the first group to the ground by any of the switching means.

6. The apparatus according to claim 3, wherein said switch control means and said detector means are formed as a single large-scale integration circuit.

7. The apparatus according to claim 6, wherein said detector means includes:

potential-discriminating means for discriminating the potential at the connecting point of said serial circuit and said second resistor, by comparing this potential with a reference voltage changing step by step; and key-detecting unit for detecting which key switch of any group has been operated, in accordance with the potential discriminated by said potential-discriminating means and also with which said switch control means con nects line of the first group to the ground by any of the switching means.

8. A data input apparatus having a microcomputer, substantially as hereinbefore described with reference to the accompanying drawings.

Published 1989 at The Patent Offire, State I-louse, 86,71 HigbLEolbom, londonWCIR4TP.Purther copiestnaybe obtainedfrom Thepatentofftce. Saleo Bran-?a. St. Mar- Cra, 0,'oingnon. Xeiit LRG OEM Printed by Multiplex techniques ltd, St Mary Cray, Kent, Con- 1/87 T