GB2210739A

GB2210739A - Spread spectrum receiver

Info

Publication number: GB2210739A
Application number: GB8723463A
Authority: GB
Inventors: Alistair Henry Tweedie
Original assignee: Honeywell Control Systems Ltd
Current assignee: Honeywell Control Systems Ltd
Priority date: 1987-10-06
Filing date: 1987-10-06
Publication date: 1989-06-14
Also published as: GB8723463D0

Abstract

In a direct sequence spread spectrum receiver for signals having the carrier phase modulated by an information signal and a pseudo random code sequence, the carrier signal and the pseudo random code are demodulated by a carrier phase locked loop 1-8 and a code tracking loop which overlap and share in-phase and quadrature mixers 1, 2 and filters 4, 5. The carrier phase lock loop 1-7 may be a conventional costas loop and a demodulated output is obtained from limiter 8. In the tail dither code tracking loop shown, the incoming code-carrying signal is compared with phase advanced and phase delayed versions of a locally generated code to derive a timing error for adjusting a local VCO 16 so that the received signal occurs midway between the two versions. A local code generator 15 is driven by the oscillator 16 output via a phase-shifter 17 which alternately advances and retards the oscillator phase under control of a dither generator 18. A delay locked loop in which the error signal directly controls a code generator may alternatively be used. <IMAGE>

Description

SPREAD SPECTRUM RECEIVER The present invention relates to spread spectrum receivers, and more specially to direct sequence (pseudo noise) systems.

A direct sequence spread spectrum system is one in which a carrier is phase modulated by an information signal and also by a digital code sequence the bit rate of which is much higher than the information signal bandwidth. The digital code sequence is normally generated by a pseudo-random bit sequence generator.

To receive such a signal, two distinct reference signals are required in the receiver, a carrier reference and a pseudo-random sequence reference. These references must be maintained in phase lock with the carrier of the received signal and the pseudo-random sequence in order to demodulate the signal and extract the information signal.

The carrier phase is controlled by a carrier phase locked loop and the pseudo-random sequence phase is controlled by a pseudo-random sequence phase locked loop, more commonly referred to as a code tracking loop, which term will be used hereinafter.

Various techniques are available for implementing a carrier phase locked loop, a Costas loop commonly being employed. The principle of the Costas loop is that the incoming signal is fed to two parallel paths, termed in-phase and quadrature paths: in each path the incoming signal is multiplied by an internal signal from a voltage controlled oscillator (VCO) (one of the two multiplying signals being in quadrature with the other), the two product signals are each lowpass filtered or integrated and dumped and the resultant signals are multiplied together to produce a control signal for the VCO.

More specifically, the Costas loop can be briefly explained as follows. Ignoring all modulation for the moment, the received carrier may be represented as 9 cos wt. The two internal signals generated by the VCO may be represented as cos (wt+y) and sin (wt+y), the in-phase and quadrature signals, respectively, where y is the phase error with respect to the received signal. The product of the received and reference signals in the in-phase path is: k (cos y + cos (2wt +y)] 2 and in the quadrature path is A (sin y + sin (2wt + y)].

2 after the lowpass filters (or integrate and dump circuits) the in-phase and quadrature signals are: A cos y and x sin y respectively, 2 2 since the twice carrier(2w) terms are removed. The product of these two signals is: k sin 2y 8 Thus the system as described so far generates a control signal sin 2y which is dependent on the phase difference (y) between the received signal and the internal reference signals and can thus be used to control the VCO to keep this phase error close to zero. Of course, there are various elaborations and modifications of the basic Costas loop as just described.

Various techniques are also available for implementing a code tracking loop, one commonly employed is known as a delay lock loop. The code is often termed a pseudo-noise (PN) code. In such a loop, the incoming code-carrying signal is compared with an early and a late version (in the phase sense) of a locally generated replica of the code, and the difference between these two signals correlated with the incoming signal to indicate the timing error of the incoming signal relative to the local generator. The difference signal is used to adjust the timing of the local generator, e.g. by the use of a clock VCO, so that the received signal occurs midway between the two local replicas of the code.

There is a modification or variant of this technique known as a tau dither loop. In this, there is a single correlation path which is fed with the incoming signal and alternately with the early and late versions of the locally generated code. Thus the two correlation signals, between the incoming signal and the two local versions of the code, are generated alternately by the single correlation path. By processing the resulting alternating signal, the difference between the two correlation signals is produced. This system may be regarded as the time-sharing use of a single physical correlation channel to simulate two logic channels.

More specifically, a tau dither loop can be briefly explained as follows. The incoming signal is a carrier frequency which is modulated with both the information signal and the code sequence. This is mixed in a multiplier with an internal code sequence which is generated by a code generator which is driven by a code frequency clock via a phase shifter which alternately advances and retards the clock phase at the dither rate.

The mixed signal is fed through a bandpass filter, centred at the carrier frequency and with a bandwidth sufficient only to allow through the information signal and to reject all other frequency components to very low levels. The bandpass filter output is then passed to a square law envelope detector. The output of this detector is passed through a multiplier, which is fed with the same dither control signal as the phase shifter to ensure that the correlation signals for the advanced and retarded intervals have opposite signs, to a loop filter which is a lowpass filter with a cut-off frequency well below the dither rate. This loop filter feeds a VCO which acts as the code frequency clock.

The object of the present invention is to simplify the known arrangement of carrier locking loop and code tracking loop in a direct sequence spread spectrum receiver.

According to the present invention there is provided a direct sequence spread spectrum receiver comprising a carrier phase locked loop and a code tracking loop, characterised in that the carrier phase locked loop and the code tracking loop are arranged to overlap, and in that the carrier signal and the pseudo random code are demodulated using common in-phase and quadrature channel mixer means and filter means.

Thus the present invention affords a significant saving in components without detracting from the function of the carrier phase locked loop and the code tracking loop.

The carrier phase locked loop may be a Costas loop and the code tracking loop may be a tau dither loop or a delay locked loop, for example.

Direct sequence spread spectrum receivers in accordance with the present invention will now be described in greater detail, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block circuit diagram of a first embodiment, Figure 2 is a block circuit diagram of a second embodiment which is a modified version of the embodiment of Figure 1, Figure 3 is a block circuit diagram of a third embodiment, and Figure 4 is a block circuit diagram of a fourth embodiment which is a modified version of the embodiment of Figure 3.

Referring first to Figure 1 of the drawings, the spread spectrum receiver embodies a Costas loop comprising two multiplicative mixers or multipliers 1 and 2 to which a received signal is applied from an input I/P. The two mixers 1 and 2 are fed with signals which may be taken for the moment as cos wt and sin wt, the outputs of a carrier frequency VCO (voltage controlled oscillator) 3. The mixer 2 is the start of an in-phase channel I, and mixer 1 is the start of a quadrature channel Q. Each mixer 1 and 2 feeds a respective Low pass filter 4 and 5, the outputs of which are fed to a multiplier 6. The multiplier 6 feeds the carrier frequency to the VCO 3 via a loop filter 7.

The output of the filter 5 is shown fed to the multiplier 6 via a hard limiter 8, which gives a binary output - in this instance, +1 if the output of the filter 5 is positive, and -1 if it is negative. This is a known technique which slightly modifies the details of the operation of a Costas loop without changing its essential principles and may, in some circumstances, slightly enhance its peformance. It also simplifies the construction of the multiplier 6, since the multiplier then need only either pass the output from the filter 4 unchanged or reverse its sign.

Of course, if the filters 4 and 5 are digital, the multiplier 6 becomes a digitial multiplier, and in fact has to do no more than change the sign bit of the output of the filter 4 if the output of the hard limiter 8 is -1. The hard limiter 8 in turn becomes merely a connection of the sign bit from the output of the filter 5, the amplitude bits all being dropped. The loop filter 7 may have a digital implementation of known type, and the VCO 3 may either be an analog circuit or a digitial one which synthesizes the functions sin wt and cost wt and then converts them to analog form by digital-to-analog converters.

The Costas loop comprising the components 1 to 7 described above maintains lock with the incoming signal on the input I/P at the carrier frequency in the manner described above.

The spread spectrum receiver also comprises a code tracking loop which, in accordance with the present invention is arranged to overlap the carrier phase locked loop with the mixers 1 and 2 and the filters 4 and 5 being common to both Loops. The code tracking loop also comprises squarer circuits 9 and 10 which the respective outputs of the filters 4 and 5 are applied. The outputs of the squarers 9 and 10 are applied to a summer 11, the output of which is applied to a square root circuit 12.

It will be recalled that in the Costas loop, the output of the lowpass filters 4 and 5 in the in-phase and quadrature channels I and Q are proportional to cos y and sin y, where y is the phase difference between the incoming received signal and the carrier frequency VCO output. The effect of squaring and adding these two signals is therefore to make the signal from the summer 11 independent of this phase difference. The signals from the filters 4 and 5 are also, of course, proportional to the amplitude of the carrier signal. The squarers 9 and 10 make the signal from the summer 11 proportional to the square of the carrier amplitude, and the square root circuit 12 gives an output which is again proportional to the amplitude of the carrier signal.

Looking again at the multipliers 2 and 1, these are fed with the carrier frequency VCO 3 outputs cos wt and sin wt, but via multipliers 13 and 14 rather than directly, as has been assumed up till now. These two multipliers 13 and 14 are part of both the Costas loop and the code tracking loop and are fed by a code sequence or pseudo random generator 15, forming part of the code tracking loop, whereby the signals fed to the multipliers 2 and 1 are in fact the carrier frequency VCO 3 signals modulated by the locally generated code sequence.

Xccordingly, the signal from the square root circuit 12 is not merely proportional to the input signal, but is dependent on the input signal as demodulated by the pseudo random sequence from the generator 15.

The generator 15 is driven by VCO 16, via a phase shifter 17. k dither generator 18 generates a square wave which controls the phase shifter 17 to alternately advance and retard the phase of the clock signal passing to the generator 15. Thus the code sequence from the generator 15 is alternately advanced and retarded.

If the mean phase position of the local code sequence from the generator 15 were exactly in phase with the code sequence of the received signal at the input I/P, the output from the square root circuit 12 would be constant. This is because the local PN code sequence is being dithered between two phase positions, advanced and retarded by equal amounts with respect to the correct phase position and the amplitude of the square root circuit output is direclty proportional to phase error between received and locally generated PN codes, however not dependent on the sign of this phase error.

If the mean phase position of the local code sequence from the generator 15 were slightly advanced or retarded in phase with respect to the received code sequence, the output from the square root circuit 12 would not be constant but would step between two levels as the dither generator advances and retards the local code sequence phase. This is because as the dither generator advances the local code sequence phase, it is moved further out of phase or more in phase, as the case may be, decreasing or increasing the amplitude of the output signal of the square root circuit 12 and as the dither generator retards the local code sequence phase, it is moved more in phase or further out of phase, thus increasing or decreasing the amplitude of the output signal of the square root circuit.

Thus for the situation where a small mean phase error exists between the locally generated code sequence and the received signal, the output of the square root circuit 12 consists of a dc level (portional to the mean received signal amplitude) with a square wave superimposed on it the amplitude of which is proportional to the mean phase error and who's phase (i.e. o0 or 1800) with respect to the dither generator square wave is dependent on the sign of the phase error. after the output of the square root circuit 12 has been multiplied by the dither square wave from the dither generator 18 in a multiplier 19 and filtered by a loop filter 20, the dc component of the output of the square root circuit 11 has been removed and the square wave component has been converted to a signal with a polarity according to the phase of the square wave and amplitude proportional to the amplitude of the square wave.

The filter 20 feeds the PN clock VCO 16, to control it so as to keep the PN generator 15 in synchronism with the PN code sequence of the received signal. Thus the dither loop is implemented, using the two channels of the Costas loop, together with the components 9, 10, 11 and 12, as the mixer, bandpass filter, and envelope detector of the dither loop.

It will of course be realised that the details of the circuitry can be changed without affecting the principles of operation. For example, the squarers 9 and 10 could be replaced by units which output the modulus of an input, i.e. leaving the input unaltered if it is positive and inverting it if it is negative. klso the square root circuit 12 could be omittea. These modifications have the advantage of ease of implementation but have inferior performance.

Data is often modulated onto the transmitted binary pseudo random sequence using the technique of sequence inverse keying (exclusive OR-ing the data with the pseudo random sequence prior to modulation of the carrier). It is then possible to extract this data from the receiver after the hard limiter 8 once sequence and carrier lock have been achieved.

It is possible to peform pseudo random sequence search and acquisition of correct sequence phase using the conventional stepping or sliding correlator techniques. Similarly carrier phase acquisition techniques as used in normal Costas loops may be employed.

Figure 2 of the drawings illustrates an alternative embodiment based on that of Figure 1 in as much as it comprises a Costas loop and a multi-channel (four) tau dither loop. The four channels of the dither loop comprise first multipliers 21, 22, 23 and 24 the outputs of which are applied to respective multipliers 25, 26, 27 and 28. The outputs of the second multiplier 25 to 28 are applied to respective lowpass filters (which optionally may be integrate and dump circuits) 29, 30, 31 and 32, the outputs of which are applied to respective modulus circuits 33, 34, 35 and 36. The outputs of the modulus circuits 33 to 36 are applied to a summer 37, the output of which is applied at one input to a further multiplier 39 which receives another input the output of a dither generator 40. The output of the multiplier 39 is applied to a voltage controlled oscillator 41 via a loop filter 42.The output of the VCO 41 is applied as one input to a phase shifter 38 which receives as a second input the output from the dither generator 40.

The output of the phase shifter 38 is applied to a pseudo random generator 43, the output of which is applied as one input to each of the first multipliers 21 to 24, second inputs being provided by an oscillator 44, these second inputs being, respectively, cos wt, cos (wt + 450), sin wt and sin (wt + 450).

The Costas loop comprises the second multiplier 25 and lowpass filter 29 of one dither channel, and multiplier 27 and lowpass filter 31 of another dither channel to form the in phase (I) and quadrature (Q) channels of the Costas loop. The outputs of the lowpass filters 29 and 31 are applied as inputs to a multiplier 45, the output of the lowpass filter 29 optionally being applied to the multiplier 45 via a hard limiter 46. The output of the multiplier 45 is applied to the oscillator 44 via a loop filter 47. The information or output signal is taken from the output of the lowpass filter 29.

Thus, in the second embodiment of the invention, the components common to the Costas and dither loops are the second multipliers 25 and 27 and the lowpass filters 29 and 31.

Turning now to Figure 3 of the drawings, this illustrates a third embodiment of the present invention which combines a Costas loop with a delay locked loop.

The delay locked loop comprises two channels to which the received signal is applied from the input I/P, each channel comprising two further channels having multipliers 48 and 49 receiving the signal on the input I/P as one input and having their output supplied to respective lowpass filters 50 and 51. The outputs of the lowpass filters 50 and 51 are applied to respective squarer circuits 52 and 53 the outputs of which are summed in a summer 54, the output of which is applied as one input to a subtractor 55. The other input to the subtractor 55 is taken from the summer 54 of the other parallel channels of the basic second channel of the loop. The outputs of the two summers 54 may be applied to the subs tractor 55 via respective square root circuits shown in phantom in Figure 3.The output of the subtractor 55 is applied, via a loop filter 56, to a pseudo random generator 57 the output of which is applied to respective multipliers 58 and 59, the output of the multiplier 58 being applied as a second input to the multipliers 48 of the two sub channels and the output of the multiplier 59 being applied as a second input to the multipliers 49 of the sub channels. 9 second input to the multipliers 58 and 59 is applied by a voltage controlled oscillator 60 which receives an input, via a loop filter 61, from a multiplier 62 which may be arranged to receive as inputs the outputs of the lowpass filters 50 and 51 of one or other of the two channels of the delay locked loop. Two such multipliers 62 are shown but only one would be employed in practice.

The Costas loop can therefore comprise the multipliers 48 and 49, the lowpass filters 50 and 51 and the multiplier 62 of one or other of the pairs of sub channels of the delay locked loop, these components being common to both loops.

The fourth embodiment of the present invention is a modification of the third embodiment of Figure 3 and is illustrated in Figure 4 of the accompanying drawings.

The modification being by way of the delay locked loop being of multi-channel form, four channels being employed. In this respect, this embodiment is somewhat similar to that of Figure 2 of the drawings. Each of the two main channels of the delay locked loop comprises four sub channels having respective multipliers 63, 64, 65 and 66 the outputs of which are applied to respective lowpass filters 67, 68, 69 and 70. The outputs of the lowpass filters 67 to 70 are applied to respective modulus circuits 71, 72, 73 and 74. The outputs of the modulus circuits 71 to 74 are applied as inputs to a summer 75, the output of which is applied as one input to a subtractor circuit 76, the other input being applied from the other channel of the delay locked loop. The output of the subtractor 76 is applied, via a loop filter 77, to a pseudo random generator 78.The output of the pseudo random generator 78 is applied as one input to four multipliers 79, 80, 81 and 82, the outputs of which are applied as second inputs to the respective multipliers 63, 64, 65 and 66 of the -sub channels of the two main channels of the delay locked loop. Second inputs to the multipliers 79 to 82 are applied by a voltage controlled oscillator 83, the inputs respectively representing cos wt, cos (wt + 450), sin wt and sin (wt + 45 ). The voltage controlled oscillator 83 receives an input, via a loop filter 84, from a multiplier 85 which is provided in one or other of the main channels of the delay locked loop. Xs with the embodiment of Figure 3, only one such multiplier will be provided in practice but two are shown in Figure 4 to illustrate the two alternative arrangements. More specifically, the multipliers 85 receive two inputs from the lowpass filters 67 and 69 and these filters, together with their associated multipliers 63 and 65, form the components which are common to both the costas loop and the delay lock loop.

although the embodiments of Figures 2 and 4 illustrate four-channel arrangements, it will be understood that different numbers of channels may be employed.

It will be appreciated that the present invention provides a direct sequence spread spectrum receiver having overlapping phase locked and code tracking loops with a significant saving in components yet without detracting from the function of either loop.

Claims

1. A direct sequence spread sprectrum receiver comprising a carrier phase locked loop (1 to 8) and a code tracking loop (9 to 20), characterised in that the carrier phase locked loop and the code tracking loop are arranged to overlap, and in that the carrier signal and the pseudo random code are demodulated using common in-phase and quadrature channel mixer means (1, 2) and filter means (4, 5).

2. A receiver according to claim 1, characterised in that the carrier phase locked loop is a costas loop (1 to 8) and the code tracking loop (9 to 20) is a tau dither loop.

3. A receiver according to claim 2, characterised in that the tau dither loop is a multi-channel dither loop (21 to 47).

4. A receiver according to claim 1, characterised in that the code tracking loop is a delay locked loop (48 to 59).

5. A receiver according to claim 4, characterised in that the delay locked loop is a multi-channel loop (63 to 82).

6. h receiver according to any of the preceding claims, characterised in that the filter means in the in-phase and quadrature channels are in the form of lowpass filters.

7. A receiver according to any of claims 1 to 5, characterised in that the filter means in the in-phase and quadrature channels are in the form of integrate and dump circuits.

Amendments to the claims have been filed as follows Claims 1. 9 direct sequence spread sprectrum receiver comprising a carrier phase locked loop (1 to 8) and a code tracking loop (9 to 20), characterised in that the carrier phase locked loop and the code tracking loop are arranged to overlap, and in that the carrier signal and the pseudo random code are demodulated using common in-phase and quadrature channel mixer means (1, 2) and filter means (4, 5).

2. k receiver according to claim 1, characterised in that the carrier phase locked loop is a costas loop (1 to 8) and the code tracking loop (9 to 20) is a tau dither loop.

3. k receiver according to claim 2, characterised in that the tau dither loop is a multi-channel dither loop (21 to 47).

4. k receiver according to claim 1, characterised in that the code tracking loop is a delay locked loop (48 to 59).

5. k receiver according to claim 4, characterised in that the delay locked loop is a multi-channel loop (63 to 82).

6. k receiver according to any of the preceding claims, characterised in that the filter means in the in-phase and quadrature channels are in the form of lowpass filters.

7. k 4 receiver according to any of claims 1 to 5, characterised in that the filter means in the in-phase and quadrature channels are in the form of integrate and dump circuits.

8. A direct sequence spread spectrum receiver substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.