JPH0761023B2 - Interference compensation circuit - Google Patents
Interference compensation circuitInfo
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- JPH0761023B2 JPH0761023B2 JP60287881A JP28788185A JPH0761023B2 JP H0761023 B2 JPH0761023 B2 JP H0761023B2 JP 60287881 A JP60287881 A JP 60287881A JP 28788185 A JP28788185 A JP 28788185A JP H0761023 B2 JPH0761023 B2 JP H0761023B2
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Description
【発明の詳細な説明】 （産業上の利用分野） 本発明はディジタル通信方式においてディジタル信号が
受ける他方式からの干渉を除去する干渉補償回路の構成
に関するものである。Description: TECHNICAL FIELD The present invention relates to a configuration of an interference compensation circuit that removes interference from other systems that a digital signal receives in a digital communication system.
（従来の技術） 従来の基本的な干渉補償回路の構成例を第５図に示す。(Prior Art) FIG. 5 shows a configuration example of a conventional basic interference compensation circuit.
主アンテナ１から受信した主信号は合成回路３に入力さ
れる。一方、補助アンテナ２から受信した干渉信号は可
変振幅位相回路４で主信号中にもれ込んだ干渉成分とほ
ぼ等振幅、逆位相となるように設定され、その信号は合
成回路３に入力される。合成回路３の出力は、完全に消
去できなくて残留している干渉信号と補助アンテナ出力
の干渉信号との相関をとる相関器６に通し、その出力を
積分器５に通して、可変振幅位相回路を制御している。
制御ループは、残留干渉信号と、干渉信号との相関が最
小となるように動作する。ここで、相関器６の入力信号
は振幅および位相を含む複素信号であり、可変振幅位相
器４も複素量として扱っている。The main signal received from the main antenna 1 is input to the combining circuit 3. On the other hand, the interference signal received from the auxiliary antenna 2 is set by the variable amplitude phase circuit 4 so as to have almost the same amplitude and opposite phase as the interference component leaked into the main signal, and the signal is input to the synthesis circuit 3. It The output of the synthesizing circuit 3 is passed through a correlator 6 that correlates the interference signal that cannot be completely erased and remains with the interference signal of the auxiliary antenna output, and the output is passed through an integrator 5 to obtain a variable amplitude phase. Controlling the circuit.
The control loop operates to minimize the correlation between the residual interference signal and the interference signal. Here, the input signal of the correlator 6 is a complex signal including amplitude and phase, and the variable amplitude phase shifter 4 is also treated as a complex quantity.
（発明が解決しようとする問題点） 実際には合成回路３の出力中の残留干渉成分を抽出する
誤差信号発生回路の実現が重要な課題である。(Problems to be Solved by the Invention) Actually, it is an important issue to realize an error signal generation circuit for extracting the residual interference component in the output of the synthesis circuit 3.
本発明は第５図の原理的回路構成の制御部分を具体化し
たもので主信号中に残留する干渉成分をとり出す誤差信
号発生回路としては主信号用復調器自身を用い、また干
渉信号の直交位相検波器出力を用いて両出力信号の相関
検出をおこない可変振幅回路、可変位相回路の振幅およ
び位相の制御情報を得るもので、干渉補償回路の簡易な
回路構成を提供することを目的とする。The present invention embodies the control portion of the principle circuit configuration shown in FIG. 5. The main signal demodulator itself is used as the error signal generating circuit for extracting the interference component remaining in the main signal, and the interference signal The purpose of the present invention is to provide a simple circuit configuration of an interference compensation circuit, which obtains control information of the variable amplitude circuit and the amplitude and phase of the variable phase circuit by detecting the correlation between both output signals using the output of the quadrature phase detector. To do.
（問題点を解決するための手段） 本発明では、主信号中に含まれる残留干渉成分と干渉信
号との相歓をとり振幅と位相の制御情報を得る具体的手
段として、残留干渉成分および干渉信号を同相分および
直交分にそれぞれ分解するため受信した主信号を直交位
相同期検波する復調器を通し、その出力から同相および
直交成分の誤差情報を得る。また、干渉信号を主信号用
復調器で再生した搬送波を用いて直交位相検波をおこな
い同相および直交分の信号成分を得る。(Means for Solving the Problems) In the present invention, as a concrete means for obtaining the control information of the amplitude and the phase by deriving the interference between the residual interference component contained in the main signal and the interference signal, In order to decompose the signal into an in-phase component and a quadrature component, the received main signal is passed through a demodulator for quadrature phase synchronous detection, and in-phase and quadrature component error information is obtained from the output. In addition, quadrature phase detection is performed using a carrier wave reproduced from the interference signal by the main signal demodulator to obtain in-phase and quadrature signal components.
そして、お互い誤差信号と干渉信号の同相成分どうし、
また直交成分どうしの間で相関をとり積分器に通すこと
により可変減衰器の制御情報を得る。また、誤差信号と
干渉信号について同相分と直交分または直交分と同相分
との間で相関をとり積分器に通すことにより可変移相器
の制御情報を得る。従って、可変減衰器および可変移相
器を制御するため、誤差信号と干渉信号を同相分および
直交分に分解した後、相関検出する点とその制御回路を
するために必要な外部負荷回路としては、干渉信号を直
交位相検波する直交検波器と相関検出するための乗算器
および積分器だけでよい点を特徴とする。Then, the in-phase components of the error signal and the interference signal,
Moreover, the control information of the variable attenuator is obtained by obtaining the correlation between the orthogonal components and passing them through the integrator. Further, the control information of the variable phase shifter is obtained by obtaining the correlation between the in-phase component and the quadrature component or the quadrature component and the in-phase component for the error signal and the interference signal and passing the correlation through the integrator. Therefore, in order to control the variable attenuator and variable phase shifter, the error signal and the interference signal are decomposed into the in-phase component and the quadrature component, and then the correlation detection point and the external load circuit necessary for the control circuit are The feature is that only a multiplier and an integrator for detecting the correlation with the quadrature detector for detecting the quadrature phase of the interference signal are required.
（実施例） 本発明の具体的な一実施例を第１図に示す。主アンテナ
１から受信した主信号は帯域フィルタ２を通って後周波
数変換器３を通りIF信号に変換される。一方、主信号に
含まれる干渉信号成分だけを受信する補助アンテナ４か
ら受信した干渉信号は帯域フィルタ５を通り主信号側と
共通の局部発振器７により周波数変換６されIF信号に変
換される。この干渉信号は可変減衰器８および可変移相
器９を通り、分配器10により２分配され一方は制御部へ
もう一方は主信号と合成するための合成器11に入力され
る。ここで合成する以前の主信号は次式で表わされる。(Example) FIG. 1 shows a specific example of the present invention. The main signal received from the main antenna 1 passes through the bandpass filter 2 and the post-frequency converter 3 to be converted into an IF signal. On the other hand, the interference signal received from the auxiliary antenna 4 which receives only the interference signal component contained in the main signal passes through the bandpass filter 5 and is frequency-converted 6 by the local oscillator 7 common to the main signal side to be converted into an IF signal. This interference signal passes through the variable attenuator 8 and the variable phase shifter 9, is divided into two by the divider 10, and one is inputted to the control section and the other is inputted to the combiner 11 for combining with the main signal. The main signal before being combined here is expressed by the following equation.
ここでは主信号として16QAM信号を考える。従ってak,bk
＝｛±1,±３｝ｒ（ｔ）は系全体のインパルス応答であ
り、ナイキスト伝送系を仮定すればｒ（０）＝1,r（k
T）＝０ただしｋ≠０の整数、Ｔはクロック周期、ω１
は主信号の搬送波角周波数である。また干渉成分として
はCW波を考えており、ｒはその振幅、θは位相、ω２は
干渉成分の各周波数である。 Here, a 16QAM signal is considered as the main signal. Therefore, a k , b k
= {± 1, ± 3} r (t) is the impulse response of the entire system, and assuming a Nyquist transmission system, r (0) = 1, r (k
T) = 0, where k ≠ 0 is an integer, T is a clock period, and ω 1
Is the carrier angular frequency of the main signal. Further, the CW wave is considered as the interference component, r is its amplitude, θ is the phase, and ω 2 is each frequency of the interference component.
一方、分配器10の出力の信号は正常に制御されていれば
次式で表せる。On the other hand, the signal output from the distributor 10 can be expressed by the following equation if it is controlled normally.
ただし、Δr,Δθは十分小さい値と考えてよい。 However, Δr and Δθ may be considered to be sufficiently small values.
式（１）および（２）を加算した結果、主信号に含まれ
る残留干渉成分は第２図のベクトル図のようになる。残
留干渉を含む主信号を復調器100により同期検波12,13し
た後、高調波成分除去フィルタ14,15を通すことにより
同相および直交の復調信号が得られ次式となる。As a result of adding equations (1) and (2), the residual interference component contained in the main signal becomes as shown in the vector diagram of FIG. After the main signal including the residual interference is synchronously detected 12 and 13 by the demodulator 100, in-phase and quadrature demodulated signals are obtained by passing through the harmonic component removal filters 14 and 15, and the following equation is obtained.
一方、分配器10出力の干渉信号は直交位相検波器22,23
により主信号復調器で再生された搬送波で検波され好調
波除去フィルタ24,25通過後次式で与えられる同相分お
よび直交分を得る。 On the other hand, the interference signal output from the distributor 10 is quadrature phase detector 22,
Thus, the in-phase component and the quadrature component given by the following equation are obtained after being detected by the carrier regenerated by the main signal demodulator and passing through the harmonic elimination filters 24 and 25.
i2（ｔ）＝（ｒ＋Δｒ）・cos（Δωｔ＋θ′ ＋Δθ＋π）≒−ｒ・cos（Δωｔ＋θ′） （５） q2（ｔ）＝（ｒ＋Δｒ）・sin（Δωｔ＋θ′ ＋Δθ＋π）≒−ｒ・sin（Δωｔ＋θ′） （６） ここで、Δωはω１とω２の差を表わしている。i 2 (t) = (r + Δr) · cos (Δωt + θ ′ + Δθ + π) ≈−r · cos (Δωt + θ ′) (5) q 2 (t) = (r + Δr) · sin (Δωt + θ ′ + Δθ + π) ≈−r · sin ( Δωt + θ ′) (6) Here, Δω represents the difference between ω 1 and ω 2 .
θ′は初期位相差である。主信側の復調信号に対し、識
別回路16,17出力と識別回路入力信号との差をとる回路1
8,19を通すことにより残留干渉成分だけをとり出すこと
ができ、同相および直交の誤差信号は次式となる。θ ′ is the initial phase difference. Circuit 1 that takes the difference between the discrimination circuit 16 and 17 outputs and the discrimination circuit input signal for the demodulated signal on the master side
Only the residual interference component can be extracted by passing through 8 and 19, and the in-phase and quadrature error signals are given by the following equation.
Ei（ｔ）＝−Δｒ・cos（Δωｔ＋θ） ＋ｒ・Δθ・sin（Δωｔ＋θ） （７） Eq（ｔ）＝−Δｒ・sin（Δωｔ＋θ） −ｒ・Δθ・cos（Δωｔ＋θ） （８） ここで式（７），（８）で表わされる誤差成分と式
（５），（６）で表わされる干渉信号に対し相関検出を
おこなうため以下に示す演算をおこなう。すなわち、i2
（ｔ）とEi（ｔ）の積27またはq2（ｔ）とEq（ｔ）の積
28の結果を低減フィルタ34に通すことにより次式が得ら
れる。E i (t) = − Δr · cos (Δωt + θ) + r · Δθ · sin (Δωt + θ) (7) Eq (t) = − Δr · sin (Δωt + θ) −r · Δθ · cos (Δωt + θ) (8) where The following calculation is performed to detect the correlation between the error components represented by the equations (7) and (8) and the interference signals represented by the equations (5) and (6). I 2
The product of (t) and E i (t) 27 or the product of q 2 (t) and E q (t)
By passing the result of 28 through the reduction filter 34, the following equation is obtained.
i2（ｔ）×Ei（ｔ）＝q2（ｔ）×Eq（ｔ） ＝＋ｒ・Δｒ・cos（θ−θ′） （９） 第１図では制御ゲインをかせぐため27の積と28の積との
和をとって制御信号としている。また、q2（ｔ）とE
i（ｔ）の積29またはi2（ｔ）とEq（ｔ）の積30の逆符
号の結果を低減通過フィルタ33に通すことにより次式が
得られる。なお、低減通過フィルタ33,34は各々積分器
として作用する。i 2 (t) × E i (t) = q 2 (t) × E q (t) = + r · Δr · cos (θ−θ ′) (9) In Fig. 1, the product of 27 is used to gain control gain. And the product of 28 are used as the control signal. Also, q 2 (t) and E
By passing the result of the opposite sign of the product 29 of i (t) or the product 30 of i 2 (t) and E q (t) through the reduction pass filter 33, the following equation is obtained. The reduction pass filters 33 and 34 each function as an integrator.
q2（ｔ）×Ei（ｔ）＝−i2（ｔ）×Eq（ｔ） ＝−r2・Δθ・cos（θ−θ′） （10） 同様に、制御ゲインをかせぐため29の積と30の積との差
をとって制御信号としている。ここでθおよびθ′は初
期位相であり、その変動量はほとんど考えなくてよいた
めθ＝θ′となるよう初期調整しておけば式（９）より
Δｒ、また式（10）よりΔθとそれぞれ比例関係になり
式（９）の結果で可変減衰器の振幅を、また式（10）の
結果で可変移相器の位相を制御可能となる。第１図の10
1は制御回路を示している。従って、Δr,Δθは最適に
制御され主信号に含まれる残留干渉成分は最小となる。q 2 (t) × E i (t) = − i 2 (t) × E q (t) = −r 2 · Δθ · cos (θ−θ ′) (10) Similarly, to gain control gain 29 The difference between the product of and the product of 30 is taken as the control signal. Here, θ and θ ′ are initial phases, and the amount of fluctuation can be hardly considered. Therefore, if the initial adjustment is made so that θ = θ ′, Δr is obtained from equation (9) and Δθ is obtained from equation (10). As a result, the amplitude of the variable attenuator can be controlled by the result of the expression (9), and the phase of the variable phase shifter can be controlled by the result of the expression (10). Figure 10
Reference numeral 1 indicates a control circuit. Therefore, Δr and Δθ are optimally controlled, and the residual interference component contained in the main signal is minimized.
次に本発明の別の具体的実施例を第３図に示す。主信号
および干渉の源信号を主信号の復調器で再生した搬送波
で両信号は直交位相検波され、高調波除去フィルタを経
てそれぞれ同相および直交成分の復調出力を得るまでは
第１図の実施例と全く同じである。主信号の復調された
信号は識別器16,17で識別され、その出力と識別器入力
信号との差18,19をとりその結果を２値化することによ
り主信号に残留している干渉成分の極性を得ることがで
きる。具体的には第４図に示すように、16QAMの復調信
号である４値信号をA/D変換器に通すことにより上位２
ビットは識別データとなり、上位３ビット目が誤差信号
の極性、すなわち残留干渉成分の極性を示している。第
３図では、減算器18,19の出力はいわば上位３ビット以
降の情報を含んでいるが、この出力の極性が上位３ビッ
ト目に相当する。極性は２値だから、例えば正極性をパ
ルスの“1"、負極性を“0"に対応させれば18,19の出力
を排他的論理和29に入力できる。クロック周期Ｔごとに
サンプリングされた誤差信号の極性は次式で表わされ
る。Next, another concrete embodiment of the present invention is shown in FIG. The main signal and the interference source signal are quadrature-phase detected by the carrier wave regenerated by the main-signal demodulator, and the embodiment of FIG. 1 is executed until the demodulated outputs of the in-phase component and the quadrature component are obtained through the harmonic elimination filter. Is exactly the same as The demodulated signal of the main signal is discriminated by the discriminators 16 and 17, and the difference 18 and 19 between the output and the discriminator input signal is taken and the result is binarized, and thereby the interference component remaining in the main signal. The polarity of can be obtained. Specifically, as shown in FIG. 4, a four-valued signal, which is a 16QAM demodulated signal, is passed through an A / D converter, and the upper two
The bits serve as identification data, and the upper 3rd bit indicates the polarity of the error signal, that is, the polarity of the residual interference component. In FIG. 3, the outputs of the subtractors 18 and 19 include, so to speak, the information of the upper 3 bits, and the polarity of this output corresponds to the upper 3 bits. Since the polarity is binary, if the positive polarity is associated with the pulse "1" and the negative polarity is associated with "0", the outputs of 18 and 19 can be input to the exclusive OR 29. The polarity of the error signal sampled every clock cycle T is expressed by the following equation.
sgn｛Ei（mT）｝＝sgn｛−Δｒ・cos（Δω・mT＋θ） ＋ｒ・Δθ・sin（Δω・mT・θ）｝ （11） sgn｛Eq（mT）｝＝sgn｛−Δｒ・sin（Δω・mT＋θ） −ｒ・Δθ・cos（Δω・mT＋θ）｝ （12） 一方、干渉の源信号の直交検波された出力の極性をとる
回路27,28を通すことにより次式で与えられる。ただ
し、サンプリングタイミング主信号用復調器で再生され
たタイミング信号を用いる必要がある。sgn {E i (mT)} = sgn {-Δr ・ cos (Δω ・ mT + θ) + r ・ Δθ ・ sin (Δω ・ mT ・ θ)} (11) sgn {Eq (mT)} = sgn {-Δr ・ sin ([Delta] [omega] mT + [theta])-r * [Delta] [theta] cos ([Delta] [omega] mT + [theta])} (12) On the other hand, it is given by the following equation by passing the circuits 27 and 28 which take the polarities of the quadrature detected outputs of the interference source signals. However, it is necessary to use the timing signal reproduced by the demodulator for the sampling timing main signal.
sgn｛i2（mT）｝＝−sgn｛cos（Δω・mT＋θ′）｝（1
3） sgn｛q2（mT）｝＝−sgn｛sin（Δω・mT＋θ′）｝（1
4） 式（５），（６）に比べると、上記の右辺でｒが抜けて
いるが、上式は式の符号をとるだけであり、ｒは正だか
らこれを省略しても誤りではない。sgn {i 2 (mT)} =-sgn {cos (Δω ・ mT + θ ')} (1
3) sgn {q 2 (mT)} =-sgn {sin (Δω ・ mT + θ ')} (1
4) Compared to equations (5) and (6), r is missing on the right side above, but the above equation only takes the sign of the equation, and r is positive, so omission of this is not an error. .
ここでsgn｛Ei（mT）｝,sgn｛Eq（mT）｝,sgn｛i2（m
T）｝およびsgn｛q2（mT）｝に対して以下の演算をおこ
なう。すなわちsgn｛i2（mT）｝とsgn｛Ei（mT）｝のデ
ィジタル的乗算、すなわち排他的論理和29をとり低減通
過フィルタ38を通すことにより次式を得る。Where sgn {E i (mT)}, sgn {E q (mT)}, sgn {i 2 (m
T)} and sgn {q 2 (mT)} are calculated as follows. That is, the following equation is obtained by digitally multiplying sgn {i 2 (mT)} and sgn {E i (mT)}, that is, taking the exclusive OR 29 and passing it through the reduction pass filter 38.
sgn｛i2（mT）｝×sgn｛Ei（mT）｝ ＝−sgn｛−Δｒ・cos（θ−θ′） ＋ｒ・Δθ・sin（θ−θ′）｝ （15） 同様に sgn｛q2（mT）｝×sgn｛Eq（mT）｝ ＝−sgn｛−Δｒ・cos（θ−θ′） ＋ｒ・Δθ・sin（θ−θ′）｝ （16） 同様に sgn｛q2（mT）｝×sgn｛Ei（mT）｝ ＝−sgn｛Δｒ・sin（θ−θ′） ＋ｒ・Δθ・cos（θ−θ′）｝ （17） 同様に −sgn｛i2（mT）｝×sgn｛Eq（mT）｝ ＝−sgn｛Δｒ・sin（θ−θ′） ＋ｒ・Δθ・cos（θ−θ′）｝ （18） ここで前回同様θθ′とおくと sgn｛i2（mT）｝×sgn｛Ei（mT）｝ ＝sgn｛q2（mT）｝×sgn｛Eq（mT）｝ ＝＋sgn（Δｒ） （19） sgn｛q2（mT）｝×sgn｛Ei（mT）｝ ＝−sgn｛i2（mT）｝×sgn｛Eq（mT）｝ ＝−sgn（Δθ） （20） 従って、式（19）により可変減衰器８の振幅を、また式
（20）により可変位相器９の位相を制御可能である。10
1の制御回路では式（16）および式（17）の結果は同じ
であり、また式（17）および式（18）の結果は同じであ
るため制御ゲインを向上する目的で両信号を加算する例
を示している。sgn {i 2 (mT)} × sgn {E i (mT)} = -sgn {-Δr · cos (θ−θ ′) + r · Δθ · sin (θ−θ ′)} (15) Similarly, sgn { q 2 (mT)} × sgn {E q (mT)} = -sgn {-Δr · cos (θ−θ ′) + r · Δθ · sin (θ−θ ′)} (16) Similarly, sgn {q 2 (MT)} × sgn {E i (mT)} = − sgn {Δr · sin (θ−θ ′) + r · Δθ · cos (θ−θ ′)} (17) Similarly, −sgn {i 2 (mT )} × sgn {E q (mT)} = −sgn {Δr · sin (θ−θ ′) + r · Δθ · cos (θ−θ ′)} (18) Here, θθ ′ is the same as the previous time. i 2 (mT)} × sgn {E i (mT)} = sgn {q 2 (mT)} × sgn {E q (mT)} = + sgn (Δr) (19) sgn {q 2 (mT)} × sgn {E i (mT)} = − sgn {i 2 (mT)} × sgn {E q (mT)} = − sgn (Δθ) (20) Therefore, the amplitude of the variable attenuator 8 can be calculated by the equation (19). Also, the phase of the variable phase shifter 9 can be controlled by the equation (20). . Ten
In the control circuit of 1, the results of equations (16) and (17) are the same, and since the results of equations (17) and (18) are the same, both signals are added for the purpose of improving the control gain. An example is shown.
以上、第１図および第３図に示す回路ではIF帯の可変減
衰器、可変移相器により補償する場合の例を示したが、
RF帯の可変減衰器、可変移相器で補償する場合も同じで
ある。As described above, in the circuits shown in FIGS. 1 and 3, an example in which compensation is performed by a variable attenuator and a variable phase shifter in the IF band has been described.
The same applies when compensating with a variable attenuator or variable phase shifter in the RF band.
また、干渉信号としてCW波を例にとり説明したが、それ
以外の任意の変調信号に対しても同様、干渉成分と同一
の干渉源を別アンテナで受信しているため同じ回路構成
で干渉補償が可能である。Although the CW wave is used as an example of the interference signal in the description, the same circuit configuration can be used to compensate for interference with any other modulated signal because the same interference source as the interference component is received by another antenna. It is possible.
ここで、補助アンテナより受信した干渉信号を可変移相
器に通した後、一方を直交位相検波器へ、他方を可変減
衰器に通した後、主信号と合成すること、すなわち可変
減衰器を通す前で干渉信号を分岐する構成も考えられ
る。このようにすると、直交位相検波器に入る干渉信号
レベルは、可変減衰器の前段でとっているため、一般に
前述の場合に比べ高い。従って位相検波の際、感度を向
上することができる。可変減衰器前段での干渉信号の振
幅は式（２）の（ｒ＋Δｒ）≒ｒの代りに別の値ｒ′と
すれば、ｒ′,rは共に正の値であり、式（９），（10）
および式（19），（20）は同様に成り立つことは明らか
である。ゆえに、原理的にも振幅および位相を制御可能
である。Here, after passing the interference signal received from the auxiliary antenna through the variable phase shifter, one is passed through the quadrature phase detector and the other is passed through the variable attenuator and then combined with the main signal, that is, the variable attenuator is used. A configuration may be considered in which the interference signal is branched before passing through. In this way, the interference signal level entering the quadrature detector is taken before the variable attenuator, so it is generally higher than in the case described above. Therefore, the sensitivity can be improved during the phase detection. Assuming that the amplitude of the interference signal in the preceding stage of the variable attenuator is another value r ′ instead of (r + Δr) ≈r in the equation (2), both r ′ and r are positive values, and the equation (9), (Ten)
And it is clear that equations (19) and (20) hold in the same way. Therefore, the amplitude and phase can be controlled in principle.
（発明の効果） 以上説明したように、本補償回路では、主信号に混入し
た干渉信号を別のアンテナにより干渉の源信号を受信
し、主信号中の干渉成分と等振幅、逆位相で加算してい
るため干渉信号の変調方式によらず任意の信号に対し
て、十分な補償効果を得ることができ、また主信号中に
残留した干渉成分を抽出する誤差信号発生回路としては
主信号用復調器をそのまま用いる。従って、新たに付加
する回路としては干渉信号を直交位相検波する直交位相
検波器と、その出力と誤差信号発生回路出力との相関を
とるアナログ乗算器、またはディジタル乗算器（排他的
論理和回路）と積分用低域通過フィルタだけでよく、上
述の回路を用いる簡易な回路構成で可変減衰器および可
変移相器を制御する制御回路を構成可能であるという利
点を有する。(Effects of the Invention) As described above, in the present compensation circuit, the interference signal mixed in the main signal is received by another antenna as the source signal of the interference, and added with the interference component in the main signal in the same amplitude and opposite phase. Therefore, a sufficient compensation effect can be obtained for any signal regardless of the modulation method of the interference signal, and the error signal generation circuit for extracting the interference component remaining in the main signal is used for the main signal. Use the demodulator as is. Therefore, as a newly added circuit, a quadrature phase detector for quadrature phase detection of an interference signal and an analog multiplier or a digital multiplier (exclusive OR circuit) for correlating the output with the output of the error signal generating circuit It has the advantage that a control circuit for controlling the variable attenuator and the variable phase shifter can be configured with a simple circuit configuration using the above circuit, since only the low pass filter for integration and the above is required.
第１図は本発明の実施例を示す図、第２図は残留干渉信
号のベクトル図、第３図は本発明の別の実施例を示す
図、第４図は多値（４値）識別回路（誤差信号発生回
路）の入出力関係図、第５図は従来の干渉波補償回路で
ある。 符号の説明（第１図） １……主アンテナ、2,5……帯域フィルタ、 3,6……周波数変換器、４……補助アンテナ、 ７……受信局部発振器、８……可変減衰器、 ９……可変移相器、10……分配器、 11……合成器、12,13,22,23……検波器、 21,26……90゜移相器、20……再生搬送波、 14,15,24,25……低減フィルタ、 16,17……識別回路、18,19……減衰器、 27,28,29,30……乗算器、 31……加算器、32……減衰器、 33,34……積分器、100……復調器、 101……制御回路、 102,103……誤差信号発生回路。FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a vector diagram of a residual interference signal, FIG. 3 is a diagram showing another embodiment of the present invention, and FIG. 4 is a multi-value (four-value) discrimination. FIG. 5 shows a conventional interference wave compensating circuit, which is an input / output relationship diagram of a circuit (error signal generating circuit). Explanation of symbols (Fig. 1) 1 ... Main antenna, 2,5 ... Band filter, 3,6 ... Frequency converter, 4 ... Auxiliary antenna, 7 ... Receive local oscillator, 8 ... Variable attenuator , 9 ... Variable phase shifter, 10 ... Distributor, 11 ... Combiner, 12,13,22,23 ... Detector, 21,26 ... 90 ° phase shifter, 20 ... Regenerated carrier wave, 14,15,24,25 …… Reduction filter, 16,17 …… Identification circuit, 18,19 …… Attenuator, 27,28,29,30 …… Multiplier, 31 …… Adder, 32 …… Attenuator Integrator, 100 ... Demodulator, 101 ... Control circuit, 102, 103 ... Error signal generation circuit.
Claims (2)
信用の補助アンテナと、該補助アンテナ出力の振幅およ
び位相を可変するお互いに縦続に接続された可変位相回
路および可変振幅回路と、該可変位相回路及び該可変振
幅回路により位相および振幅を制御された干渉信号と該
主アンテナ出力とを合成する合成回路（11）と、該合成
回路の出力を入力信号として、再生した基準搬送波を用
いて同相成分および直交成分に分解する第１の直交位相
同期検波器（12,13）と、同相成分および直交成分の該
直交位相検波器の出力をそれぞれ入力信号とし合成回路
の出力に残留する干渉成分を検出する２つの誤差信号発
生回路（102,103）と、 前記干渉信号を同相成分および直交成分に分解するた
め、該干渉信号を入力信号とし前記直交位相同期検波器
（12,13）と共通の基準搬送波を用いて直交位相検波す
る第２の直交位相検波器（22,23）と、干渉信号の直交
位相検波器（22,23）の２つの出力信号と前記誤差信号
発生回路（102,103）の２つの出力の各々との相関をそ
れぞれ独立にとる少なくとも２個以上の乗算器（27,28,
29,30）とを有し、 前記直交位相検波器（22,23）の２つの出力と前記誤差
信号発生回路（102,103）の２つの出力のお互いに同相
成分どうしの相関、直交成分どうしの相関、または前記
各相関の和を積分した信号を前記可変振幅回路の制御信
号とし、 前記直交位相検波器の同相成分の出力と前記誤差信号発
生回路の直交成分の出力との相関、前記直交相検波器の
直交成分の出力と前記誤差信号発生回路の同相成分の出
力との相関、又は前記各相関の差を積分した信号を前記
可変位相回路の制御信号とすることを特徴とする干渉補
償回路。1. A main antenna for receiving a main signal, an auxiliary antenna for receiving an interference signal, and a variable phase circuit and a variable amplitude circuit which are connected in series to each other for varying the amplitude and phase of the output of the auxiliary antenna. A synthesis circuit (11) for synthesizing an interference signal whose phase and amplitude are controlled by the variable phase circuit and the variable amplitude circuit and the main antenna output, and a reproduced reference carrier wave using the output of the synthesis circuit as an input signal. The first quadrature-phase synchronous detector (12, 13) used for decomposing into in-phase component and quadrature component, and the outputs of the in-phase component and the quadrature component of the quadrature component are used as input signals and remain in the output of the combining circuit. Two error signal generation circuits (102, 103) for detecting an interference component, and for decomposing the interference signal into an in-phase component and a quadrature component, the interference signal is used as an input signal and the quadrature phase synchronous detector (1 The second quadrature detector (22,23) for quadrature detection using a common reference carrier with the two output signals of the interference signal quadrature detector (22,23) and the error At least two multipliers (27, 28, 27) that independently correlate with each of the two outputs of the signal generation circuit (102, 103)
29, 30), and the two outputs of the quadrature phase detector (22, 23) and the two outputs of the error signal generating circuit (102, 103) are mutually in-phase component correlation and quadrature component correlation. , Or a signal obtained by integrating the sum of the respective correlations as the control signal of the variable amplitude circuit, the correlation between the output of the in-phase component of the quadrature phase detector and the output of the quadrature component of the error signal generating circuit, the quadrature phase detection Of the output of the quadrature component of the converter and the output of the in-phase component of the error signal generation circuit, or a signal obtained by integrating the difference between the correlations is used as the control signal of the variable phase circuit.
信用の補助アンテナと、該補助アンテナ出力の振幅およ
び位相を可変するお互いに縦続に接続された可変位相回
路および可変振幅回路と、その出力を前記主アンテナの
出力と合成する合成回路（11）と、前記可変位相回路と
前記可変振幅回路との間に挿入され可変位相回路の出力
を分岐する２分配器と、前記合成回路の出力を入力信号
として、再生した基準搬送波を用いて同相成分および直
交成分に分解する第１の直交位相同期検波器（12,13）
と、同相成分および直交成分の該直交位相検波器の出力
をそれぞれ入力信号とし合成回路の出力に残留する干渉
成分を検出する２つの誤差信号発生回路（102,103）
と、 前記干渉信号を同相成分および直交成分に分解するた
め、前記２分配器の分岐出力信号を入力信号とし前記直
交位相同期検波器（12,13）と共通の基準搬送波を用い
て直交位相検波する第２の直交位相検波器（22,23）
と、直交位相検波（22,23）の出力信号と前記誤差信号
発生回路（102,103）の２つの出力との相関をそれぞれ
独立にとる少なくとも２個以上の乗算器（27,28,29,3
0）とを有し、 前記直交位相検波器（22,23）の２つの出力と前記誤差
信号発生回路（102,103）の２つの出力のお互いに同相
成分どうしの相関、直交成分どうしの相関、又は前記各
相関の和を積分した信号を前記可変振幅回路の制御信号
とし、 前記直交位相検波器の同相成分の出力と前記誤差信号発
生回路の直交成分の出力との相関、前記直交位相検波器
の直交成分の出力と前記誤差信号発生回路の同相成分の
出力との相関、又は前記各相関の差を積分した信号を前
記可変位相回路の制御信号とすることを特徴とする干渉
補償回路。2. A main antenna for receiving a main signal, an auxiliary antenna for receiving an interference signal, and a variable phase circuit and a variable amplitude circuit which are connected in series and which vary the amplitude and phase of the output of the auxiliary antenna. A combining circuit (11) that combines the output with the output of the main antenna, a two-way divider that is inserted between the variable phase circuit and the variable amplitude circuit, and branches the output of the variable phase circuit, and the combining circuit. First quadrature-phase synchronous detector (12,13) that decomposes into in-phase component and quadrature component using regenerated reference carrier wave with output as input signal
And two error signal generating circuits (102, 103) for detecting interference components remaining in the output of the synthesizing circuit using the outputs of the quadrature phase detector of the in-phase component and the quadrature component as input signals, respectively.
In order to decompose the interference signal into an in-phase component and a quadrature component, the quadrature phase detection is performed by using the branch output signal of the two-way divider as an input signal and using the reference carrier common to the quadrature phase synchronization detector (12, 13). Second quadrature detector (22,23)
And at least two or more multipliers (27, 28, 29, 3) that independently correlate the output signal of the quadrature detection (22, 23) and the two outputs of the error signal generating circuit (102, 103).
0) and the two outputs of the quadrature detector (22, 23) and the two outputs of the error signal generating circuit (102, 103) are mutually in-phase component correlated, quadrature component correlated, or A signal obtained by integrating the sum of the correlations is used as a control signal of the variable amplitude circuit, and the correlation between the output of the in-phase component of the quadrature phase detector and the output of the quadrature component of the error signal generation circuit, the quadrature phase detector An interference compensating circuit, wherein a correlation between an output of a quadrature component and an output of an in-phase component of the error signal generating circuit or a signal obtained by integrating a difference between the correlations is used as a control signal of the variable phase circuit.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60287881A JPH0761023B2 (en) | 1985-12-23 | 1985-12-23 | Interference compensation circuit |
| US06/921,093 US4736455A (en) | 1985-12-23 | 1986-10-21 | Interference cancellation system |
| CA000521944A CA1257658A (en) | 1985-12-23 | 1986-10-31 | Interference cancellation system |
| DE8686308589T DE3685645T2 (en) | 1985-12-23 | 1986-11-04 | SYSTEM FOR COMPENSATING A RADIO INTERFERENCE SIGNAL. |
| EP86308589A EP0228786B1 (en) | 1985-12-23 | 1986-11-04 | Radio signal interference cancellation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60287881A JPH0761023B2 (en) | 1985-12-23 | 1985-12-23 | Interference compensation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62147818A JPS62147818A (en) | 1987-07-01 |
| JPH0761023B2 true JPH0761023B2 (en) | 1995-06-28 |
Family
ID=17722935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60287881A Expired - Lifetime JPH0761023B2 (en) | 1985-12-23 | 1985-12-23 | Interference compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0761023B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0773224B2 (en) * | 1988-01-22 | 1995-08-02 | 日本電信電話株式会社 | Interference compensation circuit |
| JP2809897B2 (en) * | 1991-07-19 | 1998-10-15 | 松下電器産業株式会社 | Television signal receiving device and transmitting device |
| US6564038B1 (en) * | 2000-02-23 | 2003-05-13 | Lucent Technologies Inc. | Method and apparatus for suppressing interference using active shielding techniques |
| WO2011114726A1 (en) * | 2010-03-18 | 2011-09-22 | パナソニック株式会社 | Radio reception device for vehicle and noise cancellation method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57111132A (en) * | 1980-12-26 | 1982-07-10 | Nec Corp | Disturbing wave rejecting and receiving system |
| JPS58131852A (en) * | 1982-01-30 | 1983-08-05 | Nec Corp | Interference wave erasing device |
-
1985
- 1985-12-23 JP JP60287881A patent/JPH0761023B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62147818A (en) | 1987-07-01 |
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| EXPY | Cancellation because of completion of term |