GB2185648A - Electronic interface circuit - Google Patents

Abstract

It is a problem providing coupling between a device (3) that operates between one set of supply voltage levels (say, 0V and +5V) and another device (5) operating between another set of voltage levels, (say, -5V and 0V). In the circuit described (Figure 1) an interface (1) is provided by a source-follower transistor (7) and a series connected level-shift network (9), comprised for example of two resistors (R1, R2). A particular feature of this circuit (1) is that the transistor (7) is of the isolation well type - (e.g. n-channel, p-well CMOS FET), and the well and transistor substrate are connected in common to an appropriate rail (e.g. <V>DD @ 0V). When the transistor channel is non-conducting, current is drawn from the well so that source drain stress on the transistor (7) does not become excessive.

Description

SPECIFICATION Electronic Interface Circuit Technical Field The present invention concerns electronic interface circuits, in particular interface circuits for coupling electronic devices operating between different supply voltage levels.

There are applications, such as digital to analogue conversion (DAC), where it would be convenient to operate between differential supply rails e.g. +5 volts. Field-effect transistors produced by modern small geometry processes operate typically only up to 5 volts total supply. There is thus a need for an interface circuit that can provide level shift for logic circuitry operating between 0 and 5V and DAC circuitry operating between -5V and OV, such that no system transistor will operate on more than 5V source drain stress.

Also, as CMOS processes move to even smaller geometries and lower breakdown voltages, it will become desirable to interface chips with a 3 volt maximum supply to 5 volt devices.

Background Art In ECL combinational logic devices, for example, level shift arrangements have been devised to shift logic signal levels so that these signals can be applied to cascoded gates without causing transistor saturation. In a typical arrangement the logic signal is applied to the base of an emitterfollower bipolar transistor and the signal level shifted by means of a diode-resistor level-shift network. This level-shift arrangement, however, is connected between standard supply voltage rails and the transistor is not unduly stressed.

By analogy, an n-channel 5V CMOS sourcefollower field-effect transistor and resistor level-shift network can be devised to operate between OV and +5V voltage supply rails. Conventionally, the p-well isolating structure of this transistor would be connected to the more negative rail (OV) and the surrounding n substrate material would be connected to the more positive rail (+5V). In this arrangement the p-well/n- substrate diode interface is at all times reverse biassed. It is a problem, however, that such an arrangement would not operate satisfactorily when connected between the +5V and -5V voltage supply rails of a differential power supply.

Disclosure of the Invention The present invention is intended to provide an electronic interface circuit to enable the coupling of electronic devices operating between different supply voltage levels.

Accordingly there is provided an electronic interface circuit connected between first and second supply voltage rails to enable signal coupling to an electronic device operable between a third supply voltage rail, corresponding to an intermediate voltage, and the second supply voltage rail, this circuit comprising: a field-effect transistor, of the type including an isolating well adjacent to the source and drain thereof this well being disposed between these and the transistor substrate, the gate of this transistor to serve as input terminal; and, a level-shift network, a junction thereof to serve as output terminal; wherein, the transistor well and the adjacent transistor substrate are connected in common and to an appropriate one of the supply rails such that when current flow between the source and drain is inhibited, current flows from the well into the level-shift network.

The level-shift network aforementioned may comprise a resistor voltage divider. Alternatively, it may comprise a resistor and series connected current source.

The field-effect transistor aforementioned may be of CMOS, NMOS, Schottky MESFET or JFET types.

By way of particular example, and to provide coupling between a device operable between OV and +5V supply voltage rails and a device operable between -5V and OV supply voltage rails, this transistor may be of the n-channel, p-well 5V CMOS type, the p-well and substrate of which are connected to the OV supply voltage rail.

Brief Introduction of the Drawings In the drawings accompanying this specification: Figure lisa circuit diagram of an interface circuit, an embodiment of this invention;.

Figure 2 is a circuit diagram of an interface circuit, a variant of the circuit of Figure 1 above; Figure 3 is a circuit diagram of an interfaced inverter circuit; Figure 4 is a cross-section drawing of an integrated circuit implementation of the circuit of Figure 3 above; Figure 5 is a block circuit diagram to show digital to analogue converter input interfacing; and, Figure 6 is a block circuit diagram of an alternative device/interface arrangement for coupling 5V to 3V CMOS devices.

Description of Preferred Embodiments So that this invention may be better understood, embodiments will now be described with reference to the accompanying drawings. The description that follows is given by way of example, only.

In Figure 1 an interface circuit 1 is shown and is provided to afford coupling between a first electronic device 3 (operable between the first and third rails, Vcc and VDD respectively of a voltage supply (not shown)), and, a second electronic device 5 (operable between the third and second rails, VDD and Vss respectively, of the voltage supply). The interface circuit 1 is connected between the first and third voltage rails, Vcc and Vss respectively and is comprised of a field-effect transistor 7 and a series connected level-shift network 9. In the example illustrated, the transistor 7 is an n-channel, p-well CMOS transistor and the p-well and transistor substrate are connected to the third voltage rail VDD.

The p-well/source junction is represented by a diode 11 in this figure. The transistor drain is connected to the first voltage rail Vcc corresponding here to the most positive voltage, and the end of the level-shift network is connected to the second voltage rail Vss, corresponding here to the most negative voltage.

The gate I/P of the transistor 7 is connected to the output of the first electronic device 3. The level-shift network 9 shown comprises a pair of resistors Rt, R2. The output is taken from a junction O/P between these two resistors R1, R2 to the input terminal of the second electronic device 5. In the drawing, symbol A represents the input voltage applied to the gate of the transistor 7, symbol B represents the voltage at the source of the transistor 7 and symbol C represents the output voltage taken from the levelshift network 9.

In the derivations that follow, V55 GS is the n-channel gate-source voltage and VBE is the forward bias diode voltage of the p-well and n+ source junction of the transistor 7.

An optimum relationship between values for the resistances R1, R2 is derived below: Consider first, operation of the interface circuit 1 when the applied input signal is at logic high:- A=Vcc # B=Vcc-VGS and R2.

CHIGH=VSS+ (Vcc-VssVss) (R1 +R2) i.e.

VssR1 + R2Vcc - R2V55 CHIGH = (R1 +R2) It is requisite that the output voltage CHIGH shall not exceed the intermediate rail voltage VDD:- i.e.

CHIGH6VDD By way of simplification it is assumed that VDD is the 0V ground rail:- CHIGHO.

# R1#R2(VCC-VGS)/(-VSS) Constraint 1.

Consider now, operation of the interface circuit 1 when the applied input signal is at logic low (VDD=OV).

A=OV #B=0V-VBE and R2 CLoW=Vss+ (-VsE-Vss) (R1 +R2) i.e.

CLow=(RlVssR2VBEW(Rl +R2) The logic swing AC in the output signal C is thus given as: aC=CHIGH CLOW R2 =(Vcc-VGS+VBE) (R1 +R2) Thus the maximum swing corresponds to the minimum value of the resistor R1, and this within Constraint 1: (-VSS)(VCC-VGS+VBE) ACmax= (VCC-VGS-VSS) where RI(MIN)=R2(V,c-VGs)/(-Vss) The resistance values R1, R2 of the network resistors would be so chosen for maximum noise immunity.Where the above described interface 1 is followed by an inverter, the threshold voltage VTH would be chosen as follows: VTH=1(CHIGH+CLOW) R1VSS+R2(VCC-VGS-VBE) (R1 +R2) A variant of the interface circuit 1 is shown in Figure 2 where the level shift network comprises a resistor R1 and, a current source 13 in place of the second resistor R2.

With reference now to Figures 3 and 4, an interfaced inverter circuit 15 is shown. In this circuit the interface circuit 1 comprises a transistor T1 (7) as before and series connected resistors R1, R2. The drain of this transistor T, is connected to the first rail Vcc (+5V) and the end of the second resistor R2 is connected to the second rail V55 (-5V). The inverter circuit 15 comprises a pair of complimentary transistors a p-channel transistorT2 and an nchannel transistorT3. The gates of these two transistors Tr, T2 are connected to the output junction O/P of the interface circuit 1 and their drains are connected to a common output node 17.The sources of the two transistors T2, T3 are connected to the third supply rail VDD (OV) and to the second supply rail V55 (-5V), respectively.

In Figure 4 an n-type silicon substrate integrated circuit implementation of this circuit (Figure 3) is shown. The source and drain regions of transistors T, and T3 are of n+ doped material and are isolated from the n-/n+ substrate 19 each by a p-well structure 21,23. The nin+ substrate 19 and the p-well 21 of the first transistor T1 have a common connection to the third rail VDD (OV) of the power supply. The source of the first transistor T1,which is operated as a source follower, feeds a pair of resistors R1, R2 connected as in Figure 4to the second (negative) voltage rail Vss (-5V). The input to the following circuitry T2, T3 is fed from the junction O/P between these resistors R1, R2. These latter may be polysilicon as shown, or of n+ source/drain implants isolated in p-wells as for the transistor T1, T3. It is noted that the p-well 23 and source of the third transistor T3 are connected to the second rail Vss, here the most negative rail (-5V), as is conventional practice. It will be recalled that the adjacent substrate 19 is connected to the third rail Vss (OV).

The device functions as follows. When the input is in the high state, the transistor T1 is turned on and the upper end of the first resistor R1, is pulled up to 5V-VGS, where Vcs is the n-channel gate source voltage. The resistors R, and R2 act as a voltage divider and so the output voltage is pulled to: (1OV-Vas)Ra/(Ri+R2)5V When on the other hand, the input is in the low state, the source of the first transistor T1 falls to -VBE, the forward bias diode voltage of the p-well and n+ source junction 21 of the first transistor T1, and again this voltage is divided down.

Propertolerancing will ensure that the following gate T2/T3 turns on and off satisfactorily. The net effect is that the signal is level shifted without any transistor T1, T2 or T3 being overstressed.

In the foregoing description an n-channel, p-well device was considered. It is noted that the concept is likewise adaptable to p-channel, n-well devices.

A particular application is in digital/analogue conversion, where it is advantageous to operate the logic and current switching between OV and -5V to allow a negative output voltage compliance. This is illustrated in Figure 5. Each input l/P(1), . . I/P (N) to a digital to analogue converter 31, is connected to the output O/P of a corresponding interface circuit 1. For simplication, only one of these interface circuits has been illustrated.

Further applications of this invention are likely to arise for very small geometry processes where the circuit would be operable between, say, OV and 3V but where an interface is needed to accept OV to 5V conventional CMOS inputs. The input structure T1, R1, R2 (Figure 1) or equivalent current source alternatives (Figure 2) will provide an interface without need for process modification to avoid device overstress. Figure 6 shows just such an application where the interface circuit 1 provides coupling between a standard CMOS device 33 and a low voltage CMOS device 35.

Whilst the invention is most relevant to digital design, it could also handle analogue signal interfacing. However, in this context, it is noted that the dynamic range would be severely restricted.

Claims (7)

1. An electronic interface circuit connected between first and second supply voltage rails to enable signal coupling to an electronic device operable between a third supply voltage rail, corresponding to an intermediate voltage, and the second supply voltage rail, this circuit comprising: a field-effect transistor, of the type including an isolating well adjacent to the source and drain thereof, this well being disposed between these and the transistor substrate, the gate of this transistor to serve as input terminal; and, a level-shift network, a junction thereof to serve as output terminal, wherein, the transistor well and the adjacent transistor substrate are connected in common and to an appropriate one of the supply rails such that when current flow between the source and drain is impeded, current flows from the well into the level-shift network.

2. A circuit as claimed in claim 1 wherein the level-shift network comprises a resistor voltage divider.

3. A circuit as claimed in claim 1 wherein the level-shift network comprises a resistor and a current source.

4. A circuit as claimed in any one of the preceding claims wherein the first, second and third rails are rails for positive, negative and intermediate voltage, the transistor is an n-channel, p-well transistor and, the p-well and substrate are connected in common to the third voltage rail.

5. A circuit as claimed in claim 4 wherein the transistor is a MOSFET n-channel p-well transistor.

6. A circuit, as claimed in any one of the preceding claims, when used as interface to a digital to analogue converter.

7. A circuit as claimed in any one of the preceding claims 1 to 3, when used as interface between CMOS devices produced by different geometry CMOS processes.

7. A circuit, as claimed in any one of the preceding claims 1 to 5, when used as interface between CMOS devices produced by different geometry CMOS processes.

8. An electronic interface circuit constructed, adapted and arranged to operate, substantially as described hereinbefore, with reference to and as shown in the accompanying drawings.

9. A digital to analogue converter including a plurality of input interface circuits, each as claimed in claim 1 preceding.

Amendments to the claims have been filed, and have the following effect: Claim 7 above has been textually amended.