GB2173930A - Physical modelling device for use with computer-aided design - Google Patents

Abstract

A device for the modelling of a physical electrical component as part of an electrical logic simulation comprising: a logic simulation computer 11-19 coupled to a bus 22 for implementing an event driven algorithm; a first means 23 coupled to the bus for modelling the component when the component's state does not decay over time, and receiving input vectors from the computer to present to the component; a second means 24 for modelling the component when the component must be operated at a minimum rate in order to function properly and when the component is uninitializable, the means 24 including a memory for receiving and storing the input vectors from the computer and presenting them to the component in a continuous series; the first and second means comprising a plurality of channels, the channels including detecting means and driving means, the driving means including tristatable drivers; whereby the component can be utilized in a logic simulation without software modelling. <IMAGE>

Description

1 GB2173930A.1

SPECIFICATION

Physical modelling device for use with computer-aided design BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of computer aided design and more particularly to the im plementation of a physical part into a simulation algorithm.

2. Prior Art

In the design of electrical circuits, it is necessary to test the circuit prior to fabrica tion. In the past a circuit design would be implemented by---breadboarding- but such a method is uneconomical and impractical for today's circuits, which contain hundreds of thousands of components. One prior art method for simulating such circuits consists of computer aided design utilizing a simulation al gorithm. In such a system, the individual ele ments of a circuit are simulated by software and are subjected to truth table analysis.

Numerous computers and systems are cur rently available for logic simulation. Illustrative of those available is the digital computer used for implementing an event driven simulation al gorithm as taught in patent application No.

594,533 and assigned to the assignee of the present invention. In that system, three pro cessors consisting of an evaluation unit, a state unit and a queue unit are interconnected and run the algorithm to perform logic analysis 100 on a circuit design. Often circuits are designed which employ standard, pre-existing parts as a portion of the circuit. In such as case, it is unnecessary to test the internal logic of the part, but it is desired to test its output as part of the designed circuit. It would be possible to simulate the part through software, but not all manufacturers have made public the internal circits of parts fabricated by them. In that case, it is desired to have a method of including the physical part itself as part of the circuit simulation.

The prior art includes examples of the physical modelling of a part in a test system.

Illustrative are the following: In -Microprocessor Testing-Method or Madness- by Douglas H. Smith printed in Digest of Papers, 1976 Symposium on Semiconductor Memory Testing, it is noted that an actual device can be utilized in a test instead of a software algorithm. A second article, Testing Microprocessor Chips: A Large Scale Challenge- Electronic Packaging and Production, April 1975, pp. 35-42, teaches the use of physical devices to generate their own behavior in an -emulationsequence. The article notes that output states are detected as a result of input data during such emulations. The author recommends testing a physical device'as part of its in- tended overall system. Additionally, the April 1981 edition of the reference manual for a Sentry MASTR Modular Monitor (M3) Release 1.1 instructs programmers to us& a,function of the monitor to construct programs which will progressively build up a test pattern by applying test signals to a part, and incorporating the response of the part to determine subsequent test signals.

Disadvantages of prior systems are an inability to incorporate parts which must be operated rapidly to function properly, or parts which are uninitializable. The present invention provides solutions to those problems.

According to the present invention there is provided a device for the modelling of a physical electrical component as part of an electrical logic simulation comprising:

a logic simulation computer coupled to a first bus for implementing an event driven algorithm; a first means coupled to said first bus for modelling said component when said component's state does not decay over time, said first means receiving input vectors from said computer to present to said component; a second means for modelling said components when said component must be operated at a minimum rate in order to function properly and when said component is uninitializa- ble, said second means including a memory means for receiving and storing said input vectors from said computer and presenting said vectors to said component in a continuous series; said first and second means comprising a plurality of channels, said channels including a detecting means and a driving means, said driving means including a plurality of tristatable drivers; whereby said component can be utilized in a logic simulation without software modelling.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 includes a block diagram showing the overall architecture of the present invention and a block diagram of a prior art logic simulator used in conjunction with the present invention.

Figure 2 illustrates the method of generating vectors.

Figure 3 illustrates a table which shows the state of a part for various input and output values.

Figure 4 is an electrical schematic of a por- tion of the dynamic card channels.

Figure 5 is an electrical schematic illustrating the sensing detectors of a portion of the dynamic card channels.

Figure 6 is a flow diagram used to describe the operation of the loop mode.

Figure 7 is a flow diagram illustrating the operation of the dynamic card.

Figure 8 is a block diagram illustrating the static card.

Figure 9 is a block diagram illustrating the 2 GB2173930A 2 dynamic card.

Figure 10 is an electrical schematic illustrating an individual channel.

DETAILED DESCRIPTION OF THE INVENTION 70

A logic simulation computer with the im- provement of a physical modelling device for the simulation of circuits containing real parts is described. In the following description, numerous specific details are set forth such as specific number of lines, etc., in order to pro vide a thorough understanding of the present invention. It will be obvious, however to one skilled in the art that the present invention may be practiced without these specific de tails. In other instances, well-known circuits and structures have not been shown in detail in order not to unnecessarily obscure the pre sent invention.

Prior Art Logic Simulator

It will be helpful to an understanding of the present invention to first describe a prior art logic simulator. The present invention is used in conjunction with a simulator similar to this prior art simulator.

The prior art simulator is that which appears above the line 15 in Fig. 1 and is the subject of patent application 594,533. Three nearly identical processors, the queue unit 11, the state unit 12, and the evaluation unit 13 are interconnected through uni-directional buses as shown. All units are connected through a bus 14 (in the Preferred embodiment, an Intel Multi-bus is used) and are controlled by a 100 master computer 17 through a slave interface 16. The queue unit 11 stores the events which drive the algorithm used in this logic simulator, along with the delay times for the simulated gates and the like. The state unit 12 along with its memory contains the state at a particular time for each of the simulated ele ments. The evaluation unit 13 along with its memory 19 stores the behavioral character istics of the components in the systems being 110 simulated, such as the truth tables for the in dividual gates. The queue unit 11, the state unit 12 and the evaluation unit 13 operate simultaneously utilizing a simulation algorithm applied to a software modelled circuit. 115 Overview of the Apparatus of the Present Invention Referring again to Fig. 1, that portion of the drawing situated below line 15 illustrates a block diagram of the present invention. The physical modelling device 20 consists of a static card 23 and a dynamic card 24. The part 25 being simulated is connected to a daughter board 21 which in turn is connected to the device 20 and acted on by the static card 23 or dynamic card 24 as required. The device 20 connects by means of a bi-directional bus 22 to the memory bus 29 of when the state of the part 25 does not decay over time. When the part 25 needs to be operated at a high rate of speed to be effective, the dynamic card 24 is utilized.

Description of Input Vectors

The input vectors are the stimuli which are presented to the part being modelled. The vectors contain information which will drive the part in a certain manner and each pin of a part is presented a series of input vectors. This series of vectors defines the simulation run.

Whether operating in the dynamic or static mode, the function of the input vectors remains the same. Each input vector is generated as shown in Fig. 2. Each mark on the vector change line 28 represents a new vector. Each change in the clock 26 will require a new vector. As seen by the marks above line 28, the vectors generated by the clock are periodic. Whenever data changes, as shown on data line 27, a new vector is generated. The data vectors, represented by the marks on the underside of line 28, are not periodic and can be generated at the same time as, or in between clock pulses. Because of this method, the rate of vector generation will never be slower than the slowest clock pulse and will often be faster. Once generated, the vector is presented to the part being modelled and that part's response to the vector is recorded.

Description of Channels

The dynamic card and static card consist of a number of channels. The channels provide information to the part and there is one channel for each logically active pin. An individual channel is illustrated in Fig. 10. (The letter.. a- has been added to numbers of Fig. 4 and Fig. 5 is Fig. 10 to designate like elements). Each channel requires two bits, 45a and 46a with bit 46a containing the value (low or high) at which the part is to be driven and bit 45a determining if the pin is to be in tri-state or not. After passing through the tristatable driver 43a the information passes through a resistor 42a. This resistor performs two functions. First, it permits detection of conflicting drive when the part is both driving and being driven simultaneously. Second, it prevents damage to the driver and to the part when both are driving. The information is then pre- sented to the pin on line 41a, interconnected to line 41a is tug voltage 49a. This connection is crucial to detection of the tristate mode. A voltage between the low voltage threshold and the high voltage threshold re- sults when the part is not driving and the driver is tristated.

Input/Output Map Each pin has two bit positions, 0 and L, in evaluation unit 13. The static card 23 is used 130the output sense field. The L bit is 1 if the

3 GB2173930A 3 voltage detected is higher than the low detection threshold. The 0 bit is 1 if the voltage detected is higher than the high detection threshold. A channel map 30 is illustrated in Fig. 3. As shown, if the 0 and the L bit agree at a low value as in row 31 or a high value as is row 33 there is a valid signal of the indicated value of the pin connected to that channel. If the output values disagree as at row 32, and the input channel for that pin is tristated as at columns 35 and 36, that pin is in tristate. The situation presented at row 34 is an impossibility since the pin could not read higher than the highest detection voltage while being lower than the lowest detection voltage. Such a situation indicates a malfunction, probably in the detector. If the input for a channel is being driven and both outputs do not agree, then the part is disagreeing with the input drive. This channel map 30 is identical for the dynamic card and the static card.

Description of the Static Card As shown in Fig. 8, the static card communicates with data bus 22 through the backplane bus converson 81 and bus inter-face 82. The backplane bus conversion enables more than one static card to be employed in a simulation as well as allowing dynamic cards to be used, with information to the additional cards travelling on backplane bus 89. The bus interface is coupled to a control state machine 83 through multiple signal line 131, and by multiple signal line 80 to the channel drive unit 84 and detector unit 85. The control state machine 83 controls read and write cycles for the card and is connected through multiple signal line 132 to the channel drive unit 84 and detector unit 85. The channel drive unit 84 stores and then presents the drive level for each channel on the static card. (One em bodiment of the static card contains 156 channels) The channel drive unit presents the drive levels to the daughter card 87 holding the parts through multiple signal line 88. The 110 channel drive unit is shown in detail in Fig. 4.

The detector unit (shown in detail in Fig. 5) receives the output from the part in the daughter board 87 through multiple signal line 88 and sends the information on line 80 to 115 the bus interface and eventually to the evalua tion unit. The reference block 86 is coupled to the channel unit 84 and detection unit 85 through line 133 and provides the high and low detection voltages along with the power 120 and tug voltage.

Operation of the Dynamic Card There is a class of components which do not function effectively unless operated at a minimum rate of speed. Additionally, there are parts with the disadvantage of being uninitializable, rendering their output nonrepeatable. The static card alone is insufficient as a method for modelling,. ---parts as part of a logic simulation. The design features of the dynamic card, on the other hand, permit these parts to be utilized in simulation runs.

For parts which must be run at a high rate of speed, but whose states can be initialized, the dynamic card operates in the manner shown in Fig. 7. As with the static card, input vectors are read one at a time from the evaluation unit, as shown in step 74.

The first vector is read and then is stored by the dynamic card as shown in step 75. At step 76, all stored vectors are presented to the part. At this point, however, only the first vector has been stored by the dynamic card.

After the first vector has been presented to the part, the output of the part is sensed in step 77. During step 78, the dynamic card checks its control register to see if this is the final vector to be presented to the part. In this case, the answer is no and the card returns to step 74, reading the second vector from the evaluation unit. After adding that vector to memory, the dynamic card at step 76 presents not only the second vector but the first and second vector to the part. The part's output after the second vector has been presented is sensed at step 77. This process repeats itself for all vectors 1 through n. When the nth vector is read from the evalua- tion unit and added to the previously read vectors, the dynamic card then presents all vectors 1 through n to the part, senses the output of the part after the nth vector at step 77 and because its control register now indi- cates the nth vector is the final vector, ends the simulation, step 79. In this manner, parts whose states decay over time can be utilized in a logic simulation. By reading all the vectors from the first vector to the vector being pre- sented to the part at that particular time, the state of the part does not decay between vectors.

The dynamic card carries a vX2Xn ram for input vectors where n is the number of logically active pins which can be driven by the card and v is the number of vectors supported by the card. The entire series of vectors is mapped in the evaluation unit address space, and can be read or written in arbitrary order. Like the static card, the dynamic card has one channel for each logically active pin.

A 24 bit word location on the dynamic card, known as the control register, is utilized as a write only location which chooses among several alternate operating modes available to a dynamic card, such as collective go, user strobe and loop mode.

Eac time the collective go word is written to, vectors are presented starting with the current starting address and ending at the vector marked as the end vector for that particular readthrough. Because the collective go word is found at a standard location for all dynamic cards, several cards may be synchro- nized to drive devices requiring more channel 4 GB2173930A 4 resources than are present on one card. The collective go mode is incompatible with the loop mode, which will be described further below.

When the user strobe bit of the control 70 register is active, vector readthrough and out put sensing are under user control. During vector readthrough, each new vector will not be released to the part until the receipt of an external ready signal. Similarly, the output will not be sensed until a ready signal is received. This mode is utilized when interfacing with external physical devices with long response times.

When the loop mode is activated, the input vector ram cycles continuously from beginning to a point defined by an inner loop end bit. Simulation vectors begin at the end of the inner loop and continue to the last vector. The output is sensed, and the part again goes back to the inner loop. This mode is useful for preserving the state of devices which are unintializable.

Description of Loop Mode

The loop mode is further explained by referring to Fig. 6. Loop mode consists of an inner loop 61 and an outer loop 63. The inner loop 61 is a set of vectors written prior to the simulation of the vectors being read. The inner 95 loop 61 is created by the user for the particular part being modelled. The part is cycled: continuously in the inner loop 61 until the simulation vectors are presented. The inner loop 61 is such that the state of the part when the simulation run begins is always the same. When the signal to run the simulation vectors is given, the part exits at the end of the inner loop, and all vectors in the outer loop 63 are then presented to the part. The 105 outer loop consists of the simulation vectors 64 and padding vectors 66. Included in the 24 bit words which control the last channels of the dynamic card are three bits, 0, 1 and S, which control the operation of the loop mode. 110 The 1 bit defines the vector which represents the inner loop end bit. In loop mode, vectors are continuously presented to the part, starting at the beginning location and ending with the inner loop end bit location. The 0 bit de- 115 fines the outer loop end bit. After reading the vector containing the outer loop end bit. the card returns to the inner loop. The S bit is the strobe bit, and the output of the part being modelled is sensed after the vector in which the S bit is one. The vectors up to and including the one containing the 1 bit will not change during loop mode. but the S bit will be moved to one higher vector after each simulation run.

In order for the loop mode to be effective, the 125 outer loop 63 must return the part at the inner loop initialization state 62 each time.

Since the state of the part at vector n, which is the final vector of the simulation, may not be identical to that state, padding 66, a series130 of vectors not part of the simulation run is utilized to return the part to the proper state. The padding 66 is determined by the user prior to the simulation run.

In general several distinct padding sequences 66 may be needed. The evaluation unit chooses which padding sequence is required to restore the initial state, based on information from: the simulation. The padding required is written immediately after the vector with the S-bit, before the dynamic card is instructed to leave the inner loop.

Description of Dynamic Card

Figs. ga and 9b illustrate a block diagram of the dynamic card. Address and data information enter the dynamic card on the backplane bus, shown separated as address bus 103 and data bus 104. The bus interface 91 also contains address latches. Input vector's travel data bus 106 to the vector RAM 94 of Fig. 9b. As each new vector is rec eived by the dynamic card it is added to those vectors already stored in the vector RAM 94. The vector RAM 94 stores the vectors received from the evaluation unit and can be accessed by address. When a go command is received, all vectors stored in the RAM are presented to the channel drive 95 and thence to the part in a continuous stream. In loop mode, the vectors defining the inner loop are continuously presented to the channel drive 95. Control data travels along bus 105 to.the control state machine 93. The control state machine, like its static card counterpart, controls read and write cycles under user control and processes other control information. Included in this information are the state of the S bit 7 1, the 1 bit 72 and the 0 bit 73. The control data travels on the card control bus 109 to the vector RAM 94. As shown, the states of the S, 1 and 0 bits are added to the vector information contained in the vector RAM. 94. For each vector two bits of information travel to the channel drive unit 95 (shown in detail in Fig. 4), tristate information on line 111 and value data on line 112. The channel drive unit presents vectors to the modelled part contained in the daughter card 96. The state of each pin travels line 113 to the detector unit 102 (shown in detail in Fig. 5). The channel drive 95 and detector unit perform the identical functions in both the static and dynamic cards. For the vector in which the S bit is 1, the output of the device is recorded and sent back to the bus interface on data bus 106. As with the static card, power and reference voltages are supplied by reference block 97. Information on the beginning address register is contained in beginning address register block 98. This information travels on line 119 to the vector ram 94 so that different vectors can be chosen as the beginning vector of a simulation run. In this manner, when a physical part is repeated several times in a circuit, GB2173930A 5 a single part can be used for the modelling in each of the locations. When the part in the first location is being modelled, the vector run will begin at vector 0, when the part appears at another point in the circuit, the beginning address register will designated some other vector as the first vector in the run. Obvi ously, when operating in this manner, the total number of vectors that can be run for that particular part is reduced.

The board address block 92, is coupled to various units. This block compares the ad dress of bus cycles to addresses on the card and generates select signals when the differ ent resources of the card are addressed. 80 Channel Drive Unit The channel drive unit is shown in Fig. 4. The input vector enters on the data bus 40 of Fig. 4. Two bits are required for each channel, and the two which exit flip-flop 44 on lines 45 and 46 will be traced through Figs. 4 and 5. The bit on line 45 indicates whether the pin driver on this channel is to be put in tristate or not, while bit 46 indicates whether the part is to be driven high or low. After passing through the tristatable driver 43, the information travels on line 47 through a resistor 42. The channel 94 emerging from resistor 42 is interconnected with resistor 48 and tug voltage 49. Finally, through line 41, the channel 94 is connected to a pin and to the sensing unit, which is shown in Fig. 5.

Detector Unit The sensing unit, illustrated in Fig. 5, detects the output of the pin which is connected to channel 94. The output of the pin travels on line 41 to part 53. As shown, the output of channel 94 enters the quad differential line receiver 53 at point B- and D-. A low reference voltage 51 enters at D+ and a high reference voltage 52 at B+. line 58, emerging from the part 53 represents the L bit and line 57 the 0 bit. The output passes through flip- flop 54 and onto data bus 59 where it returns to the evaluation unit.

As described thus far, the channels of the static card and the dynamic card are identical, except the static card lacks flipfiop 54. However, as shown in Fig. 4, the dynamic card also receives information concerning the S bit on line 7 1, the 1 bit on line 72, and the 0 bit on line 73. If the value of the S bit is 1, that particular vector is the final one in that run, and the value of the pins is to be sensed at the end of the vector. If the 1 bit has a value of 1, that vector represents the final vector in the inner loop. If the 0 bit has a value of 1, that vector represents the end of the outer loop. As seen in Fig. 5, the S, 1 and 0 bits travel on lines 71, 72 and 73 respectively through the flip-flop 54 and onto the data bus 59 which leads to the evaluation unit.

Thus, a device has been described which allows physical components to be included as part of a design simulation. The unique structure of the channels along with the loop mode permit modelling of a wide range of parts in a highly efficient manner.

The present invention has been divided out of our copending U.K. patent application No. 8520915 in which three is described and claimed a device for the modelling of a physi- cal electrical component in an electrical logic simulation comprising:

a connecting means for electrically coupling said component to a logic simulation computer; a plurality of channels coupled to said computer and said components for presenting data vectors to said components, said vectors comprising information to stimulate said component; said channels including a driving 85. means for stimulating said component, and a detecting means for determining resulting output of said component.

a memory means for storing said data vectors coupled to said channels and to said con- necting means; a looping means coupled to said channels for continuous cycling of said vectors through said component; whereby said components can be utilized as part of a logic simulation without the need for software modelling.

Claims (5)

1. CLAIMS 1. A device for the modelling of a physical electrical component as

   part of an electrical logic simulation comprising:

   a logic simulation computer coupled to a first bus for implementing an event driven algorithm; a first means coupled to said first bus for modelling said component when said component's state does not decay over time, said first means receiving input vectors from said computer to present to said component; a second means for modelling said components when said component must be operated at a minimum rate in order to function properly and when said component is uninitializable, said second means including a memory means for receiving and storing said input vectors from said compyter and presenting said vectors to said component in a continuous series; said first and second means comprising a plurality of channels, said channels including a detecting means-and a driving means, said driving means including a plurality of tristatable drivers; whereby said component can be utilized in a logic simulation without software modelling.
2. 2. The device as defined by Claim 1 wherein said first means includes a plurality of channels for driving said components, said channels holding two bits of information, there being one channel for each logically active pin 6 GB2173930A 6 of said component, said channels including a detector unit coupled with reference voltages such that said detector can identify the output of said component as high, low or tri-state, said first means including a bus interface for communicating with said computer.
3. 3. The device as defined by Claim 1 wherein said second means includes a random access memory for storing said vectors from said computer, a plurality of channels for driving said component, said plurality of channels presenting all said vectors stored in said memory to said component in a continuous stream, said channels including a detector for determining the state of said components as high, low or tri-state, said second means including a bus interface for communicating with said computer, said second means including a looping means for continuous cycling of said vectors through said component.
4. 4. The device as defined by Claim 3 wherein said second means has a fixed command location, said location allowing synchronism of a plurality of said second means, whereby parts requiring the use of said channels from more than one of said second means may be modelled.
5. 5. The device as defined in Claim 3 wherein said looping means is controlled by bit commands from a bit address in said memory, said bit address coupled to said channels for continuous cycling of said vectors through said component; whereby a component which is uninitializable may be maintained at a repeatable state and a component which must be operated at a minimum speed may be utilised.

   Printed in the United Kingdom for Her Majesty's Stationery Office, Dd 8818935, 1986, 4235. Published at The Patent Office, 25 Southampton Buildings. London, WC2A 1 AV, from which copies may be obtained.