GB2171271A - Generation of waveforms - Google Patents

Abstract

A waveform generator stores a plurality of sequences of digital words each word of which defines a bit pattern the bits of which represent the level of each of the waveforms and a run length defining the number of counts during which the bit pattern remains unchanged. Each word is read out and signal levels are maintained in accordance with the bit pattern while a counter increments to zero, having been loaded with the number defining the run length. The invention facilitates the storage of a multiplicity of sets of optimised waveforms suitable for controlling an induction motor and facilitates the on-line computation of those optimised waveforms. <IMAGE>

Description

SPECIFICATION Method and apparatus for the generation of waveforms The present invention relates to the generation of waveforms and in particular to the generation of a set of cyclic switched waveforms. The invention is intended, though not exclusively so, for use in the precision speed control of polyphase induction motors.

It is known to code a wave form which is essentially switched between two values by means of the run length between successive transitions.

However, the present invention in one aspect is concerned with the greater problem of generating a set of switched waveforms and coding them in an efficient manner.

One problem to which the present invention relates concerns the speed control of induction motors driven by switched waveforms, generated for example by direct current to alternating current inverters. Precise speed control of induction motors in this manner requires the generation of waveforms which are controllable in amplitude and frequency. A further requirement for satisfactory operation over the entire speed range is that the waveforms should posses a minimum of certain harmonics. For exam ple, satisfactory speed control of a three-phase induction machine may be achieved provided that the wave forms contain no significant harmonics other than the triplen harmonics (namely the third, ninth, fifteenth harmonics etc.). For a three-phase induction motor the effects of the triplen harmonics are automatically eliminated by virtue of the three phase system.It is therefore necessary only to ensure the minimisation of other harmonics.

Any switched waveforms with odd quarter-wave symmetry may be represented mathematically with sets of equations as described in Patel and Hoft "Generalized Techniques of Harmonic Elimination and Voltage Control in Thyristor Inverters" IEEE Transactions - Industry and Applications - May/June 1971. These equations relate harmonics to particular switching angles. By equating any harmonic to zero it is possible to obtain a set of non-linear transcen dental equations which may be solved by numerical methods to produce a set of switching angles which may then be used to produce switched wave forms optimised with respect to harmonic content. It is possible to eliminate m harmonics with m switching angles in a waveform possessing odd quarter-wave symmetry.The requirement in induction motor control for variable amplitude waveforms may also ,lbe met using similar techniques. The amplitude of the fundamental component may be controlled simultaneously by introducing another degree of freedom. This is achieved by the use of (m+ 1 ) switching angles to eliminate m harmonics with fundamental amplitude control.

The optimisation problem may be solved off-line by the use of numerical methods for solving sets of non-linear equations. However, it should be noted that current technology does not permit the use of on-line controllers based on such algorithms for the production of waveforms of frequencies suitable for the operation of induction motors. In one aspect the invention bypasses this difficulty by facilitating the storage of optimised switching waveforms in electronic memory. It thus facilitates the use of modern low cost methods in information storage and signal processing to provide waveforms optimised with respect to harmonic content and at the same time usually controllable in frequency and amplitude.It may further facilitate the use of on-line computers as speed controllers for induction motors by providing, in a preferred embodiment, an interface between the computer itself and the necessary DC to AC power inverter.

According to one aspect of the invention, a method of encoding a set of waveforms wherein the waveforms can be represented at each of a multiplicity of discrete phase positions within a repeating cycle by a multi-bit digital pattern coding the signal values of each of the waveforms, comprises forming a sequence of digital words each of which comprises a portion constituting or defining a respective multibit digital pattern and a run length portion defining the number of consecutive phase positions during which the respective pattern remains unchanged.

Preferably each bit in the said pattern represents the binary state of a respective waveform, each waveform being regarded as a two level signal.

The invention also provides a method of generating a set of cyclic switched waveforms each constrained to be in one or other of two states at each of a multiplicity of discrete phase positions, the method comprising reading out from a store each of a sequence of digital words in turn, each word having a part defining a pattern of states of the individual waveforms at at least one phase position and another part defining a number of phase positions during which the said pattern persists, and maintain- ing separate signal levels in accordance with said pattern while counting the number of phase positions. Preferably, for each word in turn, a counter is loaded in accordance with the number of phase positions and is incremented to a datum. The rate of incrementing may be selectable in order to achieve conveniently control of frequency.

In another aspect the invention provides apparatus for generating a set of waveforms, comprising means for storing a sequence of digital words, means for reading out each word in the sequence, means responsive to the word read out to maintain a plurality of signal levels for a number of clock intervals defined by said word, and means responsive to the elapse of said number of clock intervals to enable the read-out of the next word in the sequence. In practice the sequence may be recycled and the means for storing, which may comprise a read-only memory, may readily be arranged to store a multiplicity of different sequences each of which is controllably selectable. The clock signal may be of variable frequency.

The present invention is now described in more detail by way of example, with reference to the accompanying drawings, in which: Figure 1 illustrates three phase shifted switched waveforms possessing odd quater-wave symmetry; Figure 2 schematically indicates an embodiment of the apparatus according to the invention; and Figure 3 illustrates a timing diagram.

Awaveform generator in the embodiment shown in Figure 2 comprises three main elements, namely a read-only memory 1, a frequency generator, for example a voltage controlled oscillator 2, and two counters 3 and 4the counter 3a and 3b and the counter 4 being constituted by three "pattern duration" counters 4a, 4b and 4c. Figure 2 illustrates a specific embodiment showing the type numbers of the integrated circuits employed and the specific interconnection; however, this embodiment is shown only by way of example and many other arrangements are possible. The manner of operation of the embodiment shown in Figure 2 will be understood by a consideration of Figure 1 and the following description.

Each waveform in Figure 1 may be represented as an array of ones and zeros for ease of manipulation.

The number of elements in each array will depend upon the resolution required but will also be limited by the information capacity of the memory used.

Considering each waveform as an array of ones and zeros according to the level of the waveform at each of a multiplicity of discrete spaced apart phase positions, the topmost waveform has a transition between binary zero and binary one atthe phase position zero and a reverse transition to zero at or before the phase position 23, another transition form 0 to 1 at phase position 31 and so on. This waveform may be coded in terms of the run length between successive transitions. That is to say, if each phase position is denoted by an array subscript identifier n, then where A represents the signal level, a FOR NEXT software algorithm may be used for example for nO to 22, A(n) equals 1; next n; for n=23to 30, A (n) = 0; next n and so on.This process may be repeated for each of the waveforms in Figure 1, giving rise to three arrays, A, B and C each represent- ing one of the three phases. Inspection of Figure 1 reveals that for runs of certain array subscript identifiers each array has the same value. For example between array subscript identifiers (which may be regarded as counts or phase positions) 7 and 17, the arrays A, B and C representing each phase have values (1,1,1). in the next set of five counts the array values are (1,1,0). This allows the three waveforms to be encoded as a single array, each waveform being represented by a bit of different significance in a digital binary word.This in turn permits the coding of the set of waveforms in terms of for-next algorithms in which each word has a part, constituted by a multiplicity of digits in accordance with a particular bit pattern (1,1,1) or (1,1,0) as the case may be and another part representing the number of counts or phase positions during which that particular bit pattern persists. Thus an entire set of switched waveforms may be represented by a single array of digital words and, if desired, the array may be constructed using a computer once the switching angles for one waveform of a particular fundamental amplitude have been determined. It may be seen that in the particular example given, the pattern (1,1,0) remains valid for seven counts whereas the pattern (1,1,1) remains valid for eleven counts and so on.Owing to the cyclic nature of the wave forms there will be a particular number of bit patterns or blocks that may occur. It is preferable to increase this number to an integral power of two in order to simplify the hardware. This may easily be achieved by splitting up the runs or blocks wherein each pattern remains the same. For example the pattern (1,1,1) mentioned above is valid for eleven counts. This may be split into two runs, of six counts and five counts respectively. Thus the array of digital words fully describes the three phase shifted waveforms in terms of the number of counts for which a particular bit pattern persists.

The array may be stored in memory in the following manner. Each memory location in a readonly memory may be eight data bits wide. A number of counts forwhich each pattern remains valid is stored as a binary number in the five most significant data bits. The actual bit pattern is stored in the remaining three bits. In one example the number of bit patterns or blocks described in the waveform may be constrained to equal sixtyfour. Accordingly the encoded waveforms may be stored in sixtyfour consecutive memory locations. A different array may be constructed for each fundamental amplitude and then each set of three phase waveforms may be stored in another sixtyfour consecutive locations and so on.

With reference to Figure 2 and 3, the "pattern duration" counters count down to zero, at which point they are loaded with a currently addressed top five data bits stored in the read-only memory. The data on the remaining three lines of the same location corresponding to each respective phase of the optimised waveforms is latched out (on lines 01, 02, 03) and the block address counter is incremented. This counter then addresses the next location in the block of sixtyfour locations. When the pattern duration counters reach zero the new count duration is loaded and the new output pattern (which may be the same as or different from the previous bit pattern) is latched out then the block address counter is incremented again and so on.

The use of synchronous binary counters allows the generation of cyclic waveforms in a simple manner if the number of blocks is constrained to be a power of two, which allows the block address counter to overflow and start counting again.

A different set of waveforms may be selected simply by using the top address lines of the readonly memory to select different runs of sixty four consecutive memory locations. In this manner eightbit amplitude resolution may be achieved using a sixteen k-byte read-only memory in the illustrated example.

The speed at which each run of sixtyfour bytes is read through determines the frequency of the output waveforms. The speed is selected by means of the oscillator 2.

It is desirable to encode each set of waveforms in the same number of counts to ensure that the output waveform frequency remains the same regardless of amplitude for a given setting of the voltage controlled oscillator.

The invention is accordingly suitable for the wide range speed control of inverter fed polyphase induction motors. In addition the waveform generator may be used in either variable voltage and frequency or variable voltage position control of induction motors. Furthermore, the differing arrays need not be stored as a linearly ascending sequence in read-only memory. It is therefore possible to relate the amplitudes of the fundamental waveforms to a controlling binary signal in a non-linear manner. In this way the non-linear static torque/control voltage characteristic of the induction motor may be linearised by programming the read-only memory with a suitable non-linear compensating fundamental amplitude sequence. This would leave any controlling element free from time consuming linearisation routines (whether by means of look-up table or algorithm) and allow the position control of high frequency induction motors, with optimised waveforms, in real time.

Claims (9)

1. A method of encoding a set of switched waveforms wherein the waveforms can be represented at each of a multiplicity of discrete phase positions by a multi-bit digital pattern coding the signal values of each of the waveforms, comprising forming a sequence of digital words each of which comprises a portion constituting or defining a respective multi-bit digital pattern and a run length portion defining which the respective pattern remains unchanged.

2. A method according to claim 1 in which each bit in the pattern represents the binary state of a respective waveform, each waveform being regarded as a two level signal.

3. A method of generating a set of cyclic switching waveforms each constrained to be essentially in one or other of two states at each of a multiplicity of discrete phase positions, comprising reading out from a store each of a multiplicity of discrete phase postions, comprising reading out from a store each of a sequence of digital words in turn, each word having a part defining a pattern of states of the individual waveforms at at least one phase position and another part defining a number of phase positions during which the said pattern persists, and maintaining separate signal levels in accordance with said pattern while counting the said number of phase positions.

4. A method according to claim 3 in which for each word in turn a counter is loaded in accordance with the number of phase positions and is incremented to a datum.

5. A method according to claim 4 in which the rate of incrementing is selectable.

6. Apparatus for generating a set of waveforms, comprising means for storing a sequence of digital words, means for reading out each word in sequence, means responsive to the word read out to maintain a plurality of signal levels for one or more clock intervals defined by said word and means responsive to the elapse of the number of clock intervals to enable the read out of the next word in the sequence.

7. Apparatus according to claim 6 in which the sequence is recycled.

8. Apparatus according to claim 6 or claim 7 in which the means for storing is arranged to store a multiplicity of different sequences, each of which is controilably selectable.

9. Apparatus according to any of claims 6 to 8 in which the clock signal is a variable frequency.