GB2168340A - Forming glass layers on semiconductor substrates - Google Patents
Forming glass layers on semiconductor substrates Download PDFInfo
- Publication number
- GB2168340A GB2168340A GB08529383A GB8529383A GB2168340A GB 2168340 A GB2168340 A GB 2168340A GB 08529383 A GB08529383 A GB 08529383A GB 8529383 A GB8529383 A GB 8529383A GB 2168340 A GB2168340 A GB 2168340A
- Authority
- GB
- United Kingdom
- Prior art keywords
- glass
- atmosphere
- integrated circuit
- contact holes
- pulse heating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011521 glass Substances 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 title description 4
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 12
- 239000001301 oxygen Substances 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims abstract 2
- 238000001465 metallisation Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000012530 fluid Substances 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- DLYUQMMRRRQYAE-UHFFFAOYSA-N tetraphosphorus decaoxide Chemical compound O1P(O2)(=O)OP3(=O)OP1(=O)OP2(=O)O3 DLYUQMMRRRQYAE-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005094 computer simulation Methods 0.000 description 1
- 238000004320 controlled atmosphere Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000005365 phosphate glass Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23D—ENAMELLING OF, OR APPLYING A VITREOUS LAYER TO, METALS
- C23D13/00—After-treatment of the enamelled articles
- C23D13/02—Removing defects by local re-melting of the enamel; Adjusting the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Materials Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
A glass coating on a substrate, e.g. an integrated circuit is planarised, by pulse heating the substrate provided with the glass to a temperature at which the glass becomes fluid. The glass viscosity is determined by control of an atmosphere in which heating is effected. Typically this atmosphere includes oxygen or water or is inert. The process is carried out under atmospheric pressure.
Description
SPECIFICATION
Forming glass layers on semiconductor substrates
This invention relates to a method of reflowing a glass insulating layer on a semiconductor surface.
With decreasing device geometries the problems associated with surface topography of an integrated circuit are becoming increasingly difficult to overcome. In particular there is a need to planarise the circuit surface prior to the application of the metallisation to avoid the risk of incomplete step coverage.
This problem is becoming particularly acute with the present trend towards a very high density of integration. Planarising surface coatings have been employed but, as device geometries become smaller, it has become difficult to provide adequately profiled contact openings. To avoid a sharp step around such openings, etches have been employed which form a tapered profile at the periphery of each opening.
However, unless etching is very carefully controlled, there is considerable risk of 'overbiowing' of the contact opening.
Attempts have been made to overcome this problem by the provision of a surface glass layer that is etched to provide contact openings and is then flowed across the device by heating to a temperature at which the glass becomes fluid thus profiling the edges of the contact openings. Typically a 30 minutes bake at 10000C is required for this purpose.
However this treatment then has an adverse effect on the device as a result of dopant redistribution.
Again this problem is accentuated by the small device dimensions involved. The problem of dopant redistribution has been overcome by pulse heating techniques. In a typical prior art process, such as that described in UK specification No. 2126418 A, a semiconductor circuit is coated with a phosphate glass and is then pulse heated in a vacuum for a period, typically 8 to 15 sec, sufficient to cause softening and flow of the glass. Whilst this technique is suitable for single planarising coatings it cannot readily be applied to structures using a plurality of metallisation levels. During the vacuum heating process phosphorus pentoxide is lost from the glass by evaporation. This significantly raises the softening point of the glass. Any subsequent reflow then requires a substantially higher processing temperature which may damage either the circuit or a deposited metallisation layer.It will also be appreciated that vacuum techniques are not readily compatible with processes requiring a high throughput rate.
The object of the present invention is to minimise or to overcome this disadvantage.
According to one aspect of the invention there is provided a method of flowing a glass across a substrate to provide a substantially smooth surface, the method including pulse heating the glass coated substrate in an inert or oxidising atmosphere at atmospheric pressure to a temperature above the softening point of the glass.
According to another aspect of the invention there is provided a method of contacting an integrated circuit with a metallisation pattern, the method including providing a first glass layer on the circuit, pulse heating the structure in an oxidising atmosphere to a temperature above the softening point of the glass whereby the glass is reflowed to planarise the surface, etching contact holes through the glass to expose contact regions on the substrate, pulse heating the structure in an inert atmosphere to a temperature above the softening point of the glass thereby rounding the edges of the contact holes, and applying a metallisation pattern to contact the circuit via the contact holes.
The pulse heating process is performed at ambient pressure in a controlled atmosphere which may be active or inert. We have found for example that the inclusion of oxygen or water in the atmosphere provides increased flow of the glass and hence increased planarisation for the same anneal time and temperature. Thus, priortothe contact hole etch, an oxygen or steam containing atmosphere can be used for transient reflow. By using two reflows it is possible to planarise the surface topography and round the contact hole edges thereby improving step coverage and yield. The degree of reflow is determined by control of the atmosphere in which the reflow is performed. Thus, for a given peak temperature, reflow is enhanced by the use of an oxidising atmosphere, e.g. oxygen or steam.We have found that oxygen reduces the softening temperature by 25 , and steam reduces the temperature by 500.
Embodiments of the invention will now be described with reference to the accompanying drawings in which:
Figures 1 to 4 illustrate successive stages in the fabrication of an integrated circuit;
Figures 5 and 6 illustrate the effects of conventional heat treatment and thermal pulse heating on dopant redistribution.
and Figures 7 and 8 illustrate the effect of reflow on contact hole sidewall angle and step planarisation respectively.
Referring to Figure 1 to 3, the circuit is formed on e.g. a silicon substrate 11 (Figure 1) and may comprise a plurality of transistors having doped drain and source regions, 12 and 13 respectively, separated by a gate region. The gate comprises an insulator film 14 and a polysilicon electrode 15. The transistor is surrounded by a wall 16 of oxide. The device is provided with a surface layer 21 (Figure 2) of a glass, typically by a chemical vapour deposition process. For this purpose we prefer to employ an 8% phosphosilicate glass deposited from a gaseous mixture of silane, phosphine and oxygen. This glass is a silica glass containing 8 weight % of phosphorus. Typically this glass layer 21 is about 8000 A (0.8 microns) in thickness. The glass as deposited follows the contours of the substrate surface.To provide a smooth surface for subsequent processing the glass 21 is subjected to a first reflow by pulse heating the structure in an atmosphere comprising e.g. oxygen, steam or mixtures thereof to a peak temperature of 1050 to 1075"C, typically for a period of 10 to 30 seconds. The assembly is then cooled and provided with a mask 31 (Figure 3) having openings 32 defining the positions of the device contacts. Contact openings 33 in the glass 21 are formed by plasma etching through the mask 31. For this purpose we prefer to employ a mixture of oxygen and a fluorine containing vapour. Typically we employ oxygen and a a mixture of CHF3 and C2F6. The contact holes 33 etched through the glass layer 21 expose the source, drain and gate of the transistor.
After contact hole etching the glass surface is smoothed and the contact hole edges rounded by a second reflow of the glass 21. This is effected by pulse heating the device to a temperature of about 11 00 C, i.e. about 1 000C to 1 500C above the glass softening point, for 10 to 20 seconds in an inert atmosphere, typically comprising nitrogen. The two reflows have been found to provide adequate surface smoothing without effecting significant dopant redistribution. For each reflow heating may be effected by irradiation from an infra-red halogen lamp.
After the second reflow of the glass has been effected metallisation 41 (Figure 4) is applied to contact the drain, source and gate. Typically the metallisation comprises aluminium or an aluminium alloy.
Although we prefer to employ a phosphosilicate glass the technique is not so limited. For example, borophosphosilicate, phosphogermanosilicate and arsenosilicate glasses may also be used.
The advantage of pulse heating over conventional furnace processing is illustrated in Figures 5 and 6 which show computer simulations of dopant redistribution for those two techniques. The two figures model the distribution of an arsenic dopant in a surface oxide and in the underlying silicon. As can be seen from Figure 6 the redistribution of arsenic resulting from the pulse heating process is insignificant.
To illustrate the technique described herein, an 8% phosphosilicate glass was deposited over nonplanar topography to investigate the planarisation of the glass as a function of anneal conditions. Contact holes were cut into the glass using an anisotropic etch and reflowed. The effect of the temperature and duration of anneal on the contact hole profile was studied by scanning electron microscopy. A similar series of experiments has been conducted on 4%/4% borophosphosilicate glass. This glass contained 4 weight % phosphorus and 4 weight % boron. The resuls of these tests are summarised in Figures 7 and 8.
Contact chains have been produced using transiently reflowed phosphosilicate glass and borophosphosilicate glass. Metal step coverage and contact resistance were investigated and compared to traditional reflow schedules. Both n and p+ diodes with xi 3000 A were fabricated to investigate the effect of the transient anneal on junction characteristics. After a total anneal time of 45 seconds at 11 000C the junction leakage is typically less than 10 nAcm-2 for both types of junction. The transient reflow has the additional benefit of fully activating all dopants. Sheet resistivities typically of 40 ohms per square have been obtained for both n+ arsenic junctions and p+ boron junctions.
These results indicate the compatibility of a transient reflow with a 2 micron CMOS technology.
As the pulse heating technique is transient, shallow junctions are substantially unaffected and improved device performance is thus obtained. Also the technique has the advantage of activating the doped layers in an advanced VLSI structure. Thus a single anneal can be used both to activate implanted species and to reflow the contact holes.
Claims (11)
1. A method of flowing a glass across a substrate to provide a substantially smooth surface, the method including pulse heating the glass coated substrate in an inert or oxidising atmosphere at atmospheric pressure to a temperature above the softening point of the glass.
2. A method as claimed in claim 1, wherein said atmosphere includes oxygen or steam.
3. A method as claimed in claim 1 wherein said atmosphere comprises nitrogen.
4. A method as claimed in claim 1,2 or 3, wherein said glass is a phosphosilicate, borophosphosilicate, phosphorogermanosilicate or arsenosilicate glass.
5. A method of contacting an integrated circuit with a metallisation pattern, the method including providing a first glass layer on the circuit, pulse heating the structure in an oxidising atmosphere to a temperature above the softening point of the glass whereby the glass is reflowed to planarise the surface, etching contact holes through the glass to expose contact regions on the substrate, pulse heating the structure in an inert atmosphere to a temperature above the softening point of the glass thereby rounding the edges of the contact holes, and applying a metallisation pattern to contact the circuit via the contact holes.
6. A method as claimed in claim 5, wherein the oxidising atmosphere comprises oxygen, steam or mixtures thereof.
7. A method as claimed in claim 5 or 6, wherein the inert atmosphere comprises nitrogen.
8. A method as claimed in claim 5, 6 or 7, wherein the contact holes are plasma etched with a mixture of oxygen and a fluorine containing vapour.
9. A method of contacting an integrated circuit substantially as described herein with reference to and as shown in Figures 1 to 4 of the accompanying drawings.
10. An integrated circuit provided with a glass surface coating by a method as claimed in any one of claims 1 to 4.
11. An integrated circuit contacted by a method as claimed in any one of claims 5 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08529383A GB2168340B (en) | 1984-12-13 | 1985-11-29 | Contacting an integrated circuit with a metallisation pattern |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB848431525A GB8431525D0 (en) | 1984-12-13 | 1984-12-13 | Forming glass layers |
| GB08529383A GB2168340B (en) | 1984-12-13 | 1985-11-29 | Contacting an integrated circuit with a metallisation pattern |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8529383D0 GB8529383D0 (en) | 1986-01-08 |
| GB2168340A true GB2168340A (en) | 1986-06-18 |
| GB2168340B GB2168340B (en) | 1988-11-02 |
Family
ID=26288570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08529383A Expired GB2168340B (en) | 1984-12-13 | 1985-11-29 | Contacting an integrated circuit with a metallisation pattern |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2168340B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001018848A2 (en) * | 1999-09-07 | 2001-03-15 | Steag Rtp Systems, Inc. | Pre-metal dielectric rapid thermal processing for sub-micron technology |
| WO2003029159A1 (en) | 2001-10-03 | 2003-04-10 | Qinetiq Limited | Coated optical components |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2097582A (en) * | 1981-04-28 | 1982-11-03 | Rca Corp | Process for tapering openings in glass coatings in semiconductor devices |
-
1985
- 1985-11-29 GB GB08529383A patent/GB2168340B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2097582A (en) * | 1981-04-28 | 1982-11-03 | Rca Corp | Process for tapering openings in glass coatings in semiconductor devices |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001018848A2 (en) * | 1999-09-07 | 2001-03-15 | Steag Rtp Systems, Inc. | Pre-metal dielectric rapid thermal processing for sub-micron technology |
| WO2001018848A3 (en) * | 1999-09-07 | 2001-05-17 | Steag Rtp Systems Inc | Pre-metal dielectric rapid thermal processing for sub-micron technology |
| US6514876B1 (en) | 1999-09-07 | 2003-02-04 | Steag Rtp Systems, Inc. | Pre-metal dielectric rapid thermal processing for sub-micron technology |
| WO2003029159A1 (en) | 2001-10-03 | 2003-04-10 | Qinetiq Limited | Coated optical components |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8529383D0 (en) | 1986-01-08 |
| GB2168340B (en) | 1988-11-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19991129 |