GB2140634A - Improvements relating to load trip circuits - Google Patents

Abstract

A load trip circuit comprises a plurality of transistors (TR1 to TR7) in which consequent upon the switching of the arrangement into operation a DC supply (+28V) is initially connected to the load (connected to terminal O/P) through one transistor (TR5) which is momentarily rendered conducting. During this momentary conduction of the transistor the load resistance is tested by monitoring the development of a voltage at terminal O/P which is representative of the resistance of the load and which renders another transistor (TR3) conducting when the voltage reaches a predetermined value indicative of the absence of short-circuiting in the load in order to supply current to the load. Under overload or short-circuit conditions in the load the transistor (TR3) is rendered non-conducting in order to disconnect the load supply. <IMAGE>

Description

SPECIFICATION Improvements Relating to Load Trip Circuits This invention relates to load trip circuits and one application thereof is in the load tripping circuit arrangement which forms the subject of our co-pending Patent Application No.

According to the present invention there is provided a load trip circuit comprising a plurality of transistors in which consequent upon the switching of the arrangement into operation a DC supply is initially connected to the load through one of said transistors which is momentarily rendered conducting and in which during such momentary conduction of the transistor the load resistance is tested by monitoring the development of a voltage which is representative of the resistance of the load and which renders another transistor conducting when said voltage reaches a predetermined value indicative of the absence of short-circuiting in the load in order to supply current to the load and in which under overload or short-circuit conditions in the load the latter transistor is rendered non-conducting in order to disconnect the load supply.

The load cannot be re-connected to the supply without the trip circuit being disconnected and again switched into operation, but even then the load will not be re-connected to the supply unless the short-circuit or overload condition which caused tripping of the trip circuit has been removed.

An example of the present invention will now be described with reference to the accompanying drawings which are identical to those included in our co-pending Patent Application No.

The load trip circuit of the present invention forms part of the overall circuit arrangement shown in Figure 1 of these drawings. In the drawings: Figure 1 is a circuit diagram of a load current tripping circuit arrangement; Figure 2 is a diagram depicting the load current/time delay characteristic of the load tripping circuit arrangement shown in Figure 1; and, Figure 3 shows the relevant pulse waveforms which are utilised in the circuit of Figure 1.

Referring to the drawings the overall load circuit tripping arrangement shown comprises a transistor oscillator OSC which in operation of the arrangement produces an output dependent upon the load current IL flowing through the primary conductor of a linear ferrite core transformer T1.

The frequency f of the oscillator output is a linear function of the load current IL.

The output from the oscillator OSC is applied to a binary counter BC which accordingly produces a first square-wave pulse output SQ1 of frequency f2-m (Figure 3). The binary counter BC also produces a second square-wave pulse output SQ2 of frequency 2-n which is an integral multiple of the frequency f2-m of the first squarewave pulse output from the counter BC. The two square-wave pulse outputs S01 and SQ2 from the binary counter are then fed to a timing circuit TC which effectively serves to convert the frequency of the oscillator into a time delay which is dependent upon load current as determined by the requisite load current/time delay characteristic of the circuit shown in Figure 2.For this purpose the timing circuit TC comprises a monostable multivibrator MV which is arranged to be operated to produce a rectangular-wave pulse output RW (Figure 3) having the leading edges of its pulses coincident with the corresponding edges of the pulses of the squarewave output SQl. The pulse period of the output RW is pre-set by adjustment of resistance and capacitor timing components R and C according to the aforesaid load current/time delay tripping characteristic of the circuit. As can be seen from the characteristic of Figure 2 the tripping time delay t of the circuit diminishes as the load current IL increases. Without limit controls, when IL equals the rated load current IR the delay t=cg and in the case of infinite load current the time delay t=to.However, the circuit arrangement is arranged to provide instant tripping of the load under load short-circuit conditions, as will be described later, and the time limit circuit TLC causes the characteristic to be truncated as shown when t=tL.

The characteristic of Figure 2 can be expressed as K(CONST) t= +to (IL-IR)2 The rectangular-wave pulse output RWfrom the monostable multivibrator MV is applied to one input of a three input gate G also in the timing circuit TC. The first and second squarn-wave pulse outputs S01 and SQ2 from the binary counter BC are applied to the other inputs of the gate G. As can be seen from Figure 3 the output from this gate G consists of pulses of frequency f2-n modulated by pulses of frequency f2-m having a duration corresponding to the difference between the duration of the square-wave pulses of frequency f2-m and the rectangular-wave pulses of the monostable output RW.

The number of pulses of frequency f2-" gated out in any given time period will be a measure of the load current IL. These pulses are fed to a comparator circuit COM of the timing circuit TC which.has applied to it a coded input which effectively determines the time delays apertaining to different load current values. Consequently, the comparator circuit COM counts the pulses of frequency f2-" in the gated output and if the number of pulses for a pre-determined time period exceeds the number indicated by the coded input to the comparator circuit the comparator produces an output which causes a latching circuit LA of the timing circuit TC to turn off an instant trip circuit PR which is constructed in accordance with the present invention and which disconnects the load from the supply.If, however, the number of pulses indicated by the code input is not reached in the predetermined time period (t) the counting cycle of COM is terminated by an output signal from the circuit TLC and a further counting cycle of COM started.

In operation of the present embodiment the load will be supplied with current from a DC supply (e.g.+28V) and will be connected between the output terminal O/P and ground potential (i.e.

OV). As already mentioned, the load current in the present example also flows through the primary conductor of transformer T1, but it should be understood that this could comprise a load representative current rather than the load current itself, and it may continue to flow after the load current has been switched off.

Considering now the full operation of the circuit arrangement, when the DC supply referred to is applied to the circuit, the oscillator OSC commences to operate at its free running frequency since at this stage there is zero load current. The oscillator OSC has a temperature compensating circuit TX associated with it to regulate the supply to the oscillator.

As previously explained, the binary counter BC will produce square-wave outputs SQ1 and SQ2 in response to the oscillator output but the pulses of SQ1 will fail to produce the overlap condition with the rectangular pulse-wave output RW from the monostable multivibrator MV which is necessary to obtain gated-out pulses representing load current.

At this stage, with the DC supply connected to the circuit PR, the transistors TR 1, TR2 and TR6 are switched on whereas the transistors TR3, TR4, TR5 and TR7 are in the off condition. In order to connect the load supply circuit, the terminals H and L are short-circuited to switch the circuit PR into operation. By so doing, the transistors TR1 and TR2 are switched off. Transistor TR5 is switched on as transistor TR 1 switches off momentarily for a time period dependant upon the values of the capacitor C1 and resistor R8 after which transistorTR1 conducts again and transistorTR5 is switched off. However, during the time that transistor-TR5 is switched on, a current is supplied to the load through the conducting transistor TR5 and resistor R6.Provided the load presents a sufficient resistance (i.e. not shortcircuited condition) a voltage will be developed between the terminal O/P) and ground potential to turn on the transistor TR3. This transistor turns on momentarily and consequently turns on transistor TR4. This results in transistor TR6 being switched off which in turn causes transistor TR7 to be switched on. Load current is now supplied to the load through the transistor TR7. Transistor TR6 is then held switched off by maintaining its emitter voltage above its base voltage and TR7 is held on by a voltage derived from a secondary winding S1 of the transformer T1 . Once the load is supplied with current, the time delay circuit tripping arrangement already described comes into operation.

If, however, high overload or short-circuit conditions obtain, then according to the operation of the instant trip circuit PR the voltage at the source of the transistor TR7 drops and this reduced voltage is reflected through to the emitter of transistor TR6 and when it falls below the base voltage of TR6 the transistor TR6 starts to turn on. The gate voltage of transistor TR7 accordingly drops which increases the resistance of TR7 and by rapid regenerative action TR6 is turned on fully and TR7 switched off to disconnect the load. Transistor TR6 holds transistor TR7 off. If the terminals L and H remain short-circuited when the load circuit is tripped the instant trip circuit PR remains inoperative until the terminals L and H are open-circuited and then again short-circuited.

If, when the terminals L and H are shortcircuited again, the high overload condition still obtains, the transistor TR6 will be maintained in an on condition in order to prevent the transistor TR7 from being switched on and so re-connecting the load circuit to the supply.

As will be apparent from the foregoing, the circuit arrangement which has been described with reference to the drawings provides a high overload instantaneous trip facility afforded by the trip circuit according to the present invention and a delayed tripping facility which is dependant upon the value of load current.

Claims (4)

1. A load trip circuit comprising a plurality of transistors, in which consequent upon the switching of the arrangement into operation a dc supply is initially connected to the load through one of said transistors which is momentarily rendered conducting and in which during such momentary conduction of the transistor the load resistance is tested by monitoring the development of a voltage which is representative of the resistance of the load and which renders another transistor conducting when said voltage reaches a predetermined value indicative of the absence of short-circuiting in the load in order to supply current to the load and in which under overload or short-circuit conditions in the load the latter transistor is rendered non-conducting in order to disconnect the load supply.

2. A load trip circuit as claimed in claim 1, in which means are provided to prevent the load being re-connected to the supply without the trip circuit being disconnected and again switched into operation.

3. A load trip circuit as claimed in claim 1 or claim 2 in combination with the load tripping circuit arrangement forming the subject or our co-pending Patent Application No.8311754.

4. A load trip circuit substantially as hereinbefore described with reference to the accompanying drawings.