GB2140633A - Load tripping circuits - Google Patents

Abstract

A load tripping circuit arrangement comprises an oscillator (OSC) the output frequency of which is a linear function of the load current. It also includes pulse generating means (BC) responsive to the output from the oscillator (OSC) to produce a first square-wave pulse output (SQ1) the frequency of which is dependent upon load current and a second square-wave output (SQ2) the frequency of which is an integral multiple of the frequency of the first square-wave pulse output (SQ1). The outputs (SQ1 and SQ2) are fed to a timing circuit (TC) in which the pulses of the first square-wave pulse output (SQ1) are effectively compared with those of a pre-set rectangular-wave pulse output (RW). Pulses of the output (SQ2) are gated out during overlap period between pulses of output (SQ1) and output (RW) and the number of gated-out pulses occurring during successive time periods are counted continuously and the load current interrupted if the counted number for a particular time period exceeds the number appropriate to the load current/time delay characteristic of the circuit. <IMAGE>

Description

SPECIFICATION Improvements Relating to Load Tripping Circuits This invention relates to load tripping circuit arrangements and relates more specifically to such arrangements for the tripping of the load when load current reaches predetermined values on a load current/time delay characteristic.

According to the present invention in its broadest aspect a load tripping circuit arrangement comprises means for producing a signal having a frequency dependent upon load current and means for causing interruption of the load circuit if the value of said signal frequency and thus the value of load current persits for variable time periods determined in accordance with the load current/time delay characteristic of the circuit arrangement.

The load tripping circuit arrangement may comprise an oscillator, the output frequency of which is a linear function of the load current, pulse generating means responsive to the output from the oscillator to produce a first square-wave pulse output the frequency of which is dependent upon load current and a second square-wave pulse output the frequency of which is an integral multiple of the frequency of the first square-wave pulse output, said first and second square-wave pulse outputs being fed to a timing circuit in which the pulses of the first square-wave pulse output are effectively compared with those of a preset rectangular-wave pulse output, in which pulses of the second square-wave pulse output are gated out during the overlap period between pulses of the first square-wave pulse output and the rectangular-wave output and in which the number of gated-out pulses occurring during successive time periods are counted continuously and the load current interrupted if the counted number for a particular time period exceeds the number appropriate to the load current/time delay characteristic of the circuit.

By way of example the present invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of a load current tripping circuit arrangement; Figure 2 is a diagram depicting the load current/time delay characteristic of the load tripping circuit arrangement shown in Figure 1; and, Figure 3 shows the relevant pulse waveforms which are utilised in the circuit of Figure 1.

Referring to the drawings the load circuit tripping arrangement shown comprises a transistor oscillator OSC which in operation of the arrangement produces an output dependent upon the load current IL flowing through the primary conductor of a linear ferrite core transformer Ti.

The frequency f of the oscillator output is a linear function of the load current IL.

The output from the oscillator OSC is applied to a binary counter BC which accordingly produces a first square-wave pulse output SQ1 of frequency f2-m (Fig. 3). The binary counter BC also produces a second square-wave pulse output SQ2 of frequency f2-" which is an integral multiple of the frequency f2-m of the first squarewave pulse output from the counter BC. The two square-wave pulse outputs SQ1 and SQ2 from the binary counter are then fed to a timing circuit TC which effectively serves to convert the frequency of tha oscillator into a time delay which is dependent upon load current as determined bythe requisite load current/time delay characteristic of the circut shown in Figure 2.For this purpose the timing circuit TC comprises a monostable multivibrator MV which is arranged to be operated to produce a rectangular-wave pulse output RW (Fig. 3) having the leading edges of its pulses coincident with the corresponding edges of the pulses of the square-wave output SQ1. The pulse period of the output RW is pre-set by adjustment of resistance and capacitor timing components R and C according to the aforesaid load current/time delay tripping characteristic of the circuit. As can be seen from the characteristic of Figure 2 the tripping time delay t of the circuit diminishes as the load current IL increases.

Without limit controls, when IL equals the rated load current IR the delay t=ce and in the case of infinite load current the time delay t=to. However, the circuit arrangement is arranged to provide instant tripping of the load under load shortcircuit conditions, as will be described later, and the time limit circuit TLC causes the characteristic to be truncated as shown when t=tL.

The characteristic of Fig. 2 can be expressed as (CONST) t=K +to (IL-IR)2 The rectangular-wave pulse output RWfrom the monostable multivibrator MV is applied to one input of a three input gate G also in the timing circuit TC. The first and second square-wave pulse outputs SQ1 and 5Q2 from the binary counter BC are applied to the other inputs of the gate G. As can be seen from Figure 3 the output from this gate G consists of pulses of frequency f2-" modulated by pulses of frequency f2-m having a duration corresponding to the difference between the duration of the square-wave pulses of frequency f2rn and the rectangular-wave pulses of the monostable output RW.

The number of pulses of frequency f2-" gated out in any given time period will be a measure of the load current IL. These pulses are fed to a comparator circuit COM of the timing circuit TC which has applied to it a coded input which effectively determines the time delays appertaining to different load current values.

Consequently, the comparator circuit COM counts the pulses of frequency f2 in the gated output and if the number of pulses for a pre-determined time period exceeds the number indicated by the coded input to the comparator circuit the comparator produces an output which causes a latching circuit LA of the timing circuit TC to turn off an instant trip circuit PR to disconnect the load from the supply. If, however, the number of pulses indicated by the code input is not reached in the predetermined time period (t,) the counting cycle of COM is terminated by an output signal from the circuit TLC and a further counting cycle of COM started.

In operation of the present embodiment the load will be supplied with current from a DC supply (e.g. +28V) and will be connected between the output terminal OjP and ground potential (i.e. OV). As already mentioned, the load current in the present example also flows through the primary conductor of transformer T1, but it should be understood that this could comprise a loads representative current rather than the load current itself, and it may continue to flow after the load current has been switched off.

Considering now the full operation of the circuit arrangement, when the DC supply referred to is applied to the circuit, the oscillator OSC commences to operate at its free running frequency since at this state there is zero load current. The oscillator OSC has a temperature compensating circuit TX associated with it to regulate the supply to the oscillator.

As previously explained, the binary counter BC will produce square-wave outputs SQ1 and SQ2 in response to the oscillator output but the pulses of SQ1 will fail to produce the overlap condition with the rectangular pulse-wave output RW from the monostable multivibrator MV which is necessary to obtain gated-out pulses representing load current.

At this stage, with the DC supply connected to the circuit, the transistors TR1 , TR2 and TR6 are switched on whereas the transistors TR3, TR4, TR5 and TR7 are in the off condition. In order to connect the load supply circuit, the terminals H and L are short-circuited. By so doing, the transistors TR1 and TR2 are switched off.

Transistor is switched on as transistor TR1 switches off momentarily for a time period dependant upon the values of the capacitor C1 and resistor R8 after which transistor TR 1 conducts again and transistor TR5 is switched off.

However, during the time that transistor TR5 is switched on, a current is supplied to the load through the conducting transistor TR5 and resistor R6. Provided the load presents a sufficient resistance (i.e. not short-circuited condition) a voltage will be developed between the terminal O/P and ground potential to turn on the transistor TR3. This transistor turns on momentarily and consequently turns on transistor TR4. This results in transistor TR6 being switched off which in turn causes transistor TR7 to be switched on. Load current is now supplied to the load through the transistor TR7. Transistor TR6 is then held switched off by maintaining its emitter voltage above its base voltage and TR7 is held on by a voltage derived from a secondary winding S1 of the transformer T1.Once the load is supplied with current, the time delay circuit tripping arrangement already described comes into operation.

If, however, high overload or short-circuit conditions obtain, then the voltage at the source of the transistor TR7 drops and this reduced voltage is reflected through to the emitter of transistor TR6 and when it falls below the base voltage of TR6 the transistor TR6 starts to turn on.

The gate voltage of transistor TR7 accordingly drops which increases the resistance of TR7 and by rapid regenerative action TR6 is turned on fully and TR7 switched off to disconnect the load.

TransistorTR6 holds transistor TR7 off. If the terminals L and H remain short-circuited when the load circuit is tripped the instant tripping circuit PR remains inoperative until the terminals L and H are open-circuited and then again short-circuited.

If, when the terminals L and H are shortcircuited again, the high overload condition still obtains, the transistor TR6 will be maintained in an on condition in order to prevent the transistor TR7 from being switched on and so re-connecting the load circuit to the supply.

As will be apparent from the foregoing, the circuit arrangement which has been described with reference to the drawings provides both a high overload instantaneous trip facility in addition to the delayed tripping faciiity according to the invention which is dependent upon the value of load current.

Claims (6)

1. A load tripping circuit arrangement comprising signal generating means for producing a signal having a frequency dependent upon load current and means for causing interruption of the load circuit if the value of said signal frequency and thus the value of load current persists for variable time periods determined in accordance with the load currentitime delay characteristic of the circuit arrangement.

2. A load tripping circuit arrangement as claimed in claim 1, in which the signal generating means comprises pulee generating means which produces a first square-wave pulse output the frequency of which is dependent upon load current and a second square-wave pulse output the frequency of which is an integral multiple of the frequency of the first square-wave pulse output, the first and second square-wave pulse outputs being fed to a timing circuit in which pulses of the first square-wave pulse output are effectively compared with those of a pre-set rectangular-wave pulse output and pulses of the second square-wave pulse output being gated out during the overlap period between pulses of the first square-wave pulse output and the rectangular-wave output and in which the number of gated-out pulses occurring during successive time periods are counted continuously and the load current interrupted if the counted number for a particular time period exceeds the number appropriate to the load current/time delay characteristic of the circuit.

3. A load tripping circuit arrangement as claimed in claim 2, in which the signal generating means includes an oscillator the output frequency of which is a linear function of load current and the pulse generating means is responsive to the output from the oscillator.

4. A load tripping circuit arrangement as claimed in claim 2 or claim 3, in which the timing circuit during operation of the arrangement has applied to it a coded input which determines the time delays before load interruption appertaining to different load values.

5. A load tripping circuit arrangement as claimed in any preceding claim, in which the arrangement comprises an instant tripping circuit which interrupts the load circuit instantly under high overload or short-circuit conditions.

6. A load tripping circuit arrangement substantially as hereinbefore described with reference to the accompanying drawings.