GB2134706A

GB2134706A - Composite conductor structure for semiconductor devices

Info

Publication number: GB2134706A
Application number: GB08331916A
Authority: GB
Inventors: Osamu Kasahara; Shinji Shimizu; Hiroyuki Miyazawa; Kensuke Nakata
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1980-11-07
Filing date: 1983-11-30
Publication date: 1984-08-15
Also published as: FR2494042B1; MY8600583A; GB2087148B; IT8124891A0; JPS5780739A; GB2134706B; IT1140271B; DE3141195C2; HK44686A; FR2494042A1; GB8331916D0; HK70586A; DE3141195A1; GB2087148A

Abstract

In a semiconductor integrated circuit device comprising a memory cell array and peripheral circuitry conductive layers are of three-layer construction consisting of a polycrystalline silicon layer (27) a silicide layer (35) of silicon and a refractory metal formed on the polycrystalline silicon layer, and a refractory metal layer (42) formed on the silicide layer. The refractory metal may be molybdenum, titanium, tantalum or tungsten. The peripheral circuitry has interconnecting lines and MISFET gates formed of such conductive layers. <IMAGE>

Description

1 GB 2 134 706 A 1

SPECIFICATION

Semiconductor devices and a process for 65 producing the same Background of the invention

The present invention relates to semiconductor integrated circuit devices and a process for producing the same.

In semiconductor integrated circuit devices, and particularly in semic6nductor integrated circuit devices containing a plurality of metal oxide film semiconductor-type field effect transistors (hereinafter referred to as MISFET's), the wiring layer has often been made of polycrystalline silicon which has resistance against heat and self aligning properties, instead of aluminum. The polycrystalline silicon is doped with impurities in order to reduce its very great resistivity. Even after doping with impurities, however, the polycrystalline silicon still exhibits great resistivity compared with aluminum. In the semiconductor integrated circuit devices employing polycrystalline silicon as a wiring layer, therefore, the defect is that the signals are transmitted at slow speeds.

In order to preclude the above-mentioned defect, therefore, it has been known to use a refractory metal such a molybdenum, tungsten, platinum, or tantalum as a material for forming wiring layers (Japanese Patent Laid-Open No.

80986/1978). When a refractory metal is used in pure form as a material for forming wiring layers in the semiconductor integrated circuit device, the device will exhibit small resistivity and increased resistance against the heat treatment, but will present defects such as poor adhesiveness of the layer to the S'02 film or SiN4 film.

Therefore, it has been attempted to use a silicide layer composed of silicon and a refractory metal as a wiring layer for the semiconductor integrated circuit devices (Japanese Patent Laid- Open No. 80986/1978). This wiring layer, 1.05 however, cannot be intimately -adhered onto the S'02 film, and does not provide good contacting property to the silicon substrate, either.

In order to eliminate the above-mentioned defects, furthermore, an attempt has been made to use a wiring layer with double-layer construction consisting of a polycrystalline silicon layer and a silicide layer of silicon and a refractory metal formed on the polycrystalline silicon layer (Japanese Patent Laid- Open No. 88783/1979). Here, however, the wiring layer with the doublelayer construction has a resistivity which is considerably greater than that of a pure refractory metal though it varies depending upon the silicon content in the silicide layer. For example, when molybdenum is used as the refractory metal, the wiring layer consisting of a polycrystalline silicon layer and a silicide layer of silicon and molybdenum formed on the polycrystalline silicon layer, exhibits a resistivity of 100 to 1 5OX 10-6 ohms.cm in contrast with the resistivity of pure molybdenum of about 1 5X 10-6 ohms.cm.

Summary of the invention

The present invention consists in the use of a three-layer construction comprising a polycrystalline silicon layer, a silicide layer which consists of silicon and a refractory metal and which is formed on said polycrystalline silicon layer, and a refractory metal layer formed on said silicide layer.

One aspect of the present invention provides a semiconductor device comprising a semiconductor substrate, an insulating film formed on one main surface of said semiconductor substrate, and a conductive layer selectively formed on said insulating film, said conductive layer being composed of a polycrystalline silicon layer, a silicide layer which consists of silicon and a refractory metal and which is formed on said polycrystalline silicon layer, and a refractory metal layer formed on said silicide layer.

Brief description of the drawings 85 Figt 1 is a section of a semiconductor integrated circuit device according to an embodiment of the present invention; Fig. 2 is a circuit diagram of a D-RAM according to the present invention; 90 Fig. 3 is a diagram of the lay-out pattern of a D RAM IC of the two-mat system according to the present invention; Fig. 4 is a perspective sectional view showing the construction of memory cell elements according to the present invention; Fig. 5 is a perspective sectional view showing the construction of dummy cell elements according to the present invention; Fig. 6 is a perspective sectional view showing a portion of the elements in an active restore circuit according to the present invention; Fig. 7 is a diagram of the lay-out pattern of a memory array and a dummy array according. to the present invention; Fig. 8 is a plan view showing a portion of a semiconductor substrate which illustrates the state of a field insulation film according to the present invention;

Fig. 9 is a plan view showing a portion of a semiconductor substrate which illustrates the state of a first conductor layer according to the present invention; Fig. 10 is plan view of a semiconductor integrated circuit device which constitutes the active restore circuit according to the present invention; and Figs. 11 A to 11 S are sectional views of the semiconductor integrated circuit device in each of the steps for producing the D-RAM according to the present invention.

Description of the preferred embodiments

The invention will be described below with reference to an embodiment.

Fig. 1 is a section view of an MIS-type semiconductor integrated circuit device according to an embodiment of the present invention, in 2 GB 2 134 706 A 2 which reference numeral 51 denotes a p-type silicon substrate, and 52 denotes a field insulating film which is selectively formed by thermal oxidation. An MISFET is formed in a region surrounded by the field insulating film 52. The

MISFET consists of a gate insulating film 53 formed by surface oxidation; a gate electrode of a three-layer construction which is made up of a polycrystalline silicon layer 542, a silicide layer (hereinafter referred to as molybdenum silicide layer) 552 of silicon and molybdenum, and a pure molybdenum layer 562; and an N±type semiconductor region 572 which is formed using the gate electrode as a mask and which serves as a self-aligned source region or a drain region; and 80 an N±type semiconductor region 573.

The NI-type semiconductor region 572 is connected to other MISFET's through a wiring layer of a three-layer construction consisting of a polycrystalline silicon layer 541, a silicide layer (hereinafter referred to as molybdenum silicide layer 551) of silicon and molybdenum, and a pure molybdenum layer 561, which is in direct contact with an NI-type semiconductor region 571 that is continuous with the N±type semiconductor region 572. Further, the N±type semiconductor region 573 is connected to other MISFET's through an aluminum layer 60.

The above gate electrode works not simply as a gate for the MISFET but also as a wiring layer for connecting the gate electrode to, for example, the gates of other MISFET's in the semiconductor integrated circuit device.

As mentioned already, the time required for transmitting the signals through the wiring layer 100 in the semiconductor integrated circuit should be as short as possible and, for this purpose, the resistivity should be as small as possible. In a dynamic random access memory, in particularly, it is desired to reduce the resistivity of the wiring 105 layer as far as possible to increase the speed of transmission of the signals.

The wiring layer of the three-layer construction consisting of a polycrystalline silicon layer, a molybdenum silicide layer and a pure molybdenum layer, exhibits a resistivity of about to 35 microohms - cm. This is about twice that of pure molybdenum which has a resistivity of about 15 microohms - cm, and is about one-fifth to one-third that of the conventional wiring layer 115 which wholly or partly consists of a refractory metal.

The reason whhsuch a small resistivity can be realized is attributed to the presence of the layer of pure molybdenum which forms the uppermost layer of the wiring layer. According to the study conducted by the inventors of the present invention, it was clarified that even when a heat treatment is performed during or after the wiring layer is formed, the three layers constituting the wiring layer do not react among themselves, but retain their properties. Moreover, the Polycrystalline silicon layer which forms the lowermost layer of the wiring layer adheres intimately to an insulating film such as S'02 film' 130 S'3N4 film or the like, and also comes into ohmic contact with the silicon substrate.

The wiring layer of the three-layer construction of the present invention shown in Fig. 1, can be obtained as mentioned below. The polycrystalline silicon layers 541, 542 is formed over the whole surface by the vapor-phase chemical reaction method (CVD method) to a thickness of about 1500 to 2500 angstroms, and is doped with phosphorus ions to a high concentration to reduce the resistivity. Thereafter, molybdenum silicide layer 551, 552 is formed over the whole surface of the polycrystalline silicon layer by, for example, co-sputtering to a thickness of about 1000 angstroms. The silicon content will be 10% by weight. Then, pure molybdenum layer 561, 562 is formed on the whole surface of the molybdenum silicide layer by, for example, the sputtering method to a thickness of about 1500 angstroms.

Using C174+02 gas, the above-mentioned layers are continuously subjected to plasma etching to form a wiring layer of the three-layer construction having a predetermined shape as shown in Fig. 1.

Thereafter, the wiring layer is annealed in a nitrogen atmosphere such that the uppermost molybdenum layers 561, 562 will not be oxidized or sublimated. The annealing is effected in order that silicion is uniformly dispersed in the molybdenum layers 551, 552 which contain silicion.

In performing the annealing, it was found that the above-mentioned three layers cease to exist if the silicon is contained in a stoichlometric amount, i.e., when the silicon content is 37% by weight. Namely, when the silicon is contained in a stoichiometric amount, the individual layers undergo chemical reaction, and the stress resulting from the contraction of volume causes the individual layers to be peeled off from each other.

With the present method, however, the abovementioned three layers are bonded to each other, and the resistivity of the wiring layer can be reduced to a value as small as 30 to 35 microohms-cm.

Furthermore, the following effects can be obtained:

(1) It is possible to prevent the formation of S'02 film on the interface between the polycrystalline silicon layers 541, 542 and the molybdenum silicide layers 551, 552. The molybdenum silicide layers 551, 552 are formed by co-sputtering. In this case, oxygen in the atmosphere is taken into the molybdenum silicide layers 551, 552. Prior to reacting with silicon in the polycrystalline silicon layers 541, 542, the oxygen reacts with silicon contained in the molybdenum silicide layers 551, 552 to form S'02. Therefore, no S'02 film is formed on the interface. Further, since silicon is present in an isolated manner in the molybdenum silicide layers 5 51, 552, the S'02 film is not formed in a continuous manner. Further, the oxygen in the atmosphere is taken into the molybdenum layers 561, 562 when they are being formed by the 3 GB 2 134 706 A 3 sputtering. The oxygen reacts with silicon in the molybdenum silicide layers 551, 552. However, since silicon is present in an isolated manner, oxide film is not formed continuously on the interface.

Since no oxide film is formed on the interface, the resistivity of the wiring layer does not increase.

It was found through the study conducted by the inventors-of the present invention that a substance that serves as an oxygen getter should be contained in the second layer so that oxygen taken from the atmosphere will -not form an oxide film on the interface. It was confirmed that such a substance needs be contained in an amount of 5% by weight to 10% by weight. The substance which serves as an oxygen getter should be determined by taking into consideration the chemical relation to the three layers forming the wiring layer, i.e., by taking into consideration the adhesiveness and the chemical reaction that may take place during the step of heat treatment.

(2) When the wiring layer consisting of the polycrystalline silicon layer 541, the molybdenum silicide layer 551 formed thereon, and the molybdenum layer 561, is brought into direct contact with the semiconductor region to form an electrode, the resulting ohmic contact obviates the need for forming a high-concentration region.

This is due to the fact that impurities doped in the polycrystalline silicon are diffused into the semiconductor region to form a highconcentration region.

(3) Impurities are taken from the atmosphere into the molybdenum silicide layers 551, 552 when they are formed by the co-sputtering. However, since there exists a polycrystalline silicon layer therebetween, impurities such as sodium ions are not diffused into the activated semiconductor region.

As described above, therefore, it is possible to obtain a semiconductor integrated circuit device having a small resistivity and a short signal trasmission time.

The invention will be described below by way 110 of concrete embodiments. In the below mentioned embodiments, the present invention is adapted to a dynamic random access memory (hereinafter referred to as D-RAM).

First, the setup of the D-RAM circuit is briefly 115 mentioned below with reference to Fig. 2.

The D-RAM circuit consists of an address buffer ADB for introducing address signals A.-Aj, a row and column decoder RC-DCR for selecting a given row address line and a given column address line from the row address signals A.-A, and the column address signals A,+,-A,, a memory array M-ARY having a plurality of memory cells M-CEL's, a dummy array DARY having a plurality of dummy cells D-CEL's, a column switch C-SW1 for selecting any data line in the M-ARY responsive to a selected column address signal, a sense amplifier SA, a data input buffer DIB, an output amplifier OA, and a data output buffer DOB.

The M-CEL consists of a capacitor C. for.storing the data and an MiSFET Qm for selecting the address, and the data---1 " or "0" is stored in the form of whether there is electric charge in the capacitor C, or not.

The D-RAM circuit is arrayed on a single semiconductor chip as concretely shown in Fig. 3.

Fig. 3 is a diagram of lay-out pattern of the D- RAM IC of a so-called two-mat system in which the-memory array is divided into two in a single semiconductor chip.

First, the two memory arrays M-ARY, and MARY 2 consisting of a plurality of memory cells are placed in an IC chip, separated away from each other.

A common column decoder C-DiCR is arrayed on the central portion of the IC chip between M ARY1 and M-ARY The column switch C-SW, for the M-ARY1 and the dummy array D-ARY1 consisting of a plurality of d - ummy cells are placed between M-ARY, and C-DICR.

On the other hand, the column switch C-SW2 for the M-ARY2 and the dummy array D-ARY2 consisting of a plurality of dummy cells are placed between M-ARY2 and C-DCR, The sense amplifiers SA, and SA2 are located at an extreme left portion and at an extreme right portion of the IC chip, so that they will not be erroneously operated by noise such as signals applied to the C-DCR, and so that the wiring can be easily laid out.

On the upper left side of the IC chip are arrayed a data input buffer DIB, a read and write control signal generator F1/W- SG, a RAS signal generator RAS-SG, and a RAS family signal generator SG,. Adjacent to these circuits, there are further R-AS -- arrayed a AS signal applying pad P RAS, a WE signal applying pad P-WE, and a data signal applying pad P-1),,.

On the upper right side of the [C chip, on the other hand, there are arrayed a data output buffer DOB, a CAS signal generator CAS-SG, and a CAS family signal generator SG2. Adjacent to these circuits, there are arrayed a V.S voltage supplying pad P-V,,, a CAS signal applying pad P- CAS, a data signal output pad P-D.,t, and an address signal A, sdpplying pad P-A,.

A main amplifier MA is placed between the RAS family signal generator SG, and the CAS family signal generator SG,.

A V,,, generator V,.7G is located above a circuit which occupies large areas such as RAS family signal generator SG1, CAS family signal generator SG, or main amplifier MA. This is because, the V..-G produces a minority carrier, and the data in the memory cells constituting the M-ARY, and MARY2 may be undesirably inverted by the minority carriers. In order to prevent such a probability, therefore, the V.. generator V,,-13 is located at a position remote from the M-ARY, and M- ARY2.

The row decoder FI-DCR, for the M-ARY1 is located on the lower left side of the IC chip.

Adjacent to the R-DCR1, there are arrayed address 4 GB 2 134 706 A 4 signal supplying pads P-A0, P-Al, P-A2, and a V,, 65 voltage supplying pad P-V,c.

On the lower right side of the IC chip, on the other hand, there is provided a row decoder R- DCR2 for the M-ARY2. Adjacent to the raw decoder R-DCR21 there ararrayed address signal applying pads P-A, P-A41 P- A, and P-A7. An address buffer ADB is disposed between RDCR, and R-DCR2. 10 The D-RAM IC has a capacity of about 64 kilobits divided into two memory cell matrixes (memory arrays WARY, and M-ARY2) each having a memory capacity of 128 rowsx256 columns=32,768 bits (32 kilobits). Therefore, one 15 memory array has 128 word lines WL and 256 data lines DL. The above data lines DL are made of aluminum and have a small resistivity. Further, as will be obvious from Fig. 3, the data lines DL are short and impose no problem with regard to the time for transmitting the signals applied by the column decoder C-DCR to each of the memory cells.

On the other hand, as will be understood from Fig. 3, the word lines WL are much longer than the data lines DL. If the word lines WL have large resistivities, extended periods of time are needed to transmit the signals applied by the row decoder R-DCR to each of the memory cells, particularly to transmit the signals applied by the row decoder R-DCR to the memory cells located at the most remote positions.

The signal transmission time of the word lines WL determines the operation time of the D-RAM, and eventually determines the operation time of the whole D-RAM system.

According to the embodiment of the present invention, the word lines WL consist of a polycrystalline silicon layer, a molybdenum silicide layer formed thereon, and a pure molybdenum layer formed further thereon, as shown in Fig. 1. The word lines have a resistivity of 30 to 35 microohms cm which is one-fifth to one-third that of the conventional word lines. According to the embodiment of the present invention, therefore, the D-RAM permits the signals to transmit in less time than the conventional D-RAM, and operates at speeds faster than the conventional D-RAM. Further, the whole D-RAM system can be operated at high speeds.

According to the embodiment of the present invention, furthermore, not only the word lines but 115 also the gate electrodes of all MISFET's in the DRAM are formed in the three-layer construction.

Accordingly, the D-RAM operates at higher speeds.

Construction of the principal elements and lay- 120 out pattern in the embodiment of the present invention will be discussed below in further detail.

[Construction of memory cell M-CEL] Fig. 4 is a perspective section view showing the construction of a memory cell M-CEL of Fig. 2, in which reference numeral 1 denotes a p-type semiconductor substrate, 2 denotes a relatively thick insulating film (hereinafter referred to as field insulating film), 3 denotes a relatively thin insulating film (hereinafter referred to as gate insulating film), 4 and 5 denote N'-type semiconductor regions, 6 denotes a first polycrystalline silicon layer, 7 denotes an n-type surface inverter layer, 8 denotes a second polycrystalline silicon layer, 9 denotes a PSG (phosphorus silicate glass) layer, 10 denotes an aluminum layer, 29 denotes a molybdenum silicate layer, and 36 denotes a molybdenum layer.

A MISFET QM in a memory cell M-CEL has a substrate, a source region, a drain region, a gate insulating film and a gate electrode, that are, respectively, made up of the above-mentioned ptype semiconductor substrate 1, the n'-type semiconductor region 4, the n'-type semiconductor region 5, the gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 8, a molybdenum silicide layer 29, and a molybdenum layer 36. The multi-layer electrode can be used, for example, as a word line WL,-2 which is shown in Fig. 2. The aluminum layer 10 connected to the n±type semiconductor region 5 is used, for example, as a data line DL1_1 which is shown in Fig. 2.

On the other hand, a memory capacitor C. in the memory cell M-CEL has an electrode, a dielectric layer and another electrode which are, respectively, made up of a first polycrystalline silicon layer 6, a gate insulating film 3, and an ntype surface inverted layer 7. Namely, the powersupply voltage VCC applied to the first polycrystalline silicon layer 6 induces the n-type surface inverted layer 7 on the surface of the ptype semiconductor substrate 1 through the gate insulating film 3 owing to the effect of the electric field.

[Construction of dummy cell D-CELI Fig. 5 is a perspective section view showing the construction of a dummy cell D-CEL which is illustrated in Fig. 2. In Fig. 5, reference numerals 11 to 14 denote n1-type semiconductor regions, 15 denotes a first polycrystalline silicon layer, 16 denotes an n-type surface inverted layer, 17 and 18 denote second polycrystalline silicon layers, 19 denotes an aluminum layer, 30 and 31 denote molybdenum silicide layers, and 37 and 38 denote molybdenum layers.

A MISFET QD1 in a dummy cell D-CEL has a substrate, a drain region, a source region, a gate insulation film and gate electrode, which are, respectively, made up of the p-type semiconductor substrate, an n±type semiconductor region 11, an n'-type semiconductor region 12, a gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 17, a molybdenum silicide layer 30 and a molybdenum layer 37. The multi-layer electrode stretches on the p-type semiconductor substrate 1 as a dummy word line DWL,-2 which is shown in Fig. 2. The aluminum GB 2 134 706 A 5 layer 19 connected to the n--type semiconductor region stretches on the p-type semiconductor substrate 1 as a dummy data line M-1-1 shown in Fig. 2.

A MISFET QD2-in the dummy qell D-CEL has a substrate, a drain region, a source region, a-gate 70 insulating film and a gate electrode, that are, respectively, made up of the p-type semiconductor substrate 1, an n±type semiconductor region 13, an n'-type semiconductor region 14, a gate insulating film 3, and a multi-layer electrode consisting -of a second polycrystalline silicon layer 18, a molybdenum silicide layer 31 and a molybdenum layer 38. The multi-layer electrode is served with a discharge signal OdC which is diagrammed in the dummy cell D-CEL of Fig. 2.

The capacitor Cds in the dummy cell D-CEL has one electrode, a dielectric layer and another electrode, that are, respectively, made up of a first polycrystalline silicon layer 15, a gate insulating film 3 and an n-type surface inverted layer 16. Namely, the power-supply voltage VCC applied to the first polycrystalline silicon layer 15 induces the n-type surface inverted layer 16 on the surface of the p-type semiconductor substrate 1 via the gate insulating film 3 owing to the effect of the electric field.

[Construction of a portion of a peripheral circuit (active restore AR,)] Fig. 6 is a perspective section view showing the construction of a portion of the peripheral circuit formed in the periphery of the memory array WARY, i.e., showing a portion of the active restore AR, which is shown in Fig. 2. In Fig. 6, reference numerals 20 to 23 denote n±type semiconductor regions, 24 to 27 denote second polycrystalline silicon layers, and 28 denotes an aluminum layer. Reference numerals 32 to 35 denote molybdenum silcide layers, and 39 to 42 denote molybdenum layers.

A MISFET QS6 in the active restore AR, shown in Fig. 2 has a substrate, a source region, a drain region, a gate insulating film and a gate electrode, that are, respectively, made up of a p-type 110 semiconductor substrate 1, an n±type semiconductor region 20, an n±type semiconductor region 2 1, a gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 24, a molybdenum silicide layer 32 and a molybdenum layer 39.

A MISFET QS4 in the active restore AR, has a substrate, a source region, a drain region, a gate insulating film and a gate electrode, that are, respectively, made up of a p-type semiconductor substrate 1, an n1-type semiconductor region 22, an n1-type semiconductor region 23, a gate insulating film 3, and a multi-layer electrode consisting of a second polycrystalline silicon layer 27, a molybdenum silicide layer 35 and a molybdenum layer 42. The multi- layer electrode 125 is served with an active restore control signal Org which is shown in Fig. 2.

A capacitor C.11 in th active restore AR, has a dielectric layer and an electrode that are, respectively, made up of the gate insulating film 3 and a multi-layer electrode consisting of a second polycrystalline silicon layer 25, a molybdenum silicide layer 33 and a molybdenum layer 40. The multi-layer electrode is connected to a multi- layer electrode which serves as a gate electrode of the MISFETQ S6 and which consists of a second polycrystalline silicon layer 24, a molybdenum silicide layer 32 and a molybdenum layer 39. Further, a portion 25a of the second polycrystalline silicon layer 25 is directly connected to the nl-type semiconductor region 22 of the MISFET QS4, This is because, if the molybdenum layer 40 and the ri--type semiconductor region 22 are connected together via an aluminum wiring layer, a contact area must be formed between the molybdenum layer 40 and the aluminum wiring layer and makes it difficult to increase the wiring density. Therefore, the above- mentioned connection means is employed to incre ase the wiring density.

Another electrode of the capacitor C B11 consists of an inverted layer which is formed on the surface of the semiconductor substrate 1. The inverted layer is established by a voltage which is applied to the multilayer electrode consisting of the second polycrystalline silicon layer 25, a molybdenum silicide layer 33 and a molybdenum layer 40. Although not diagrammed in Fig. 6, the inverted layer is contiguous with the n±type semiconductor region which is formed in the semiconductor substrate 1 and which is served with an active restore control signal Ors of Fig. 2. Further, as an electrode of the capacitor C,311, there may exist a molybdenum silicide layer and a molybdenum layer on the polycrystalline silicon layer.

The multi-layer electrode consisting of a second polycrystalline silicon layer 26, a molybdenum silicide layer 34 and a molybdenum layer 4 1, serves as one electrode of the capacitor CB12 which is shown in Fig. 2, and a portion thereof is directly connected to the source region of the MISFET Qs5 of Rig. 2 like the camcltor C,,,,,and another portion thereof is connected to the gate electrode of the MISFET Qs,.

[Lay-out patterns of memory array WART and dummy array D-ARY1 Lay-out patterns of the aforementioned memory array WARY and the dummy array ARY are described below with reference to Fig. 7.

The memory array WARY shown in Fig. 7 has a plurality of memory cells MCEL shown in Fig. 4, which are arrayed on the semiconductor substrate 1. On the other hand, the dummy array D-ARY shown in Fig. 7A has a plurality of dummy cells DCEL of Fig. 5, which are arrayed on the semiconductor substrate 1.

First, the memory array WARY shown in Fig. 7 is constructed as mentioned below. The field insulating film 2 is formed described a pattern as shown in Fig.

8 in order to separate a plurality of memory cells M-CEL which are

6 GB 2 134 706 A 6 composed of MISFETs Q, and memory capacitors C. on the surface of the semiconductor substrate 1.

Exceptionally, however, in the present embodiment a field insulating film 2A is formed beneath the contact holes CHO through which the power-supply voltage Vcc is applied to the first polycrystalline silicon layer 6.

This is different from the general rule of such layouts. Therefore, no aluminum-silicon alloy formed by the reaction between the aluminum layer and the polycrystalline silicon layer in the vicinity of the contact holes CHO is allowed to penetrate through the insulation film beneath the contact holes CH, and is prevented from 80 reaching the surface of the semiconductor substrate 1.

The first polycrystalline silicon layer 6 which serves as one electrode of the memory capacitor C., in the memory cells M-CEI is formed on the field insulating film 2 and on the gate insulating film 3 describing a pattern as shown in Fig. 9.

Further, word lines WI-1-1 composed of multi layer wiring of the second polycrystalline silicon layer 8, the molybdenum silicide layer 29 and the molybdenum layer 36 of Fig. 4, stretch on the first polycrystalline silicon layer 6 in the vertical direction in Fig. 7.

A power-supply line Vcc-L runs in the lateral direction of Fig. 7 to supply power-supply voltage 95 Vcc through the contact hole CHO to the polycrystalline silicon layer 6 which serves as one electrode of the memory capacitor C On the other hand, data lines DI-1-1, DI-1-1 composed of the aluminum layer 10 of Fig. 4 run nearly in parallel with the power-supply line Vcc-L 100 as shown in Fig. 7. The data line DLj-, is connected to the drain regions of the MISFETs memory cell M-CEL via a contact hole CH1, and the data line 15-Ll-l is connected to the drain region of MISFET QM in another memory cell MCEL via a contact hole CH 2. Further, the data lines DI-1-2, DI-1-2 run in the lateral direction in Fig. 7 like the data lines DI-1-1 and ITL1-1, and are connected to the drain regionssof the MISFETs Q. in the memory cells M-CEL at predetermined portions through contact holes.

Next, the dummy cells D-CEL shown in Fig. 7 are constructed as mentioned below.

The field insulating film 2 is formed on a portion of the surface of the semiconductor substrate 1, and the gate insulating film 3 is formed on another portion on the surface of the semiconductor substrate 1.

The first polycrystalline silicon layers 1 5a, 1 5b run on the field insulating film 2 and the gate insulating film 3 in the vertical direction of Fig. 7 being separated away from each other. The widths of the first polycrystalline silicon layers 1 5a, 1 5b are very important from the standpoint of determining the capacity of capacitor Cds in the dummy cell D-CEL. The n±type semiconductor region 14 is positioned between the first polycrystalline silicon layer 1 5a and the first polycrystalline silicon layer 1 5b. The n1-type semiconductor region 14 is used as a common earth line for a plurality of dummy cells D-CEL.

Further, a dummy word line DWL1_1 composed of a multilayer wiring of the secondary polycrystalline silicon layer 17, the molybdenum silicide layer 30 and the molybdenum layer 37 of Fig. 5, runs on the first polycrystalline silicon layer 15a. The dummy word line DWL,-, constitutes a gate electrode of MISFET QD1 in the dummy cell D-CEL. On the other hand, a control signal line OdCL, of a multi-layer wiring composed of the second polycrystalline silicon layer 18, the molybdenum silicide layer 31 and the molybdenum layer 38 of Fig. 5, runs in parallel with the dummy word line DWI-1-1 being separated away therefrom, so that the discharge control signal Odc shown in Fig. 5A can be applied. The control signal line Od,-L2 forms a gate electrode of MISFET QD2 in the dummy cell D- CEL.

Similarly, a dummy word line DWL,-2 and a control signal line Odc7L2 run in parallel with the dummy word line DWL,-, and the control signal line 0dr-1-1.

_Further, the data lines DL,-,, DL,-,, DL 1-21 DL1-2 composed of aluminum layer stretch from the memory array WARY as shown in Fig. 7. The data line UL-1-1 is connected to the drain region of MISFET ON in the dummy cell D-CEL via a contact hole CH., and the data line DL,-2 is also connected to the drain region of MISFET QD1 Of another dummy cell D-CEL through a contact hole CH4 [Lay-out pattern of peripheral circuits] Fig. 10 shows a lay-out pattern of a portion of the peripheral circuits, for example, a portion of the sense amplifier SA, of Fig. 2.

In Fig. 10, AR denotes an active restore portion, and PC denotes a circuit for precharging 105 the data lines.

Two active restores AR, shown in Fig. 2 are provided in the active restore portion AR. Namely, one active restore is formed on the side of arrow A in Fig. 10, and another active restore is formed on the side of arrow B. An active restore control signal line O,g-L consisting of a polycrystalline silicon layer, a molybdenum silicide layer and a pure molybdenum layer, a line 0,s-L consisting of an aluminum layer, and a power-supply line VCC-L consisting of an aluminum layer, are arrayed in common for the active restores in the active restore portion AR as shown in Fig. 10.

On the other hand, the precharging circuit PC contains a circuit for precharging the two data lines that correspond to the two active restores. In the precharging circuit PC are arrayed a potential line VDp-L composed of an aluminum layer, a precharge control signal line opc7L, and data lines DL,-,, 51-1- 1, DI-1-2, UL1-2 composed of an aluminum layer which run on the mdmory array WARY of Fig. 2, as shown in Fig. 10.

MISFETs Q., to QS7 and capacitors CB111 C812 of Fig. 2 are arrayed as shown in Fig. 10.

Next, a process for producing an n-channel D- 7 GB 2 134 706 A 7 RAM will be described below with reference to Figs. 11 A to 11 S. In each of the drawings, X, stands for a section view of the memory array MARY of Fig. 7 along X,-X,, X2 stands for a section view of the active restore AR of Fig. 10 along XX2, and X3 stands for a section view of the active restore AR of Fig. 10 along X,-X,.

(Step for forming an oxide film and an oxidation-resistant film) As shown in Fig. 11 A, an oxide film 102 and an insulating film, i.e., an oxidation-resistant film 103 which does not permit the passage of oxygen, are 75 formed on the surface of a semiconductor substrate 10 1.

A p-type single crystalline silicon (Si) substrate having a crystalline plane (100), a silicon dioxide (SiO.) film and a silicon nitride (S'3N4) film are preferably used for forming the semiconductor substrate 101, the oxide film 102 and the oxidation-resistant film 103.

The S'02 film 102 is formed by the surface oxidation of the silicon substrate 10 1 to a thickness of about 500 angstroms, because of the 85 reasons mentioned below. That is, when the S'3N4 film 103 is formed directly on the surface of the silicion substrate 10 1, the surface of the silicon substrate 101 tends to be thermally distorted due to the difference in the thermal expansion coefficient between the silicon substrate 10 1 and 90 the S'3 N 4 film 103. Consequently, crystalline defect is given to the surface of the silicon substrate 10 1. In order to prevent this defect, the SiO 2 film 102 is formed on the surface of the silicon substrate 10 1 prior to forming the SO, film 103.

On the other hand, the S'3N4 film 103 which will be used as a mask for selective oxidation of the silicon substrate 10 1, is formed to a thickness of about 1400 angstroms by the CVD (chemical vapor deposition) method, as will be mentioned later in detail.

(Step for selectively removing oxidation- resistant film and for injecting ions) A photoresist film 104 which serves as an etching mask is selectively formed on the surface of the S'3N4 film 103 that is to be selectively removed from the surface of the silicon substrate 101 on which will be formed a relatively thick insulating film, i.e., a field insulating film. Under this condition, the exposed portions of-the SiN4 film 103 are removed by the plasma etching method which features good etching precision.

Then, impurities of the same type of conductivity as the substrate 10 1, i.e., p-type impurities are introduced into the silicon substrate 115 10 1 through the S'02 film 102 that is exposed at portions which are not covered with the photoresist film 104 as shown in Fig. 11 B, so that a so-called inverted layer of the type of conductivity opposite to that of the substrate will 120 not be formed on the surface of the substrate 10 1 on which the field insulating film is formed. The ptype impurities can be introduced preferably by the ion-injection method. For example, boron ions which are p-type impurities can be injected into the silicon substrate 101 at an injection energy of 75 KeV. In this case, the dosage of ions will be 3x 1012 atoMS/CM2.

(Steps for forming field insulating film)

A field insulating film 105 is selectively formed on the surface of the silicon substrate 10 1.

Namely, after the photoresist film 104 is removed, the surface of the silicon substrate 10 1 is selectvely oxidized by thermal oxidation using the Si3N4 film 103 as a mask, to form the the S'02 film 105 (hereinafter referred to as a field S'02 film) of a thickness of about 9500 angstroms, as shown in Fig. 11 C. When the field S'02 film 105 is being formed, the injected boron ions diffuse into the silicon substrate 101, thereby to form a p-type inversion preventing layer (not shown) of a predetermined depth beneath the field S'02 film 105.

(Step for removing oxidation-resistant film and oxide film) The S'3N4 film 103 is removed using, for example, a hot phosphoric acid (1-13pod solution in order to expose the surface of the silicon substrate 10 1 of the portions where the field SiO 2 film 105 is not formed. Then, the SiO2 film 102 is removed by using a hydrofluoric acid (HF) solution, so that the surface of the silicon substrate 10 1 is selectively exposed as show in Fig. 11 D.

(Step for forming a first gate insulating film) A first gate insulating film 106 is formed on the exposed surfaces of the silicon substrate 10 1 as shown in Fig. 11 E in order to form a dielectric layer for the capacitors C, Dds in the memory cells M-CEL and in the dummy cells D-CEL. Namely, the surface of the exposed silicon substrate 10 1 is thermally oxidized to form the first gate insulating film 106 having a thickness of about 430 angstroms on the surface of the silicon substrate 101. Therefore, the first gate insulating film 106 consists of S'02 (Step for adhering a first conductor layer) A first conductor layer 107 is formed on the whole surface of the silicon substrate 10 1 as shown in Fig. 11 F so that it can be used as one electrode of capacitors in the memory cells and in the dummy cells. Namely, a polycrystalline silicon layer 107 which serves as the first conductor layer is formed on the whole surface of the silicon substrate 10 1 by the CVD method. The polycrystalline silicon layer 107 has a thickness of about 400 angstroms. Then, in order to reduce the resistance of the polycrystalline silicon layer 107, n-type impurities, such as phosphorus ions, are introduced into the polycrystalline silicon layer 107 by the diffusion method. Therefore, the polycrystalline silicon layer 107 possesses a resistivity of about 16 ohMS/CM2.

8 GB 2 134 706 A 8 (Step for selectively removing the first conductor layer) In order to form the first conductor layer, i.e., the first polycrystalline silicon layer 107 into electrodes of a predetermined shape, the first polycrystalline silicon layer 107 is selectively removed by the photoetching method as shown in Fig. 11 G, thereby to form electrodes 108. The first polycrystalline silicon layer 107 can be selectively removed by plasma etching which features good etching precision. Therefore, the exposed first S'02 gate film 106 is subjected to etching, so that surfaces of the silicon substrate 101 are partially exposed.

(Step for forming a second gate insulating film) A second gate insulating film 109 is formed on the exposed surface of the silicon substrate 10 1 as shown in Fig. 11 H in order to obtain a gate insulating film for the MISFET's in the memory cells M-CEL, dummy cells D-CEL, and in the peripheral circuits. Namely, the exposed surface of the silicon substrate 10 1 is thermally oxidized to form an second gate insulating film 109 of a thickness of about 530 angstroms on the surface of the silicon substrate 101. Therefore, the second gate insulating film 109 consists of S'02' The surface of the electrodes 108 composed of the first polycrystalline silicon is also oxidized simultaneously with the formation of the second gate insulating film, i.e., simultaneously with the formation of the second S'02 gate film 109; an S'02 film 110 having a thickness of about 2200 angstroms is formed on the surface of the electrodes 108. The S'02 film 110 serves as an insulating layer between the electrodes 108 and the electrodes composed of a second polycrystalline silicon that will be mentioned later.

(Step for injecting ions for controlling low 100 threshold voltage) P-type impurities are introduced into the surface of the substrate through the second SiO 2 gate film 109 by the ion-injection method as shown in Fig. 111 in order to define a threshold voltage of MISFETs Qsl to QS3. QS6 and QS7 which are shown in Fig. 2 and which have a low threshold voltage. Boron ions will be used as the p-type impurities. The energy for injection will be KeV, and the dosage of ions will preferably be 110 2.4x 1011 atoms/CM2.

In this case, ions are injected without using a selection mask. Therefore, boron ions are also introduced into the surfaces of the substrate where other MISFET's are to be formed, such as QM'QD1' QD21 QD4, QD5' (Step for injecting ions for controlling high threshold voltage) A mask for ion injection, i.e., a photoresist film 111 is formed on the second S'02 gate film 109 on the channel regions of MISFET Qs, to QS31 QS6 and Q S7 as shown in Fig. 11 J, and boron ions are injected under this condition in order to define a threshold voltage of MISFET's having a threshold voltage greater than that of MISFETs Qsl to QS31 QS6 and QS7 shown in Fig. 2, i.e., in order to define a threshold voltage of MISFET QM in the memory cells, MISFETs QD11 QD2 in the dummy cells, and MISFETs QS41 Qs5 in the active restores. The injection energy will be 75 KeV, and a preferred dosage of ions will be 1.Ox 1011 atoMS/CM2.

Consequently, the impurity concentration is further increased in the surface of the portions of the substrate where MISFETs QM1 QD11 QD21 QS1 and QS5 are to be formed. Therefore, these MISFET's have a high threshold value.

(Step for forming holes for direct contact) Holes for directly connecting one electrode 25 of the capacitor C,,,, to the n+type semiconductor region 22 of MISFET Q. 4 as mentioned with reference to Fig. 6 are formed, i.e., so-called direct contract holes CH,,,are formed by selectively etching the second S'02 gate film using the photoresist film 112 as a mask, as shown in Fig. 11 K.

(Step for adhering a second conductive layer) A second conductive layer is formed on the whole surface of the silicon substrate 101 so that it can be used as a gate electrode and a wiring layer for all of the MISFET's. Namely, a polycrystalline silicon layer, a silicide layer of silicon and a refractory metal, and a pure refractory metal layer are formed as a second conductive layer, as shown in Fig. 11 L. First, a polycrystalline silicon layer 113 is formed on the whole surface of the silicon substrate 101 by the CVD method (chemical vapor deposition method). The polycrystalline silicon layer 113 has a thickness of about 1500 to 2500 angstroms. Then, n-type impurities such as phosphorus ions are introduced into the polycrystalline silicon layer 113 by the diffusion method, in order to decrease the resistance. Some of the phosphorus ions are introduced into the silicon substrate 10 1 through direct contact holes CH100 Therefore, there is no need of forming high-concentration regions for ohmic contact.

Then, a silicide layer 128 of silicon and a refractory metal is formed on the whole surface of the polycrystalline silicon layer 113. Molybdenum will be used as the refractory metal " Molybdenum and silicon are deposited on the polycrystalline silicon layer by the co-sputtering method in order to form a mixed layer of silicon and molybdenum. The silicon content will be, for example, 10% by weight. The sputtering conditions will consist of a vacuum degree of smaller than 40,uPa before argon gas is introduced, an argon-gas pressure of 4.0 Pa when the sputtering is being effected, a molybdenum deposition rate of 0.1 to 0.8 nm/sec., and a silicon deposition rate of 0.1 nm/sec or less. The molybdenum silicide layer 128 consisting of silicon and molybdenum has a thickness of about 1000 angstroms.

A pure refractory metal layer 130 is then formed on the whole surface of the molybdenum 9 GB 2 134 706 A 9 silicide layer 128. Molybdenum will be used as the refractory metal. The sputtering method is used for forming the refractory metal layer. In this case, the sputtering is effected under the same conditions as above. The molybdenum layer has a thickness of about 1500 angstroms.

(Step for selectively removing the second conductive layer) The second conductive layer, i.e., the second polycrystalline silicon layer 113, molybdenum silicide layer 128 and the molybdenum layer 130 are selectively removed to form predetermined electrodes or wirings by the dry-etching method using a photoresist. A gas consisting, for example, of C174+02 is used as an etching gas. The above- mentioned three layers are removed by etching (plasma etching) or by plasma discharge in the presence of the gas. First, the molybdenum layer is subjected to the etching, the molybdenum silicide layer is subjected to the etching next, and the polycrystalline silicon layer is subjected to the etching maintaining the same shape in the presence of the same gas. Then, the annealing is effected in an nitrogen atmosphere. Owing to the annealing, molybdenum and silicon are uniformly dispersed in the molybdenum silicide layer 129. The polycrystalline silicon layer 114, the molybdenum silicide layer 129, and the molybdenum layer 13 1, that are formed in the shapes as shown in Fig. 11 M by the plasma etching, form word lines WL1_, to WL1__6, dummy word lines DWL1_1, DWL -2, and control signal lines od.-Li, 0d,,-L21 which are shown in Fig. 7, and further form active restore control signal line Org-L, electrode 114 for the capacitors C13111 CB12, and gate electrodes for the MISFET Qsl and QS21 which are shown in Fig. 10. In Fig. 11 M, furthermore, the exposed second S'02 gate film 109 is removed, to expose the surface of the silicon substrate 10 1.

(Step for oxidizing the surface) An S'02 f" M 115 of a thickness of about 100 angstroms is formed by the chemical vapor deposition (CVD) method on the surface of the exposed silicon substrate 10 1, as shown in Fig.

11 N, so that the surfaces where source regions and drain regions of MISFET's are to be formed, will not be contaminated. Simultaneously with the formation of the S'02 film 115, an S'02 film 116 having a thickness of about 100 angstroms is also formed by the CVD method, as shown in Fig. 11 N, on the surfaces of word lines WL1_1 to WL1-6, dummy word lines DWL,-,, IDWIL1-2.

control signal lines 0dc7L1, Odc-1-2, electrode 114 of the capacitors CB111 CB12, and gate electrodes of MISFETs Qsl to QS31 which consist of the second polycrystalline silicon layer 113, molybdenum silicide layer 128 and molybdenum layer 130.

In forming the S'02 films 115 and 116, the following measure is taken in order to prevent the molybdenum layer 114 from being oxidized and sublimated.

First, the semiconductor substrate 10 1 is set 125 into a device for forming the S'02 film by the CVD method. In this case, the temperature in the device is lower than 2000C. Then, nitrogen gas is allowed to flow sufficiently so that no oxygen is present in the device. Then, the S'02 film is formed by elevating the temperature in the device to about 4000 to 4501C. Concretely speaking, SiH4+02 is allowed to flow with the nitrogen gas as a carrier gas; the SiH4+02 gas is thermally decomposed and is reacted. Oxygen introduced at this moment does not react with molybdenum but reacts with silicon to form an SiO, film on the surface of the substrate.

(Step for forming source and drain regions) N-type impurities such as arsenic ions are introduced into the silicon substrate 10 1 through the S'02 film 115, as shown in Fig. 110, in order to selectively form source and drain regions of MISFET's in the silicon substrate 10 1. The n- type impurities can be introduced preferably by the ion-injection method. For example, arsenic ions are injected into the silicon substrate 10 1 at an injection energy of 80 KeV. In this case, the dosage of ions will be 1 X1016 atorns/CM2.

(Step for forming contact holes) Contact holes are formed in the S'02 film to connect the source and drain regions to the third conductive layer. Namely, contact holes CHl., to CH 104 are formed as shown in Fig. 11 P by selectively etching the S'02 film 115 using a predetermined mask. Here, the contact hole CH102 corresponds to the contact hole CH, of Fig. 7.

(Step for forming interlayer insulating film) An interlayer insulating film is formed on the whole surface of the silicon substrate 101. That is, an interlayer insulating film 118, for example, a phosphorus silicate glass (PSG) film having a thickness of about 8000 angstroms is formed on the whole surface of the silicon substrate 101, as shown in Fig. 11 Q. The PSG film 118 also serves as a sodium ion getter which affects the characteristics of MISFET's.

(Step for forming contact holes) Contact holes are formed in the PSG film 118 in order to connect the second polycrystalline silicon layer to the third conductive layer, and the source and drain regions to the third conductive layer. That is, the PSG film 118 is subjected to the selective etching to form contact holes CH101 to CH104, as shown in Fig. 11 R. The mask used for forming the contact holes CH101 to CH104 is the same as the mask used for forming the contact holes CH101 to CH104 in the aforementioned step for forming contact holes.

Therefore, the PSG film 118 is thermally treated at a temperature of about I OOOOC in order to flatten it. Arsenic ions injected through the heat treatment are diffused to form n±type semiconductor regions 119 to 126 having a predetermined depth. The n--type semiconductor regions 119 to 126 serve as source and drain regions.

GB 2 134 706 A 10 Here, the contact holes formed in the S'02 film in the aforementioned step, may be formed simultaneously with the formation of contact holes in the PSG film 118. However, the PSG film 118 is subjected to the etching before the contact holes are completely formed in the Si02 film 115 In other words, the PSG film 118 is subjected to over-etching. In order to prevent the over-etching, therefore, the contact holes should be formed in the PSG film 118 through a step different from the step for forming the contact holes in the S'02 film 115.

(Step for forming a third conductive layer) A third conductive layer, for example, an aluminum layer having a thickness of about 80 12000 angstroms is formed on the whole surface of the silicon substrate 10 1, in order to form the power-supply line V.

c7L, and data lines DL1_1, DL1_1, DI-1-2, and DL1-2. that are shown in Fig. 7.

The aluminum layer is then subjected to the selective etching to form a power-supply line Vcc-L, data line DL1_1 and wiring layer 127, as shown in Fig. 11 S.

According to the above-mentioned embodiment of the present invention, it is 90 possible to realize a D-RAM IC, i.e., a semiconductor integrated circuit device having a wiring layer of a small resistivity and fast signal transmission speed. Further, the effects (1) to (3) obtained in the first embodiment can also be equally obtained by this embodiment. According to this embodiment, in particular, the first conductive layer consists of polycrystalline silicon.

However, since the first conductive layer is always impressed with a predetermined voltage or is grounded, there arises no problem even when it has a high resistivity. Rather, the first conductive layer composed of polycrystalline silicon makes it possible to form a dense insulating film (SiO 2 f" M) by thermally oxidizing the surface thereof.

According to the embodiment of the present 105 invention, furthermore, a semiconductor integrated circuit device having the abovementioned effects can be obtained without passing through complicated manufacturing steps. Namely, according to the embodiment of 110 the present invention, the wiring layer consisting of polycrystalline silicon layer 114, molybdenum silicide layer 129 formed on the layer 114, and molybdenum layer 131 formed on the layer 129, serves as an electrode that comes into direct contact with the n'-type semiconductor region 22, serves as a gate electrode for MISFET's, and serves as one electrode of MIS capacitors. When the individual electrodes are to be formed using separate materials, i.e., when the electrode that 120 comes into direct contact with the semiconductor region, gate electrode of MISFET's, and one electrode of MIS capacitors, are to be formed using separate materials, increased number of manufacturing steps will be necessary.

Further, simultaneous formation of one electrode of MIS capacitors and the electrode that comes into contact with the semiconductor region 22, helps increase the degree of integration. That is, if these electrodes are made of different materials, a contact area must be provided between the two electrodes. Therefore, the above-mentioned manufacturing steps are effective to increase the density of wiring. The molybdenum silicide layer which serves as one electrode of MIS capacitors presents no problem.

The present invention should in no way be limited to the above-mentioned embodiment only.

For example, in addition to using molybdenum silicide (MoSi), it is also allowable to use titanium silicide (TiSi,), tantalum silicide (TaSi) or tungsten silicide (WSi) as a second conductive layer for forming multilayer wiring.

In addition to molybdenum, furthermore, it is also allowable to use titanium, tantalum or tungsten as a refractory metal.

Furthermore, the steps of Figs. 11 L to 110 in the above-mentioned embodiment can be rearranged as mentioned below. First, the polycrystalline silicon layer 113, the silicide layer 128 of silicon and refractory metal, and the pure refractory metal layer 131 are laminted in the order mentioned on the S'02 gate film 109 and on the S'02 field film 105, as shown in Fig. 11 L. Then, the above-mentioned three layers are selectively removed by dry etching to form a wiring layer or gate electrode. Source and drain regions are then formed beneath the S'02 gate film 109 using the wiring layer as a mask. These regions are formed by the ion implantation method.

According to the present embodiments, therefore, it is possible to obtain semiconductor integrated circuit devices having a high density which resu Its from the self-matching property, and having a wiring layer with small resistivity and short signal transmission time.

Claims

1. A method of fabricating a semiconductor memory device including a memory cell array having a plurality of memory cells formed on a semiconductor substrate wherein each of said memory cells has a capacitor and an MIS-type field effect transistor and wherein each of said memory cells is coupled to at least one of a plurality of word lines and coupled to at least one of a plurality of data lines, and a peripheral circuit formed on said semiconductor substrate wherein said peripheral circuit is associated with said memory cell array and wherein said peripheral circuit is constructed of a plurality of MIS-type field effect transistors and interconnecting lines at least one of which is contacted with one semiconductor region of one of said MIS-type field effect transistors, comprising the steps of:

forming a first layer of polycrystalline silicon over substantially the entire area of one main surface of a semiconductor substrate, said first layer having portions overlying first insulating films formed on selected first areas of said main surface in which said capacitors are to be formed; iR 1 11 GB 2 134 706 A 11 patterning said first layer to form one electrode of each of said capacitors in each first area; forming a second layer of polycrystalline silicon 50 over substantially the entire area of said main surface, said second layer extending over an insulating film formed on said patterned first layer of polycrystalline silicon and extending on gate insulating films formed on selected second areas of said main surface in which said MIS-type field effect transistors for said memory cells and peripheral circuit are to be formed, said second layer having a portion which is contacted with a portion of one of said second areas; forming over said second layer a third layer which is composed of a refractory metal; and patterning said successive second and third layers to form gate electrodes of said IVIIS type field effect transistors and said word lines and to form said interconnecting lines at least one of which is contacted with the portion of said second area serving as said semiconductor region of said MIS-type field effect transistor.

2. A method of fabricating a semiconductor memory device according to claim 1, wherein said step of forming said second layer includes a step of introducing impurities of the same conductivity type as said semiconductor region of said MIStype field effect transistor into said second layer.

3. A method of fabricating a semiconductor memory device according to claim 1 or 2, wherein said step of forming said third layer includes a step of forming a lower layer of a refractory metal containing silicon on said second layer of polycrystalline silicon, and a step of forming an upper layer of a refractory metal on said lower layer. 40

4. A method of fabricating a semiconductor memory device according to any one of claims 1 to 3, wherein said refractory metal is molybdenum.

5. A method of fabricating a semiconductor memory device according to any one of claims 1 to 4, wherein said data lines are formed by patterning a metal layer which is formed over an insulating film covering said word lines.

6. A method of fabricating a semiconductor memory device according to claim 5, wherein said metal layer is made of aluminum.

7. A semiconductor memory device including a memory cell array having a plurality of memory cells formed on a semiconductor substrate wherein each of said memory cells has a capacitor and an M IS-type field effect transistor and wherein each of said memory cells is coupled to at least one of a plurality of word lines and coupled to at least one of a plurality of data lines, and a peripheral circuit formed on said semiconductor substrate wherein said peripheral circuit is associated with said memory cell array and wherein said peripheral circuit is constructed of a plurality of MIS-type field effect transistors and interconnecting lines at least one of which is contacted with one semiconductor region of one of said MIS-type field effect transistors, wherein one electrode of each capacitor is formed by a patterned first layer of polycrystalline silicon, overlying a first insulating film on a first area of the substrate; and wherein the gate electrodes of the MIS-type field effect transistors, the word lines, and the interconnecting lines are formed from a second layer of polycrystalline silicon extending over an insulating film formed on said patterned first layer and over gate insulating films in selected second areas of the substrate, and a third layer of a refractory metal over the second layer.

8. A semiconductor memory device according to claim 7 wherein said third layer includes a lower layer of a refractory metal containing silicon on said second layer, and an upper layer of a refractory metal on said lower layer.

9. A semiconductor memory device according to claim 7 or claim 8 wherein the refractory metal is molybdenum.

10. A semiconductor memory device according to any one of claims 7 to 9 wherein said data lines go comprise a patterned metal layer over an insulating film covering said word lines.

11. A semiconductor memory device according to claim 10 wherein said metal layer is made of aluminum.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1984. Published by the Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.