GB2133622A - An integrated injection logic semiconductor integrated circuit device - Google Patents

An integrated injection logic semiconductor integrated circuit device Download PDF

Info

Publication number
GB2133622A
GB2133622A GB08403188A GB8403188A GB2133622A GB 2133622 A GB2133622 A GB 2133622A GB 08403188 A GB08403188 A GB 08403188A GB 8403188 A GB8403188 A GB 8403188A GB 2133622 A GB2133622 A GB 2133622A
Authority
GB
United Kingdom
Prior art keywords
semiconductor
cross
semiconductor layer
under
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08403188A
Other versions
GB8403188D0 (en
GB2133622B (en
Inventor
Setsuo Ogura
Shizuo Kondoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB8403188D0 publication Critical patent/GB8403188D0/en
Publication of GB2133622A publication Critical patent/GB2133622A/en
Application granted granted Critical
Publication of GB2133622B publication Critical patent/GB2133622B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)

Abstract

An I<2>L device includes a cross- under semiconductor layer 5, and an isolating semiconductor layer 3 formed in a semiconductor region 2, wherein a potential is applied to the isolating layer 3 so that forward bias between the cross-under layer 5 and the isolating layer 3 is prevented. The construction is used in stacked I<2>L integrated circuits comprising blocks of I<2>L devices formed in semiconductor regions having different potentials, and prevents the operation of parasitic transistors (Qp). In stacked I<2>L integrated circuits, isolating layers 3 in I<2>L devices in I<2>L blocks may be maintained at the same potential or may be connected to regions 2 is adjacent I<2>L blocks. <IMAGE>

Description

1
SPECIFICATION
An integrated injection logic semiconductor integrated circuit device GB 2 133 622 A 1 The present invention relates to an integrated injection logic semiconductor integrated circuit device. 5 The number of gates in such devices increases with the increase in the range of uses to which they are put, and the consumption of electric power increases correspondingly.
An integrated injection logic (hereinafter referred to as 12 L) circuit construction which is called stacked 12 L has been employed in order to reduce the power consumption of 12 L circuits which have increased numbers of gates. The stacked 12 L construction consists of a plurality of 12L blocks, each formed of a plurality of 12 L elements that provide a logic structure in an electrically isolated semiconductor region, the 12 L blocks being connected in series between a reference potential (earth potential) and a predetermined supply potential.
In orderto increase the degree offreedom in the wiring layout of stacked 12 L devices and to increase the degree of integration, it is possible to attempt to form many cross-under wirings, which utilize a diffusion layer in the semiconductor.
We have previously proposed cross-under wirings ofthe construction shown in Figure 1 ofthe accompanying drawings for use in stacked 12 L devices. As shown in Figure 1, the cross-under wiring is formed by forming an W-type diffusion wiring layer 5, which crosses an aluminium wiring 4, on a portion of the surface of an N--type silicon substrate 1, with an intermediate P- type diffusion layer 3. The reason for using the N'-type diffusion wiring layer 5 as a cross-under wiring is because the W-type diffusion wiring 20 layer 5 is formed simultaneously with the formation of the collector region (N'-type diffusion layer) of the inverse transistor of an 12 L element, and because the W-type diffusion wiring layer 5 has an impurity concentration greater than that ofthe P-type diffusion layer 3 and, hence, has a low sheet resistance, lending itself well for being used as a cross-under wiring.
In stacked 12 L blocks by utilizing cross-under wirings, and to extend the wiring layer in a given 12L block into 25 other 12 L blocks by detour. With reference to Figure 2, N--type epitaxial layers 2a, 2b and 2c electrically isolated by the P-type isolation layer 6 are used as 12 L blocks having quite different potentials from each other. For instance, in the case of a three-stage stacked 12 L IC shown in Figure 2, the N---typeepitaxial layer 2a has a potential V2b = 0.7 volts, and the N---typeepitaxial layer 2c has a potential V2, = 0 volt. Therefore, when the N'-type diffusion cross-under wiring layers 5a, 5b, 5c are formed in the N-type epitaxial layers 2a,21J,2c, 30 the N'-type diffusion cross-under wiring layers being in contact with the wiring layers that electrically connect the 12 L blocks and being further in contact with the detouring wiring layers, there arises a problem with regard to potentials ofthe P-type diffusion layers 3a, 3b, 3c that are formed to provide PN junctions to electrically isolate the N'-type diffusion cross-under wiring layers from the N--type epitaxial layers 2a,2b,2c.
The cause, it has been found, is that part ofthe cross-under wiring construction serves as a parasitic NPN transistor QP which is made up of N'-type diffusion wiring layer 5, P- type diffusion layer 3 and N--type epitaxial layer 2 as shown in Figure 1. Here, it is supposed that the cross-under wiring construction of Figure 1 exists in an 12 L block (a third stage block) in which the operational voltage ranges from 1.4 volts to 2.1 volts.
That is, it is supposed that the cross-under wiring construction exists in the N--type epitaxial layer 2a shown in Figure 2 of the accompanying drawings. In Figure 1, furthermore, the wiring layer M extends from the second state 12 L block in which the operational voltage lies between 1.4 volts and 0.7 volts (i.e. extends from the 12 L block that exists in the N-type epitaxial layer 2b shown in Figure 2) and connects to the W-type diffusion wiring layer 5. In the above-mentioned cross-under wiring construction, the P-type diffusion layer 3 has a potential of 1.4 volts, which is the same as the potential of the N- -type epitaxial layer 2. When the wiring layer M has a potential of 0.7 volts, therefore, a forward bias is applied to the PN junction J between 45 the N'-type diffusion layer 5 and the P-type diffusion layer 3, and the parasitic NPN transistor Qp operates.
Operation of such a parasitic NPN transistor becomes a problem in a portion wherelhe wiring layer which extends from a low-potential driving 12 L block to a high-potential driving 12 L block, crosses under the diffusion layer in the high-potential driving 12 L block. The action of the parasitic NPN gansistor makes it impossible to properly operate the inverse transistor of an 12 L element that is connected via the cross-under 50 diffusion layer.
According to the present invention there is provided an integrated injection logic semiconductor integrated circuit device including:
(a) first, second and third semiconductor regions that are electrically isolated from each other; (b) a first integrated injection logic block including a plurality of integrated injection logic elements formed 55 in the first semiconductor region; (c) a second integrated injection logic block including a plurality of integrated injection logic elements formed in the second semiconductor region; (d) a third integrated injection logic block including a plurality of integrated injection logic elements 6() formed in the third semiconductor region; (e) first, second and third metal wiring layers formed in said first, second and third integrated injection logic blocks, respectively; (f) a first cross-under semiconductor layerwhich crosses under and is electrically isolated from the first metal wiring layer formed in the first semiconductor region; (g) a second cross-under semiconductor layer which crosses under and is electrically isolated from the 65 2 GB 2 133 622 A 2 second metal wiring layer formed in the second semiconductor region; (h) a third cross-under semiconductor layerwhich crosses under and is electrically isolated from thethird metal wiring layer formed in the third semiconductor region; (i) a first semiconductor layerwhich has a conductivity type oppositeto thatof said first cross-under semiconductor layer, and which is located adjacentto said first cross- under semiconductor iayerto electrically isolate said first cross-under semiconductor layerfrom said first semiconductor region; (j) a second semiconductor layerwhich has a conductivity type opposite to that of said second cross-under semiconductor layer, and which is located adjacentto said second cross-under semiconductor iayerto electrically isolate said second cross-under semiconductor layerfrom said second semiconductor region; and (k) a third semiconductor layerwhich has a conductivity type oppositeto that of said third cross-under semiconductor layer, and which is located adjacentto said third cross-under semiconductor layerto electrically isolate said third cross-under semiconductor layerfrom said third semiconductor region; wherein said first, second and third semiconductor regions are provided with predetermined potentials which are differentfrom each other, and wherein said first, second and third semiconductor layers are provided with predetermined potentials set at levels to prevent a forward bias from being applied across said first cross-under semiconductor layer and said first cross-under semiconductor layer, across said second cross-under semiconductor layer and said second semiconductor layer, or across said third cross-under semiconductor layer and said third semiconductor layer.
The present invention will now be described in greater detail by way of example with reference to the remaining Figures of the accompanying drawings, wherein:
Figure 3 is a d iag ram of a stacked j2 L circuit to which the present invention can be applied; Figure 4 is a sectional view showing a cross-under wiring in an lk block; Figure 5 is a plan view of a stacked 12 L IC according to a first embodiment of the present invention; Figure 6 is a sectional view which corresponds to Figure 5; Figure 7 is a plan view of a stacked 12 L IC according to a second embodiment of the present invention; Figure 8 is a sectional view showing a portion of the cross-under wiring of Figure 7; Figure 9 is a plan view of a stacked 12 L IC according to a third embodiment of the present invention; and Figure 10 is a plan view showing a portion of the cross-under wiring according to a further embodiment of the present invention.
Figure 3 shows a portion of the stacked 12 L circuit, and illstrates 12 L blocks of the n-th stage, (n-1)th stage, and the first stage, as well as the manner in which they are interconnected. In Figure 3, thick solid lines represent metal wiring layers for connecting 1 2 L elements with the 12 L blocks and for connecting the 12 L blocks. Resistors R1,R3 equivalently demonstrate cross-under wiring layers (diffusion layers) formed in a semiconductor integrated circuit device. A resistor R2 has a resistance greater than those of the resistors R1,R3, works to shift the level and to properly operate the transistor Q of the (n-1)th stage, and further works as a cross-under wiring.
The 12 L block in each stage has been independently formed in an W-type epitaxial semiconductor layer 2 which is electrically isolated from its counterparts by a P-type semiconductor substrate 1 and a P-type isolation layer 6, as shown in Figure 4. That is P-type semiconductor layers 7,8, and W-type semiconductor 40 layers 9,10 are selectively formed in the isolated W-type epitaxial semiconductor layer 2. The P-type semiconductor layer 7 serves as an injector region, i.e. serves as an emitter of a lateral PNP transistor, the W-type epitaxial semiconductor layer 2 serves as a base of the transistor, and the P-type semiconductor layer 8 serves as a collector of the transistor. Moreover, the W-tpe epitaxial semiconductor layer 2 serves as an emitter of an inverse NPN transistor, the P-type semiconductor layer 8 serves as a base of the transistor, and the N'-type semiconductor layer 9 serves as a collector of the transistor. Thus, an 12 L element (a circuit element having a logic function) is constructed. Therefore, a plurality of the thus constructed 12 L elements are formed in each of the epitaxial semiconductor layers that are isolated from each other, to constitute the individual 12 L blocks.
In Figure 4, the N'-type semiconductor layer 5 formed in the P-type semiconductor layer 3 serves as a 50 z diffusion resistance for shifting the level, which also serves as a cross- under wiring, as mentioned above, and forms a resistor R2 as shown in Figure 3.
In accordance with the present invention, the stacked j2 L circuit is formed in a semiconductor substrate as illustrated in the following embodiments.
z z Embodiment 1 Figure 5 illustrates a stacked 12 L IC in which the P-type layers 3a, 3b and 3c are connected to a minimum potential or to ground potential (GND) in order to isolate cross-under wiring layers (N'-type layers) 5a, 5b and 5c from the W-type epitaxial layers 2a, 2b and 2c.
The stacked 12 L IC of Figure 5 consists of j2 L blocks in three stages. In this case, potentials of the W-type epitaxial layers in the j2 L block of the n-th stage (third stage), 12 L block of the (n-1)th stage (second stage) and 12 L block of the first stage, are held at 1.4 volts, 0.7 volts and 0 volt, respectively. In each of the 12 L blocks as will be obvious from Figure 5, furthermore, potentials of the P-type layers 3a,3b,3c where cross-under wiring layers 5a,5b,5c are formed under the metal wiring layers (aluminum layers) La,Lb,Lc, are maintained at a minimum potential, i.e. maintained at ground potential (0 volt) being connected through wirings 65 Z 3 GB 2 133 622 A 3 I 'I a, l 'I b,l l c. This makes it possible to prevent the parasitic transistor operation that will be established by the cross-under wiring layers (N±type layers) which have a high potential, the P-type layers and the W-type epitaxial layers. That is, a metal wiring layer M, which extends from the 12 L block of the (n 1)th stage is connected to the cross-under wiring layer 5a. Accordingly the cross-under wiring layer 5a has applied to it a potential (0.7 volts to 1.4 volts) which is higher than the potential (0 volt) of the P-type layer 3a. Therefore, a reverse bias is applied across the cross-under wiring layer 5a and the P-type layer 3a, and no parasitic transistor operation takes place at the position of the cross-under wiring layer 5a. Further, a metal wiring layer M2 extending from the 12 L block of the n-th stage is connected to the cross-under wiring layer 5b. Therefore, the cross-under wiring layer 5b has applied to it a potential (1.4 volts to 2.1 volts) which is higher than the potential (0 volt) of the P-type layer 3b. Consequently, a reverse bias is applied across the cross-under wiring layer 5b and the P- type layer 3b, so that no parasitic transistor operation takes place at the position of the cross-under wiring layer 5b. Furthermore, a metal wiring layer M3 in the 12 L block of the first stage is connected to a cross-under wiring layer 5c. Therefore, the cross-under wiring layer 5c has applied to it a potential (0.7 volts) which is equal to, or greater than, the potential (0 volt) of the P-type layer 3c. Accordingly, no forward bias is ever applied across the cross-under wiring layer 5c and the P-type layer 15 As mentioned above, no forward bias is applied across the cross-under wiring layers 5a,5b,5c and the P-type regions 3a,3b,3c, and, hence, no parasitic transistor operation takes place. Figure 6 is a sectional view which schematically illustrates the wiring circuit of Figure 5.
According to the above-mentioned embodiment, the P-type layers 3a,3b and 3c are maintained at ground 20 potential in order to prevent the occurrence of parasitic transistor operation. Therefore, the number of metal wiring layers connected to the P-type layers increases, resulting in a decrease in the degree of integration of the semiconductor integrated circuit device.
In preventing the occurrence of parasitic transistor operation, it will be understood that the P-type layers in the 12 L blocks need not necessarily be maintained at a minimum voltage, provided the wiring layers 25 extending from the low-potential driving j2 L blocks to the highpotential driving j2 L blocks, do not cross under the metal wiring layers in the high-potential driving 12 L blocks. The following embodiment is to realize a semiconductor integrated circuit device which is constructed in a highly integrated form compared with the above-mentioned embodiment 1, by taking this point into consideration.
Embodiment2 Figure 7 illustrates a stacked j2 L IC in which the P-type regions 3a,3b, 3c where cross-under wiring layers (N'-type layers) 5a,5b,5c of each of the blocks are formed, have potentials that are setto be equal to the potentials of the W-type epitaxial layers 2a,2b,2c.
In Figure 7, P-type layers 3a,3b,3c are electrically connected to the Wtype epitaxial layers 2a,2b,2c by metal wiring layers (aluminum layers) 12a,12b,12c, respectively. In practice, each of the metal wiring layers 12a,12b,12c is formed on an N'-type layer 5'which electrically connects the W-type epitaxial layer 2 to the P-type layer 3, like a metal wiring layer (electrode) 12 of Figure 8, in which a metal wiring layer (aluminum layer) 4 formed on an Si02 film 13 traverses the cross-under wiring layer 5, and corresponds to the metal wiring layer La of Figure 7. The metal wiring layer 4 (La) extends from the 12 L block (low-potential driving 12 L 40 block) of the (n -1)th stage to the 12 L block (high-potential driving ft block) of the n-th stage, and does not use a cross-under wiring layer in the 12 L block of the n-th stage. The N'-type layer 5 allows the wiring layer M4 in the 12 L block of the n-th stage to cross under the metal wiring layer 4 (La).
Table 1 shows potentials V,pi, Vp and VN of the W-type epitaxial layer, Ptype layer and N'-type layer in the cross-under wiring layers 5a,5b (diffusion resistors R, 1,R2) of the stacked IL IC thus constructed.
TABLE 1
R,, Potential V,,pi of W-type epitaxial layer (fixed potential) in volts R2 (n-11WF (n-2WF Potential Vp of P-type 55 layer (fixed potential) (n-11WF (n - 2)'W in volts Potential VN of cross underwiring layer (n-l)'VF (n-11WF 60 (variable potential) in to n'VF to n'VF volts W: forward bias= 0.7 volts n: numberofstages 65 4 - GB 2 133 622 A 4 As will be obvious from Table 1, the potential of the P-type layer never becomes lowerthan the potential of the cross-under wiring layer. According to this embodiment, therefore, no parasitic transistor operation develops even when the potential of the P-type layer is changed from ground potential to the potential of the N--type epitaxial layer in which the P-type layer is formed. For instance, in the case of the stacked 12 L]C of three stages as shown in Figure 7 the potential of the P-type layer 3a in which the cross-under wiring layer 5a 5 (diffusion resistance R,,) is formed, is 1.4 volts which is equal to the potential of the N-type epitaxial layer. On the other hand, the cross-under wiring layer 5a is provided with a potential of 1.4 volts to 2.1 volts. Therefore, forward bias is never applied across the cross-under wiring layer 5a and the Ptype layer 3a. The potential of the P-type layer 3b in which the crossunder wiring layer 5b (diffusion resistance R2) is formed, is 0.7 volts which is equal to the potential of the N --type epitaxial layer. The cross-under wiring layer 5b, on the other hand, is connected to the metal wiring layer M2 which extends from the 12 L block of the third stage, and. is provided with a potential of 1.4 volts to 2.1 volts. Therefore, forward bias is never applied across the cross-under wiring layer 5b and the P-type layer 3b.
in the stacked 12 L IC of this embodiment. the wiring regions can be greatly reduced compared with the stacked 12 L IC of the above-mentioned first embodiment. That is, since the potential of the P-type layer is set 15 to be equal to the potential of the N--type epitaxial layer in which the P-type region is formed, a long wiring for ground potential can be eliminated, and the shortest wiring is required to connect to the neighbouring N--type epitaxial layer. To realize a semiconductor integrated circuit device of a highly integrated form while preventing the occurrence of parasitic transistor operation, according to this embodiment, the wiring layer which extends from a low-potential driving 1 2 L block to a high- potential driving j2 L block should not use cross-under wiring, and the cross-under wiring layer should be connected to a metal wiring layer which accomplishes electrical connection within a single I1L block only.
In the case of a wiring layer M2 extending from a high-potential driving 12 L block to a low-potential driving j2 L block as will be obvious from the above-mentioned embodiments 1 and 2, no parasitic transistor operation takes place even when the cross-under wiring layer 5b is used. Below is mentioned an embodiment in which this technical idea is positively utilized.
Embodiment 3 Figure 9 illustrates a stacked 12 L IC in which the metal wiring layer M5 of the high-potential driving 12 L block is allowed to run into a low-potential driving 12 L block in detour due to the requirement of wiring layout, and 30 use is made of the cross-under wiring layer 5b.
In Figure 9, potentials of the P-type layers 3b,3c in which cross-under wiring layers (diffusion resistances) 5b,5c are formed, are set to be equal to the potentials of the N-type epitaxiai layers 2b,2c in which the P-type layers are formed. The potentials of the P-type layers 3b,3c may instead be maintained at a minimum potential (ground potential).
The above stacked I1L IC prevents the operation of a parasitic transistor that will be established by the N---typeepitaxial layer 2b, P-type layer 3b, and cross-under wiring layer (N'-type layer) 5b, because of the same reasons as mentioned in the embodiment 2. In particular, the potentials of the N-type epitaxial layer 2b and the P-type layer 3b do not become equal to the potential of the cross-under wiring layer 5b, but are necessarily smaller than the potential of the cross-under wiring layer 5b by at least a forward bias voltage 40 level (0.7 volts), to provide increased margin. In this circuit, also, the wiring regions can be greatly reduced on account of the same reasons as mentioned in the second embodiment.
The stacked 11 IC of the third embodiment can be modified as mentioned below.
(1) In Figure 9, the cross-under wiring layer 5b contacting to the metal wiring layer M5 maybe formed in the lk block in which the cross-under wiring layer 5c has been formed.
In this case, the potential of the P-type layer 3c is lower than the potential of the P-type layer 3b, and the parasitic transistor does not operate.
(2) The cross-under wiring layer 5b maybe formed in the N---typeepitaxial layer 2a (12 L block of the n-th stage) instead of the N --type epitaxial layer 2b (12 L block of the (n- 1)th stage), and the potential of the P-type layer may be set to be equal to the potential of the N--type epitaxial layer 2b (12 L block of the (n-1)th stage) to isolate the cross-under wiring layer 5b from the N--type epitaxial layer 2a.
In this case, the potential of the P-type layer is lower than the potential of the N--type epitaxial layer 2a, and forward bias is not applied across the P-type layer and the N--type epitaxial layer 2a. The cross-under wiring layer is provided with a potential higher than the potential of the P-type layer, and forward bias is not applied across the cross-under wiring layer and the P-type layer. It is therefore possible to prevent the 55 occurrence of parasitic transistor operation.
When the potential of the P-type layer is set to be lower than the potential of the N--type epitaxial layer, it is possible to form a plurality of cross-under wiring layers close to each other in the P-type layer. This point will be described below in detail.
Figure 10 illustrates a portion of a stacked 1 2 L]C in which two crossunder wiring layers 5al,5a2 are formed 60 close to each other in a P-type layer 3.
When the two cross-under wiring layers 5al,5a2 are formed close to each other in the P-type layer 3 as shown in Figure 10, however, there arises the problem of a parasitic lateral transistor Qp made up of the two cross-under wiring layers (N'-type layers) 5al,5a2, and the P-type layer 3. Namely, parasitic lateral transistor operation will develop (case A), or will not develop (case B), depending upon the conditions.
16 - C GB 2 133 622 A 5 Table 2 shows potentials of the cross-under wiring layers 5al,5a2, and of the P-type layer in these cases A and B. TABLE 2
Case A Case B Potential VN1 offirst cross-under wiring layer (n - 1)% (n-l)'VF 5a, (varying potential) to n'VF 10 in volts Potential Vp of P-type layer 3 (fixed potential) (n - 1WF (n - 2WF in volts 15 Potential VN2 of second cross-under wiring layer (n - 1)% (n - 1)% 5a2 (varying potential) to n-VF to n'VF in volts 20 The above-mentioned cases A and B will be described below in detail in connection with a three-stage stacked 12 L IC (n=3).
(1) Case A As shown in dotted lines in Figure 10, the P-type layer 3 is connected to the N--type epitaxial layer 2 25 through an electrode 14A, to maintain the potential of the P-type layer 3 at 1.4 volts. When the potential of the first cross-under wiring layer 5a, is VN1 = 2.1 volts, and the potential of the second cross-under wiring layer 5a2 is VN2 = 1.4 volts, the potential of a portion of the P-type layer (base) 3 rises, so that the parasitic lateral transistor Qp will operate. This is because the P-type layer 3 has a low impurity concentration and, hence, has resistance R5 which causes the potential VPR of a portion of the P-type layer 3 to become greater 30 than 1.4 volts. Therefore, a voltage greater than 0.7 volts is applied across the P-type layer (base) 3 and the second cross-under wiring layer (emitter) 5a2, so that the transistor Qp will operate. Further, when the first cross-under wiring layer 5a, has a potential VN1 = 1.4 volts, and the second cross-under wiring layer 5a2 has a potential VN2 = 2.1 volts, the parasitic lateral transistor Qp will also operate. In this case, the first cross-under wiring layer 5a, serves as an emitter, and the second cross- under wiring layer 5a2 serves as a collector.
(2) Case B As shown in bold lines in Figure 10, the potential of the P-type layer 3 is set to be equal to the potential (0.7 volts) of the N --type epitaxial layer in the 1 2 L block of the (n- 1)th stage by a metal wiring layer 1413. That is, 40 the potential of the P-type layer 3 is set to be lower than the potential of the N--type epitaxial layer 2.
When the first cross-under wiring layer 5a, has a potential VN1 = 2.1 volts, and the second cross-under wiring layer 5a2 has a potential VN2 = 1.4 volts, the potential of a portion of the P-type layer (base) 3 rises as illustrated in the case A. However, since the potential of the rest of the P-type layer 3 remains at 0.4 volts, the potential VPR at this portion of the P-type layer never rises about 1.4 volts. Therefore, the parasitic lateral 45 transistor Qp does not operate.
When the potential of the P-type layer is set to be lower than the potential of the N-type epitaxial layer as in the above-mentioned case B, the parasitic lateral transistor does not operate even when a plurality of cross-under wiring layers are formed in the P-type layer close to each other.
Therefore, in the case of a stacked 12 L which requires a plurality of cross-under wiring layers formed close 50 to each other in the P-type layer, it is desired that the P-type layer is electrically connected to a lower potential, e.g. to the N --type epitaxial layer in the 12 L block of the previous stage.
Attention is drawn to our copending application No. 83.01731, from which this application has been

Claims (8)

  1. divided, in which there is claimed in claim 1, a semiconductor integrated
    circuit device comprising a first semiconductor layer of a first type of conductivity, a second semiconductor layer of a second type of conductivity which is in contact with said first semiconductor layer, and a third semiconductor layer of the first type of conductivity which is in contact with said second semiconductor layer, wherein two metal wiring layers are connected to said third semiconductor layer at spaced positions, and a predetermined potential is applied to said second semiconductor layer such that a forward bias will not be applied across said first semiconductor layer and said second semiconductor layer.
    CLAIMS 1. An integrated injection logic semiconductor integrated circuit device including:
    (a) first, second and third semiconductor regions that are electrically isolated from each other; 6 GB 2 133 622 A 6 (b) a first integrated injection logic block including a plurality of integrated injection logic elements formed in the first semiconductor region; (c) a second integrated injection logic block including a plurality of integrated injection logic elements formed in the second semiconductor region; (d) a third integrated injection logic block including a plurality of integrated injection logic elements 5 formed in the third semiconductor region; (e) first, second and third metal wiring layers formed in said first, second and third integrated injection logic blocks, respectively; (f) a first cross-under semiconductor layer which crosses under and is electrically isolated from the first metal wiring layer formed in the first semiconductor region; (g) a second cross-under semiconductor layer which crosses under and is electrically isolated from the second metal wiring layer formed in the second semiconductor region; (h) a third cross-under semiconductor layer which crosses under and is electrically isolated from the third metal wiring layerformed in the third semiconductor region; (i) a first semiconductor layer which has a conductivity type opposite to that of said first cross-under semiconductor layer, and which is located adjacent to said first cross- under semiconductor layer to electrically isolate said first cross-under semiconductor layer from said first semiconductor region; (j) a second semiconductor layer which has a conductivity type opposite to that of said second cross-under semiconductor layer, and which is located adjacent to said second cross- under semiconductor layer to electrically isolate said second cross-under semiconductor layer from said second semiconductor region; 20 and (k) a third semiconductor layer which has a conductivity type opposite to that of said third cross-under semiconductor layer, and which is located adjacent to said third crossunder semiconductor layerto electrically isolate said third cross-under semiconductor layer from said third semiconductor region; wherein said first, second and third semiconductor regions are provided with predetermined potentials 25 which are different from each other, and wherein said first, second and third semiconductor layers are provided with predetermined potentials set at levels to prevent a forward bias from being applied across said first cross-under semiconductor layer and said first semiconductor layer, across said second cross-under semiconductor layer and said second semiconductor layer, or across said third cross-under semiconductor layer and said third semiconductor layer.
  2. 2. An integrated injection logic semiconductor integrated circuit device according to claim 1, wherein the potential of said second semiconductor region is maintained higher than the potential of said first semiconductor region, and the potential of said third semiconductor region is maintained higher than the potential of said second semiconductor region.
  3. 3. An integrated injection logic semiconductor integrated circuit device according to claim 2, wherein the 35 potentials of said first, second and third semiconductor layers are maintained equal to the potential of said first semiconductor region.
  4. 4. An integrated injection logic semiconductor integrated circuit device according to claim 2, wherein said first, second and third semiconductor layers are electrically connected to said first, second and third semiconductor regions, respectively.
  5. 5. An integrated injection logic semiconductor integrated circuit device according to claim 2, wherein said third semiconductor layer is electrically connected to said second semiconductor region.
  6. 6. An integrated injection logic semiconductor integrated circuit device according to claim 5, wherein a fourth cross-under semiconductor layer having the conductivity type same as that of said third cross-under semiconductor layer, is formed in said third semiconductor layer close to said third cross-under semiconductor layer.
  7. 7. An integrated injection logic semiconductor integrated circuit device according to anyone of the preceding claims 2 to 6, wherein said third metal wiring layer is electrically connected to an integrated injection logic element in the second integrated injection logic block.
  8. 8. An integrated injection logic semiconductor integrated circuit device substantially as herein described 50 with reference to and as illustrated in Figures 5 to 10 of the accompanying drawings.
    A 36 Printed for Her Majesty's Stationery Office, by Croydon Printing Company limited, Croydon, Surrey, 1984. Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.
    A, 1
GB08403188A 1982-01-25 1984-02-08 An integrated injection logic semiconductor integrated circuit device Expired GB2133622B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57008932A JPS58127363A (en) 1982-01-25 1982-01-25 Semiconductor ic device

Publications (3)

Publication Number Publication Date
GB8403188D0 GB8403188D0 (en) 1984-03-14
GB2133622A true GB2133622A (en) 1984-07-25
GB2133622B GB2133622B (en) 1985-11-20

Family

ID=11706432

Family Applications (2)

Application Number Title Priority Date Filing Date
GB08301731A Expired GB2113915B (en) 1982-01-25 1983-01-21 Semiconductor integrated circuit device
GB08403188A Expired GB2133622B (en) 1982-01-25 1984-02-08 An integrated injection logic semiconductor integrated circuit device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB08301731A Expired GB2113915B (en) 1982-01-25 1983-01-21 Semiconductor integrated circuit device

Country Status (9)

Country Link
JP (1) JPS58127363A (en)
KR (1) KR910002036B1 (en)
DE (1) DE3302206A1 (en)
FR (1) FR2520555B1 (en)
GB (2) GB2113915B (en)
HK (2) HK70687A (en)
IT (1) IT1160470B (en)
MY (1) MY8700613A (en)
SG (1) SG36587G (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3926011B2 (en) 1997-12-24 2007-06-06 株式会社ルネサステクノロジ Semiconductor device design method
JP4292668B2 (en) * 2000-01-31 2009-07-08 富士ゼロックス株式会社 Light emitting thyristor array

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3443176A (en) * 1966-03-31 1969-05-06 Ibm Low resistivity semiconductor underpass connector and fabrication method therefor
DE1949484B2 (en) * 1969-10-01 1978-02-23 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithic integrated circuit conductive tracks intersection - has low ohmic electrode region of one integrated component longitudinally extended and containing terminal contacts
FR2244262B1 (en) * 1973-09-13 1978-09-29 Radiotechnique Compelec
DE2514466B2 (en) * 1975-04-03 1977-04-21 Ibm Deutschland Gmbh, 7000 Stuttgart INTEGRATED SEMI-CONDUCTOR CIRCUIT
JPS5264830A (en) * 1975-11-25 1977-05-28 Hitachi Ltd Power source supply system of integrated injection logical circuit
NL7700420A (en) * 1977-01-17 1978-07-19 Philips Nv SEMI-CONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THIS.
US4228450A (en) * 1977-10-25 1980-10-14 International Business Machines Corporation Buried high sheet resistance structure for high density integrated circuits with reach through contacts
DE3143565A1 (en) * 1981-11-03 1983-05-11 International Microcircuits Inc., 95051 Santa Clara, Calif. Integrated circuit

Also Published As

Publication number Publication date
IT8319236A0 (en) 1983-01-21
KR910002036B1 (en) 1991-03-30
MY8700613A (en) 1987-12-31
KR840003536A (en) 1984-09-08
IT1160470B (en) 1987-03-11
HK71287A (en) 1987-10-09
SG36587G (en) 1987-07-24
DE3302206A1 (en) 1983-08-04
GB8301731D0 (en) 1983-02-23
JPS58127363A (en) 1983-07-29
FR2520555A1 (en) 1983-07-29
FR2520555B1 (en) 1987-02-20
GB2113915A (en) 1983-08-10
JPH0334661B2 (en) 1991-05-23
GB8403188D0 (en) 1984-03-14
HK70687A (en) 1987-10-09
GB2133622B (en) 1985-11-20
GB2113915B (en) 1985-11-20

Similar Documents

Publication Publication Date Title
US4490629A (en) High voltage circuits in low voltage CMOS process
US6767784B2 (en) Latch-up prevention for memory cells
IE53844B1 (en) Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers
US4480319A (en) Emitter coupled flip flop memory with complementary bipolar loads
US4672416A (en) Semiconductor device
KR100496362B1 (en) Integrated ESD Protection Circuit Using Substrate Triggered Lateral NPN
JPS5873236A (en) Logic circuit
GB2133622A (en) An integrated injection logic semiconductor integrated circuit device
EP0003559A1 (en) Current mirror circuit
US4547743A (en) Variable resistance gain control integrated circuit
US3544860A (en) Integrated power output circuit
US5237198A (en) Lateral PNP transistor using a latch voltage of NPN transistor
US4160990A (en) Semiconductor devices and circuit arrangements including such devices
WO1985002062A1 (en) Cmos integrated circuit configuration for eliminating latchup
JP2563783B2 (en) Static electricity protection circuit
GB2106320A (en) Semiconductor integrated injection logic circuit device and fabrication method thereof
US7868392B2 (en) Integrated circuit tolerant to the locking phenomenon
US3557444A (en) Monolithic bipolar transistor logic circuit and method of forming same
JPH0458696B2 (en)
JPH0124377B2 (en)
JP3315310B2 (en) Semiconductor device
JPS60217656A (en) Semiconductor device
EP0172888A1 (en) Versatile generic chip substrate.
JPS61150229A (en) Integrated circuit
JP3124938B2 (en) DC stabilized power supply circuit

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19970121