GB2121601A - Uncommitted logic integrated circuit array - Google Patents

Abstract

A logic array in integrated circuit form comprises a plurality of transistor sub-arrays, forming a cell, each sub-array including a series connection of two p-channel transistors (P1,P2) and a series connection of two n-channel transistors (N1, N2). The gate (G1) of one p-channel transistor (P1) is connected to the gate (G3) of one n-channel transistor (N1), and the gate (G2) of the other p-channel transistor (P2) is connected to the gate (G4) of the other n-channel transistor (N2); the transistors of the sub-arrays being otherwise unconnected, at least initially, so that the logic array is uncommitted. In order to provide a desired logic circuit function, that is to commit the array, an appropriate metallisation connection pattern (not shown) is employed to interconnect selected transistors of the sub-arrays within the cell; different metallisation patterns between contacts 3-8, 14, 15, 19, 20 resulting in different logic functions. <IMAGE>

Description

SPECIFICATION Integrated circuits This invention relates to integrated circuits and in particular to transistor arrays comprising uncommitted logic arrays.

According to the present invention there is provided a logic array in integrated circuit form and adapted to be committed to a desired logic function in dependence on the configuration of an electrically-conductive interconnection pattern to be applied thereto, the array including at least one transistor subarray comprising first and second p-channel MOS transistors connected in series and first and second n-channel MOS transistors connected in series, wherein in the uncommitted state of the logic array the gate electrode of the first p-channel transistor is connected to the gate electrode of the first n-channel transistor and the gate electrode of the second pchannel transistor is connected to the gate electrode of the second n-type transistor whilst the transistors are otherwise unconnected in the one sub-array or connected to transistors of other sub-arrays.

Embodiments of the present invention will now be described with reference to the accompanying drawings in which Figure 1 shows a circuit diagram of a transistor sub-array, Figure 2 shows a schematic plan view of a practical embodiment (uncommitted) of the sub-array of Fig. 1, Figure 3 shows a schematic section taken along line Ill-Ill of Fig. 2, and Figure 4 shows a schematic plan view of a transistor array (uncommitted) incorporating sixteen sub-arrays of Fig. 2.

Uncommitted logic arrays are employed in integrated circuit manufacture in order to minimise the number of specific fabrication masks required, and thus the cost, for low volume orders of specific function devices. Thus for each of a family of devices the same fabrication masks are employed up to the metallisation stage, but different metallisation masks are employed. Therefore, the component layout is standardised and fixed, but for each new application the final metallisation (electrically-conductive interconnection) pattern is customised. It is therefore essential that the fixed component layout is such that the elements thereof can be interconnected a sufficient number of different ways to provide design flexibility with efficient use of integrated circuit chip area.

The uncommitted logic arrays of the present invention employ transistor sub-arrays with a circuit diagram as illustrated in Fig. 1. The sub-array comprises a series connection of a pair of p-channel MOS transistors P1 and P2, and a series connection of a pair of n-channel MOS transistors N1 and N2. The gates G1 and G3 of transistors P1 and N1 are connected to a common terminal 1, and the gates G2 and G4 of transistors P2 and N2 are connected to a common terminal 2. The transistors P1 and P2 have a common terminal 3 and separate terminals 4 and 5, respectively, whereas the transistors N1 and N2 have a common terminal 6 and separate terminals 7 and 8, respectively.

A schematic plan view of a practical realisation of the sub-array of Fig. 1 is shown in Fig.

2, and a schematic section therethrough is shown in Fig. 3. The transistors P1 and P2 are defined within an area 16 of a semiconductor substrate 30 whereas the transistors N1 and N2 are defined within an area 17, the limits of the P+ and N+ diffusions within these areas having been omitted from Fig. 2 for clarity although they are apparent from the cross-section of Fig. 3. Figs. 1 and 2 employ identical reference numerals for like elements, and as will be appreciated from Fig. 3, the gate electrodes G1-4, and their respective interconnections 9 and 11, are arranged on an insulating layer (gate oxide) 18 and under an insulating intermediate oxide layer 1 8a and contacted, as at 1 and 2, via apertures in the insulating layer 1 8a in which electrically-conductive material (metal) is deposited.The gate electrodes and their interconnections are thus effectively arrayed within an insulating layer provided on the surface of the substrate 30.

Additional contacts to the gate interconnections may be provided within the sub-array as at 19 and 20 (Fig. 2). Typically the gates G1-4 and their interconnections 9 and 11 are comprised by metal or polysilicon, although other high electrical conductivity materials such as titanium silicide may be employed. In order to provide for possible electrical connection between transistors P2 and N2 a connection 13, also of metal or polysilicon, for example, is arranged therebetween on an electrically-insulating layer 1 3 a. The connection 13 is not in direct contact with the transistors P2 and N2. Contact to the connection 13 is provided by means of electrically-conductive contacts 14 and 15 extending through respective apertures in the insulating layer 1 8a provided thereover. The sub-array shown in Figs.

2 and 3 may be made by entirely conventional processes which will be readily apparent to those skilled in the art and are thus not described in detail. Fig. 3 indicates the use of a N-type semiconductor substrate, however this may alternatively be of P-type with corresponding change to the type of the other indicated regions. Over the insulating layer 1 8a are provided metal interconnection tracks 10 and 12, providing power supply and/or earthing for the transistors which tracks are outside of the subarray proper, indicated by dashed lines. No "metallisation" other than of the contacts 3, 4, 5, 6, 7, 8, 14, 15, 19 and 20 themselves is provided within the sub array boundaries.Thus the uncommitted logic arrays comprising a plurality of sub-arrays as indicated in Figs. 1 to 3, can be committed to a required function simply by the subsequent application of a suitable electrically-conductive (metallization) pattern thereto to interconnect selected ones of the separate contacts.

Fig. 4 illustrates an uncommitted logic array comprising two arrays or cells 21 and 22, which is of particular benefit in integrated circuits designed for telecommunicaitons purposes. The arrays 21 and 22, which are symmetrical about the metal interconnection track 12, each comprise eight transistor subarrays 23 equivalent to that shown in Fig. 2 and which are functionally equivalent to Fig.

1. The diffused areas have been omitted from Fig. 4 for clarity. In dependence on the required function the sub-arrays or elements thereof are interconnected by a suitable single layer electrically-conductive (metallisation) pattern (not shown) generally within the boundary of a cell defined by array 21 or 22. The cell is connected to the remainder of the circuit of which it forms a part by connections (not shown) extending from the external gate contacts such as 1 and 2 or contacts, such as 24 on track 10, to the metal tracks 10 and 12. The length of the connections 13 enables more than one metal track of the interconnection pattern to be arranged between the contacts 14 and 15.The sub-arrays are suitably spaced apart whereby to allow at least one electrically-conductive (metal) track to connect contacts 7 and 8, for example within obtainable alignment tolerances so that another contact is not inadvertently contacted.

In dependence on the electrically-conductive interconnection pattern employed the elements of the two cells of the uncommitted logic array of Fig. 4 can be interconnected, for example, to provide any of the following functions: two 2-input multiplexers; a 2-bit static shift register; multiple input NAND or NORS; inverting buffers; four latches; two exclusive-OR; a full adder; various combination logic. Uncommitted logic arrays with other than the eight or sixteen sub-arrays indicated above may also be envisaged using the same basic sub-array circuit of Fig. 1. In the case of smaller numbers of sub-arrays per logic array it may be necessary to interconnect, for example, two such logic arrays in order to construct a required function; In this case, therefore, the logic function will not be created entirely within a particular cell.For telecommunications purposes, in particular, we have found that a logic island with a two cell arrangement, comprising two arrays of eight such sub-arrays, as indicated in Fig. 4, enables all of the logic functions presently regarded as necessary to be constructed within such an island, and that this is particularly beneficial to circuit design employing computer designed autorouting, since the functional parts of the chip can be confined to specific island areas thereof, leaving the remainder of the chip between the islands entirely free for interconnection of the logic functions provided in the islands. Autorouting is a term of art used to describe the connection together of all of the functions provided on a chip by means of a single layer of tracks provided in the spaces between the islands and input/output buffer cells arranged around the periphery of the chip. Our co-pending Applications No. (Serial No.

(D.J.Rogers 2) and No. (Serial No.

(D.J.Rogers 3) are also concerned with uncommitted logic array integrated circuits, the former application relating to function arrays with which the transistor arrays of the present invention may be employed, and the latter relating to interconnect arrangements for use with autorouting techniques.

Claims (8)

1. A logic array in integrated circuit form and adapted to be committed to a desired logic function in dependence on the configuration of an electrically-conductive interconnection pattern to be applied thereto, the array including at least one transistor subarray comprising first and second p-channel MOS transistors connected in series and first and second n-channel MOS transistors connected in series, wherein in the uncommitted state of the logic array the gate electrode of the first p-channel transistor is connected to the gate electrode of the first n-channel transistor and the gate electrode of the second pchannel transistor is connected to the gate electrode of the second n-type transistor whilst the transistors are otherwise unconnected in the one sub-array or connected to transistors of other sub-arrays.

2. An array as claimed in claim 1, wherein the transistors include source, drain and gate regions extending into a semiconductor substrate from a surface thereof, wherein the gate electrodes and the connections therebetween are comprised by electrically conductive material arranged within an electrically insulating layer provided upon the surface of the semiconductor substrate, and wherein electrical contact to the connections between the gate electrodes and to the source and drain regions of the transistors is made via electricallyconductive material deposited in respective apertures in the insulating layer to form respective electrical contacts, whereby, in dependence on the configuration of the electrically-conductive interconnection pattern to be provided on the insulating layer, selected electrical contacts may be interconnected to provide the desired logic circuit function.

3. An array as claimed in claim 2, wherein an interconnection track of electrically conductive material is arranged in the insulating layer between the second p-channel transistor and the second n-channel transistor and spaced apart therefrom, electrical contact to the interconnection track being via electrically-conductive material deposited in respective apertures in the insulating layer to form respective electrical contacts.

4. An array as claimed in claim 2 or claim 3, wherein the logic array comprises a plurality of said transistor sub-arrays which together define a cell and wherein the desired logic circuit function is obtained by interconnection of electrical contacts arranged within the cell boundary.

5. An array as claimed in claim 4, comprising eight of said transistor sub-arrays per cell.

6. A logic array substantially as herein described with reference to the accompanying drawings.

7. An integrated circuit including a logic array as claimed in any one of the preceding claims.

8. An integrated circuit including a committed logic array formed by the application of an electrically-conductive interconnection pattern to a logic array as claimed in any one of claims 1 to 6.