GB2088104A - Data memories - Google Patents

Abstract

A data memory for storing n bit data words comprises n bubble memories (e.g. (6)) each storing a respective single bit of each data word. The n bubble memories are stepped in parallel with each other and at some of the addresses to which the data memory is stepped a further memory (31) is examined to determine whether any of the n bubble memories has stepped to an unuseable address. If any particular memory is identified as having stepped to an unuseable address it is independently stepped to the next useable address. Parallel stepping of the n bubble memories then continues. <IMAGE>

Description

SPECIFICATION Data memories The present invention relates to data memories and in particular but not exclusively to such memories of the kind known as bubble memories.

Bubble memories have started to become economic substitutes for other kinds of semi-fast access-storage only in the very recent past.

As manufacturing techniques improve the cost per bit of bubble memory has been significantly reduced and the reliability of such memories significantly improved. One major advantage of bubble stores, as opposed to magnetic disc and drum stores and the like, is the absence of physically moving parts (for example motors). This reduces the maintenance requirement and, to a certain extent, the power requirement.

However, it is not feasible to produce large quantities of bubble memories in which all of the magnetic loops are perfect. Therefore, when memories of, say, two kilobits are manufactured the basic design may be for a two and one-half kilobit memory. Post manufacture the best loops in each device are selected for use the remaining loops (those not selected for use) being redundant.

If the redundant loops were all to occur in a sequential order at consecutive addresses of the bubble memory device it would be relatively simple to overcome the redundant loop problem.

However, it will be readily appreciated that this will not be the case, the redundant loops being scattered at random addresses of the bubble memory device.

When a bubble memory device is prepared for use the redundant loop addresses are identified (either by the manufacturer or user) and a tape or listing of the redundant loop addresses is made.

The tape or listing may then be used in the addressing circuitry of the device to ensure that redundant loops are not used.

This in effect overcomes the problem for such a memory when it is utilised to provide a series of single bits. It will be realised that a single bit in terms of data storage is insignificant unless the data words are stored in serial form. However, in serial form, accessing a word of data of say sixteen bits will take an appreciable time of sixteen times the access time for a single bit.

Therefore, it is more usual to provide one memory device for each bit required to make a word and to run the devices in parallel to give, say, a sixteen bit store, two thousand words long.

The problem of circumventing the redundant loops in each device and keeping the memories in step is now much more difficult to overcome.

It is one object of the present invention to provide a data memory, having several single bit devices running in a parallel mode, in which the difficulties caused by redundant (or malfunctioning) sections of the single bit devices are substantially overcome.

According to the present invention a data memory comprises n electrically-alterable storage devices each arranged to store data bits in a sequential manner, means to step digit values held in said n storage devices through respective addresses in a sequential manner and in parallel with each other, output means arranged to read out the respective outputs of said n electricallyalterable storage devices as an n bit data word, a further storage device arranged to store data indicating in respect of each address to which the data memory is stepped which, if any, of the n electrically-alterable storage devices has stepped to an unusable or malfunctioning segment, and stepping means arranged to step selected ones of the n storage devices independently of the other storage devices in response to the data held in said further storage device so as to avoid unusable or malfunctioning segments.

Preferably each of the n data storage devices is of the kind known as a bubble memory in which the data bits are stored as magnetic domains in an addressable loop configuration.

The stepping means may be arranged to cause selected ones of the n storage devices to step over a complete respective storage loop.

The further storage device may store data relating to redundant loops of each of the n bubble memories such that the digit values held in the bubble memories are stepped through a single loop in sequential order and only when a change of loop is indicated are selected ones of the n bubble memories stepped independently.

An embodiment of a storage memory in accordance with the invention will now be described with reference to the accompanying drawing which is a block schematic diagram of such a memory.

Referring to the drawing the data memory comprises nine bubble modules 10 to 18 each of which provides one bit of a series of nine bit bytes.

The nine bit bytes provided by the memory are used in pairs to form 1 6bit data words with two parity bits to enable the validity of the information retrieved to be checked. Provision of odd or even parity on data words is well known in the art, as are parity checking circuits and neither are discussed further herein.

Each of the bubble modules 10 to 1 8 is identical with the bubble module 10 and comprises select logic 1 which determines when and if the respective module is addressed, a bubble memory device 6, 'X' and 'Y' coil drivers 2, function drivers 3, 4 and 5 which control respectively bubble generation, bubble replication and annihilation, and bubble transfer, a sense amplifier 8 which detects the presence of a bubble at the reading point and a data toggle 7 which holds to the data output at the last reading of the memory.

The bubble memory device 6 contains a slice of gadolinium gallium garnet with a thin film of magnetic garnet epitaxially grown on its surface.

The magnetic garnet film has a deposited permalloy pattern including required special purpose areas for generation, annihilation and detection (reading) of magnetic bubbles. Other areas are arranged for transferring bubbles between major and minor storage loops on the device. Mounted on each side of the garnet slice is a permanent magnet which produces a magnetic field normal to the surface of the garnet. This field maintains the size and stability of the magnetic bubbles in the epitaxial magnetic layer.

Two orthogonal coils, the 'X' and 'Y' coils are wound around the garnet and permanent magnet assembly. When the 'X' and 'Y' coils are appropriately driven they produce a rotating field in the plane of the garnet slice which causes the bubbles to move along the storage loops of the epitaxial magnetic layer.

Reading, generation, replication and annihilation of bubbles is usually carried out on a single dedicated storage loop known as the major loop whilst the remaining storage loops are referred to as minor loops.

Under control of addressing circuitry (not shown) data held by selected minor loops of each bubble device 6 is transferred to the respective major loops. This action is carried out in parallel on all nine of the bubble modules 10 and 1 8 by way of select logic circuitry 1 activated by the addressing circuitry over leads 21 and 22. It will be realised that although only a single highway is shown for each of the leads 21 and 22, there are respective leads 21 and 22 for each of the bubble modules 10to 18.

When the appropriate data to be read has been transferred by use of a transfer driver 5 to the major loop the data is read by rotating the bubbles on the major loop past a read head and enabling respective sense amplifiers 8, at the time when the bubbles pass the read heads, by way of a sense amplifier timing lead 26 which is common to all of the bubble modules 10 to 1 8.

The timing lead 26 also enables the respective data toggles 7 so that they switch to the data value read from the bubble devices 6. The data then passes by way of nine respective leads 25 and a data output driver 9 to an output highway 27 which is nine bits wide.

As has been stated the nine bubble modules 10 to 18 are addressed in parallel so that the respective bubble devices each have a bit associated with one byte of a particular word at the reading point at the same instant of time. If all of the bubble devices 6 were functionally identical, keeping the respective bits in synchronism would not be a problem and the addressing circuitry could continuously rotate the minor loops of all of the devices.

This not being so the data memory includes a minor loop counter 30 which is stopped by the addressing circuitry each time respective minor loops are transferred to the respective major loop in the bubble devices 6. The minor loop counter 30 addresses a redundant loop PROM (programmable-read-only-memory) 31 which is nine bits wide and contains a respective marker bit at any address at which a respective one of the nine bubble devices 6 has a redundant or malfunctioning minor loop.

The output of the redundant loop PROM 31 addresses a "chip select register" 35 and a redundant loop detector 33.

If, after a transfer of minor loops has taken place, the redundant loop PROM 31 indicates that one (or more) of the bubble devices 6 has a redundant loop, the parallel driving of the bubble modules 10 to 18 is stopped and the respective bubble device(s) 6 is further rotated under control of the redundant loop detector 33 and the chip select register 35 until no further redundant minor loops are indicated by the redundant loop register 32.

Claims (7)

1. A data memory comprising n electrically alterable storage devices each arranged to store data bits in a sequential manner, means to step digit values held in said n storage devices in a sequential manner and in parallel with each other, output means arranged to read out the respective outputs of said n electrically-alterable storage devices as an n bit data word, a further storage device arranged to store data indicating in respect of each address to which the data memory is stepped which, if any, of the n electrically alterable storage devices has stepped to an unusable or malfunctioning segment, and stepping means arranged to step selected ones of the n storage devices independently of the other storage devices in response to the data held in said further storage device so as to avoid unusable or malfunctioning segments.

2. A data memory as claimed in claim 1 wherein each of then storage devices is a bubble memory in which the data bits are stored as magnetic domains in an addressable loop configuration.

3. A data memory as claimed in claim 2 wherein the stepping means is arranged to cause selected ones of the n storage devices to step over a complete respective storage loop.

4. A data memory as claimed in claim 2 or claim 3 wherein the stepping means is arranged to operate only at respective addresses of the data memory at which a change of respective storage loops of the bubble memories is required.

5. A data memory as claimed in any preceding claim wherein at least one storage device is arranged to store a respective parity bit for each data word read by the output means and parity checking means is arranged to provide an indication of the validity of the output data.

6. A data memory as claimed in any preceding claim wherein said further storage device is a programmable-read-only-memory.

7. A data memory substantially as hereinbefore described with reference to the accompanying drawing.