GB2088103A

GB2088103A - Memory control circuit

Info

Publication number: GB2088103A
Application number: GB8130756A
Authority: GB
Original assignee: Victor Company of Japan Ltd; Nippon Victor KK
Current assignee: Victor Company of Japan Ltd; Nippon Victor KK
Priority date: 1980-10-13
Filing date: 1981-10-12
Publication date: 1982-06-03
Also published as: JPS5766515A; GB2088103B; DE3140683A1; DE3140683C2; JPS628858B2; FR2492149B1; FR2492149A1

Abstract

A circuit for controlling a memory in which jitter-affected data is written at a rate commensurate with its occurrence and read out at a constant rate, includes writing and reading address counters (35, 36) to address storage locations for writing and reading operations, respectively. The writing address counter (35) is incremented at the same rate as the data is written, into the memory (32) while the reading address counter (36) is normally incremented at the constant rate. A subtractor (38) is coupled to the outputs of the writing and reading address counters to detect the difference in digital value between the storage locations addressed by the two counters. A decoder (40) is provided to detect when the difference reaches a specified upper or lower limit to cause the incremental rate of the reading address counter to decrease or increase, respectively, to prevent the memory from becoming overflowed or underflowed. <IMAGE>

Description

SPECIFICATION Memory control circuit The present invention relates generally to digital recording and reproducing systems, and in particular to a circuit for controlling a memory in which the reproduced digital signal is stored for jitter elimination and time expansion purposes.

In conventional PCM recordinglreproducing systems, digitally converted original signal is time compressed and combined with error detection and correction codes and synchronization pulses during the period prior to recording on a recording medium and the reproduced original signal is separated from such control signals and coupled to a memory for purposes of expanding its time dimension and eliminating jitter which has been introduced due to mechanical tolerances of the recording system. The memory is controlled by a writing and reading address counters to store jitter-affected digital signal in response to the jitter-affected synchronization pulse and read it out in response to a standard constant rate pulse which occurs at a lower rate than the synchronization pulse so that the digital signal is time-expanded.

A shortcoming inherent in the conventional memory control circuit is the overflowing of the memory which occurs when a large amount of jitter is generated due to transients such as starting of the recorder in playback mode or a temporary fluctuation of tape. Noise is thus generated when the overflowed signal is converted into an analog signal.

In a prior art approach to solving this problem.

the reading address counter is cleared when the memory is approaching an overflow condition to prevent it from becoming overflowed. A muting circuit is employed to mask the noise which would result from the rapid change in digital value when the reading address counter is cleared, thus producing an interruption of sound.

The present invention overcomes the noise generation problem by varying the incremental rate of the reading address counter in a direction to decrease its rate from standard rate when the memory is approaching an upper limit or in an opposite direction when the memory is approaching a lower limit. The variation of the incremental rate in either direction continues until an intermediate address count is reached so that a same data word is repeatedly read out for delivery to an output circuit when the incremental rate is decreased or an intermediate data word is skipped when the incremental rate is increased. There is no appreciable amount of transition in digital value when the incremental rate is varied which would amount to noise of noticeable degree.

According to the present invention, there is provided a circuit for controlling a memory adapted to store jitter-containing data words which are written thereinto at a rate corresponding to the rate of occurrence of the data words. The circuit comprises a first address counter arranged to be incremented at the variable rate for generating a digital incremental value for addressing storage locations into which the data words are written, a second address counter normally arranged to be incremented at a standard constant rate for generating a digital incremental value for addressing storage locations out of which the stored data words are to be read, means for reading data words at the constant rate from the storage locations addressed by the second counter, means for detecting when the amount of data words stored in the memory reaches an upper or a lower limit, and means for controlling the second counter to increase or decrease its incremental rate upon the detection of the upper or lower limit, respectively.

The invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 is a schematic block diagram of a PCM recording and reproducing system embodying the invention; Fig. 2 is a block diagram illustrating the detail of the jitter elimination and time expansion circuit of Fig. 1; Fig. 3 is a waveform diagram associated with the circuit of Fig. 2; and Fig. 4 is a waveform diagram illustrating waveforms of the digital signal read out of the memory of Fig. 2.

Referring now to Fig. 1, there is shown a PCM recording-reproducing apparatus embodying the present invention in schematic form. Two channel analog audio signals are coupled to low-pass filters 2a, 2b through input terminals 1 a, 1 b to cut off the high frequency components of the input signals and thence to sample-hold circuits 3a, 3b in a well known manner. The samples voltages are alternately coupled through a known multiplexer or switching circuit 4 to an analog to digital converter 5 where the sampled analog values are translated into corresponding digital codes represented by a predetermined number of binary digits. Thus, the sample-hold circuits 3a, 3b, multiplexer 4 and analog to digital converter 5 form a two-channel PCM encoder.For purposes of inserting vertical and horizontal sync pulses and error detection and correction codes to the PCM information signal, the latter is written into a time compression memory 6 and is read out of it at a rate higher than the input rate. A memory control unit 7 controls the input and output rates of the memory 6. The time-compressed digitatsignal is coupled to an adder 8 where it is combined with error detection and correction codes supplied from an error detection and correction code generator 11. The output of adder 8 is coupled to an adder 9 where it is combined with vertical and horizontal sync pulses supplied from a sync generator 10.

The output of adder 9 is coupled to a conventional video tape recorder 12 of a helical scan type and recorded along skewed tracks in the same manner as video signals are recorded.

Reproduced digital signal is applied to a sync separator 14 whence the sync pulses are separated and applied to a write signal generator 15 and the remainder is coupled to an error detector 16 of a conventional design in which information bits in error are detected in a known manner and supplied to an error corrector 17 which is controlled by an error corrector control unit 18. The error detection and correction codes are removed from the stream of information bits and coupled to a jitter elimination and time expansion circuit 20 constructed in accordance with the invention.The circuit 20 includes a memory and a memory control circuit to be described and receives write control signals from the generator 15 in synchronism with the separated sync pulses to write the .nformation bits on a per word basis into the memory and read them out of the memory at a specified constant rate in order to eliminate jitters introduced by the video tape recorder due to its mechanical tolerances. Since the reproduced digital signal has a smaller time dimension that the original, the circuit 20 also functions to expand its time dimension in a manner as will be detailed later.

The output of jitter elimination and time expansion circuit 20 is coupled to a digital toanalog converter 21 to translate the timeexpanded information bits or data word into a voltage signal which is alternately coupled through a demultiplexer or switch 22 to low-pass filters 23a and 23b to reconstruct the original audio signals for delivery through respective output terminals 24a and 24b to a stereo reproduction circuit, not shown.

Referring now to Fig. 2, details of the jitter elimination and time expansion circuit 20 are illustrated. The output of error corrector 17 is coupled to an input latch 31 and temporarily stored therein in response to a latch pulse 47 (see Fig. 3) supplied from write signal generator 15.

The latter generates the latch pulse as well as write enable pulses 46 and count-up pulses 50 in synchronism with the separated sync pulses.

Write enable pulses are applied to a random access memory 32 and to a selector 34, and count-up pulses are applied to a writing address counter 35. In response to a write enable pulse 46, RAM 32 is enables and selector 34 is switched to couple its input from writing address counter 35 to RAM 32 to store the latched data on a per data word basis in a storage location specified by writing address counter 35. The counter 35 is incremented by a subsequent countup pulse 50 to specify the next storage location.

The output of writing address counter 35 is also coupled to a modulo 2N subtractor 38 to which is also applied an output from a reading address counter 36 to detect the difference in address count between the two counters. The output of the subtractor 38 is coupled to a decoder 40 which translates the differential count value to constantly monitor the amount of data words stored in RAM 32 for the purpose of detecting when RAM 32 is approaching an overflowed or underflowed condition so as to determine the rate at which the reading address counter 36 is to be incremented.

The stored data words are read out of RAM 32 into an output latch 33 on a per word basis from the locations specified by an address count supplied through selector 34 from reading address counter 36 in response to a readout enable pulse 48 supplied from a stabilized frequency clock source 60. The data latched in output latch 33 is delivered to the digital to analog converter 21 in response to a readout latch pulse 49 also supplied from clock source 60. These reading pulses 49 and 48 occur at intervals longer than the writing pulses 47 and 46 as is seen from Fig. 3 to expand the time dimension of the digital signal.Since the sync pulses are jitter affected by the time axis fluctuation of the video transport mechanism of the recorder 12 as are the information bits supplied to the latch 31 and since the reading pulses 48,49 are derived from the frequency stabilized.source, the data read out of RAM 32 contains no jitter components.

Reading address counter 36 is normally incremented at a standard rate in response to count-up pulses 52b supplied via a selector 39 from a standard frequency oscillator 44 which is -receptive of its input from clock source 60.

RAM 32 has a memory capacity needed to store an amount of data words which is likely to encounter when the latter is affected by jitter since it tends to reduce the effective number-of storable data-words. Thus, the memory capacity is determined so that the effective number can hardly become zero under severe jitter conditions creating an underflow condition while it is not much higher than the number of storable data words so that the data yet to be read out is caused to be rewritten with a fresh data word creating an overflow condition.

Assume that the memory capacity of RAM 32 is 2 data words (where N is an integer), storage locations are addressable by counts ranging from "O" to "2N~1 " and both counters 35 and 36 increment their count values from "0" to "2N--1" and returns to "O" again to repeat the process.

It is noted that the count value of writing address counter 35 always precedes the count value of reading address counter 36 and since RAM 32 has a memory capacity of 2N words, reading address counter 35 is not incremented to a value higher than the count value of writing address counter 36 by 2N~1.

Modulo 2N subtractor 28 provides modulo 2N subtraction of binary counts reached in writing and reading address counters 35 and 36 to detect the effective numer of data words storable in RAM 32. Decoder 40 checks the differential count value against a lower limit value which may be "1 ", for example, and generates an early warning signal indicating that RAM 32 is approaching an underflow condition and checks it against an upper limit value which may be "2"-2", for example, and generates an early warning signal indicating that RAM 32 is approaching an overflow condition.

The underflow warning signal is coupled to the set input of an underflow flip-flop, or flag, 42 to provide a logical "1" output to selector 39 to cause it couple count-up pulses 52a supplied from a lower frequency oscillator 43. The frequency of count-up pulses 52a is lower than the standard frequency and hence it is lower than the rate at which the data is delivered from the output latch 33. Thus, the reading address counter 36 is clocked at a reduced rate increasing the effective number, or differential count value and a given data word is repeatedly read out of RAM 32 because of the difference in reading rates between latch 33 and counter 36.Decoder 40 continues to monitor the instantaneous values of its input by c hecking it against an intermediate value, or onehalf of the memory capacity of RAM 32 and delivers a reset signal to the underflow flag 42 to return the reading rate to normal when the differential count value reaches one-half of the maximum storable data words.

A waveform 61, shown in Fig. 4, is a digital representation of the data words read out of RAM 32 at normal reading rate. When reading address counter 36 is clocked at the lower rate just described, the waveform 61 would be somewhat distorted as shown at 62 in which same data words are repeatedly read out in a range from the third to sixth addresses. However, the difference in digital value between adjacent data words is not substantial so that the waveform 62 can be considered to be continuous.

In a similar manner, if the differential count value reaches 2N--2, for example, decoder 40 will issue a signal that triggers the set input of an overflow flip-flop, or flag 41 to cause the selector 39 to couple count-up pulses 52c from a high frequency oscillator 45 which also takes its input from clock source 60. The frequency of the countup pulses 52c is higher than the standard frequency so that reading address counter 36 is incremented at a higher speed than RAM 32 is read out in response to latch pulses 49 (see Fig.

3). Thus, the differential count value decreases and alternate data words are skipped in a range from the fourth to sixteenth address as shown at 63 in Fig. 4 until the differential address count decreases to the predetermined intermediate value. Although this skipping operation can generate discontinuities, such discontinuities could be satisfactorily smoothed out for practical purposes by low-pass filters 23, 23b.

Claims

1. A circuit for controlling a memory adapted to store jitter-containing data words which are written thereinto at a rate corresponding to the rate of occurrence of said data words, comprising: a first address counter arranged to be incremented at said variable rate for generating a digital incremental value for addressing storage locations into which said data words are written; a second address counter normally arranged to be incremented at a standard constant rate for generating a digital incremental value for addressing storage locations out of which the stored data words are to be read; means for reading data words at said constant rate from the storage locations addressed by said second counter; means for detecting when the amount of data words stored in said memory reaches an upper or a lower limit; and means for controlling said second counter to increase or decrease its incremental rate upon the detection of said upper or lower limit, respectively.

2. A circuit as claimed in claim 1, wherein said detecting means comprises: means for detecting the difference between said incremental values of said first and second address counters; and means for generating a first control signal when said difference reaches an upper limit value and generating a second control signal when said difference reaches a lower limit value to cause said counter control means to increase or decrease said rate in response to said first or second control signal, respectively.

3. A circuit as claimed in claim 2, wherein said control signal generating means comprises: first and second flip-flops; and a decoder including means for triggering said first flip-flop into a set condition when said difference reaches said upper limit value and subsequently into a reset condition when said difference decreases to a value intermediate between said upper and lower limit values, and means for triggering said second flip-flip into a set condition when said difference reaches said lower limit value and subsequently into a reset condition when said difference increases to said intermediate value, the outputs of said first and second flip-flops being said first and second control signals, respectively.

4. A circuit as claimed in claim 1,2 or 3, further comprising: an input latch for latching therein jittercontaining input data words for delivery to said memory at said variable rate; and an output latch for latching therein data words read out of said memory at said standard constant rate.

5. A jitter elimination and time expansion circuit for processing a digital signal reproduced from a tape recording/reproducing system, wherein said digital signal is recorded and reproduced with a synchronization signal, said circuit comprising: a memory; means for writing said digital signal into said memory at a writing rate corresponding to said synchronization signal and reading the digital signal out of the memory at a standard constant rate lower than said writing rate; a first address counter arranged to be incremented at said writing rate for generating a digital incremental value for addressing storage locations into which said digital signal is written; a second address counter normally arranged to be incremented at said standard rate for generating a digital incremental value for addressing storage locations out of which said digital signal is read;; means for detecting when the amount of said storage locations in which said digital signal is stored reaches an upper or a lower limit; and means for controlling said second counter to increase or decrease its incremental rate upon the detection of said upper or lower limit, respectively.

6. A jitter elimination and time expansion circuit as claimed in claim 5, wherein said detecting means comprises: means for detecting the difference between said incremental values of said first and second address counters; and means for generating a first control signal when said difference reaches a predetermined upper limit value and a second control signal when said difference reaches a predetermined lower limit value to cause said counter controlling means to increase or decrease the incremental rate of said second address counter in response to said first or second control signal, respectively.

7. A jitter elimination and time expansion circuit as claimed in claim 6, wherein said control signal generating first and second flip-flops; and a decoder including means for triggering said first flip-flop into a set condition when said difference reaches said upper limit value and subsequently into a reset condition when said difference decreases to a value intermediate between said upper and lower limit values and means for triggering said second flip-flop into a set condition when said difference reaches said lower limit value and subsequently into a reset condition when said difference increases to said intermediate value, the outputs of said first and second flip-flops being said first and second control signals, respectively.

8. A jitter elimination and time expansion circuit as claimed in claim 5, 6 or 7, further comprising: an input latch for latching therein said digital signal in response to said synchronization signal for delivery to said memory at said variable rate; and an output latch for latching therein at said standard constant rate the digital signal read out of said memory.

9. A circuit for controlling a memory substantially constructed as hereinabove described with reference to Figs. 2 to 4.

10. A jitter elimination and time expansion circuit substantially constructed as hereinabove described with reference to the accompanying drawings.