GB2082843A - Electric Circuit Device - Google Patents
Electric Circuit Device Download PDFInfo
- Publication number
- GB2082843A GB2082843A GB8125160A GB8125160A GB2082843A GB 2082843 A GB2082843 A GB 2082843A GB 8125160 A GB8125160 A GB 8125160A GB 8125160 A GB8125160 A GB 8125160A GB 2082843 A GB2082843 A GB 2082843A
- Authority
- GB
- United Kingdom
- Prior art keywords
- edge
- substrate
- electrical circuit
- circuit component
- termination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 36
- 229910000679 solder Inorganic materials 0.000 claims description 24
- 238000007373 indentation Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000012777 electrically insulating material Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract description 6
- 238000000576 coating method Methods 0.000 abstract description 6
- 239000000919 ceramic Substances 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000002386 leaching Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000011195 cermet Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004873 anchoring Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0272—Adaptations for fluid transport, e.g. channels, holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09163—Slotted edge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09181—Notches in edge pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1034—Edge terminals, i.e. separate pieces of metal attached to the edge of the printed circuit board [PCB]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Details Of Resistors (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
An electrical circuit component having a ceramic substrate, with a thick or thin film circuit on at least one surface (11) and projecting termination leads anchored at locations (15) in an adjacent surface has a termination coating (21) extending over the edge (25) where the surfaces meet. To improve the conductivity of the termination coating at the edge (25), the substrate has indented areas, e.g. grooves (18), which intersect both surfaces to receive an extra thickness of edge termination material (20) so as to ensure good connection electrically between the leads and the deposited circuits. <IMAGE>
Description
SPECIFICATION
Electric Circuit Device
The invention relates to electrical circuit components.
There have been developed electrical circuit components comprising a substrate of insulating material and printed or otherwise deposited circuit elements on one or more surfaces of the substrate which is usually steatite, alumina or other ceramic based composition. Although the deposition of the materials for the electrically conductive material is usually quite sufficient on adjoining surfaces, it is difficult to ensure that there is an adequate thickness of deposited conductive edge termination material at the edge forming the junction of two adjacent surfaces. The edge termination material is for instance provided to connect the circuitry deposited on one surface of the substrate to termination leads extending outwardly from an adjacent edge surface.The edge termination material underlies the deposited circuit element(s) and under a solder layer on the adjacent surface to support projecting terminal leads. The circuitry may be relatively simple, as for instance, a resistor network, capacitor electrodes or may include relatively complex semiconductor portions in the form of attached chips or other devices which comprises a hybrid assembly.
Devices, such as those to be hereinafter described, are made in relatively large quantities and are preferably arranged for automated manufacture. That is, the leads are very often attached by using conventional lead frame preforms, or other support carriers for a multiplicity of leads, and are further anchored to the substrate by means of solder applied with well-known solder flow bath or similar facilities.
Thus, the leads may be initially held in place by wedging into openings in the substrate and transported through a solder flow bath, where the solder will cling to the inner ends of the leads and to deposited solder-accepting edge termination material applied to areas of a surface of the substrate. The solder does not adhere to other portions of the substrate or the circuit.
Techniques of this nature are disclosed in relation to electrical circuit components in our U.S.
PatentsNos.4127934;4187529;4213113; and 3 878 890 of which the first-mentioned patent relates to a single in-line packaging technique, (SIP), and the last-mentioned patent relates to a dual in-line package (DIP).
Inasmuch as the edge termination material is conventionally made from a material, such as silver, which tends to go into solution with a laterdeposited solder layer, there is always present the possibility of leaching away of edge termination material which has been deposited on the adjoining surfaces during soldering operations.
This deposition is usually applied by a transfer roller and often is thinnest at the relatively sharp edge at the intersection of two adjoining surfaces.
To increase the thickness of the edge termination material at these sharp edges, resort has been made to hand painting the edge, which is a vary expensive operation.
The applicants in researching this problem conceived of the present invention, which resides principally in providing an identation extending between the adjoining surfaces and traversing the aforementioned relatively sharp edge. The indentation may take the form of a simple notch in the edge or preferably is a groove extending from the surface from which project the terminal leads of conventional parallelepiped-formed dual
in-line or single in-line packaged components.
The groove is preferred because moulding dies used to press the ceramic substrate are easier to machine than dies with a plurality of relatively small protrusions as required to form notched areas in the substrate. These projections used for notching are also relatively small and subject to early abrasive wear during use of the dies.
The present invention contemplates a method and means for improving and maintaining electrical conductivity in the edge termination layer deposited on one surface of a substrate and extending over an edge. The material of the edge termination layer is conductive so as to join electrically circuit elements on one surface of the substrate and terminal leads extending outwardly from the adjoining surface. The material is compatible for electrical and mechanical connection with a solder layer for retaining and anchoring the respective lead. The substrate may be made of a ceramic material, such as alumina or steatite, and is pressed or otherwise formed to include an indented area, in the form of a notch or groove in accordance with the present invention.
The groove or notch is preferably formed in the substrate simultaneously with the pressing operation, but when necessary, and without departing from the invention, the groove or notch may be formed by abrasive, laser, or cutting operations after the substrate has been formed.
The indented areas ensure adequate deposition of the edge termination material penetrating the adjoining surfaces and the result may be compared with providing a conducting "wire" running from a terminal lead on one surface over the edge to the surface bearing the electrical circuit elements.
Thus, any effects of leaching away of termination material during the soldering operations will be minimized by ensuring adequate thickness of termination material as it extends across the sharp edge between the adjoining surfaces.
Some embodiments of the invention will now be described with reference to the accompanying drawings in which:
Figure 1 is a perspective view of a single in-line packaging substrate of this invention for use in an electrical component,
Figure 2 is a perspective view of the substrate of Figure 1 with a layer of edge termination material applied on it,
Figure 3 is a perspective view corresponding to
Figure 2 with a typical resistive network circuit deposited on the upper surface of the substrate,
Figure 4 is a perspective view corresponding to
Figure 3 showing the product finished with an applied conformal coating and with termination leads mounted and soldered in place,
Figure 5 is a perspective view of a substrate in accordance with the invention and provided for dual in-line packaging, and
Figure 6 is a perspective view, partly broken away, illustrating a finished dual in-line package device embodying a substrate of Figure 5.
One electrical circuit component of the present invention is illustrated in Figures 1-4. Figure 1 shows the substrate 10 which is in the form of a parallelepiped and which will have applied to it electrical circuit elements and terminal leads as will hereinafter be described. The insulating substrate 10 is pressed, or otherwise formed, from a ceramic material, such as alumina or steatite, to provide opposed upper and lower planar surfaces 11 which meet a side or edge surface 12 in an edge 25. This surface 12 is preferably planar and normal to the surfaces 1 1.
Either one or both of the surfaces 1 1 may have thereon electrical circuitry, which may be in the form of a network of resistors, a combination of resistors and capacitors and semiconductor chips, or chips of capacitors or the like. The circuitry is produced by known techniques which do not form a particular part of the present invention.
The side or edge surface 12 includes a plurality of spaced apart openings 1 5 traversing the substrate 10 from the surface 12 all the way through to the opposite edge 13. These openings or apertures 15 serve as sockets to receive terminal leads. For the purpose of spacing the edge surface 12 from a circuit board or other supporting means, the substrate 10 is provided with a pairofforwardly-projecting ribs 16 and 17.
The-surface 12 has in it indentations shown as grooves 18 which also bite into the planar surfaces 1 These indentations are an important part of the present invention. The grooves 1 8 are shown to be "V" shaped in section but alternatively they may be rounded off to a general "U" shape, or may be semicircular. Although another embodiment will be described, the present embodiment is preferred at this time, since it is more facilely and inexpensively provided under known moulding and pressing techniques.It will be apparent that the moulding dies for the substrate of Figures 1 to 4 with the continuous groove 18 extending across the entire depth of the edge surface 12 are more easily made than the dies for the substrate of Figures 5 and 6 which utilizes indentations in the form of notches, the notches necessarily being small when compared to the elongated grooves 18. For instance, the substrate of Figures 1 to 4 has approximate overall dimensions of 0.78"xO.30"xO.O8" with grooves 18 being approximately 0.01" wide at the outermost dimension. Obviously, notches such as 35 are smaller and the machining of pressing dies for forming this configuration is a complex operation.
As shown in Figure 2 the substrate 10 has applied on it edge termination areas 20 as by transfer printing using a transfer wheel which applies a conducting material such as silver paste.
The edge termination area 20 extends across the surface 12, and preferably slightly into the openings 15, and also overlaps the surface 11, as shown at 21. This overlapping area 21 connects the electrical circuitry to the edge of the substrate 10, as will later be explained. The material of the termination areas 20 (in this case silver paste) is well known, and is compatible with solder for connecting to terminal leads. After application, the silver paste edge termination material 20 is fired on the substrate in the usual fashion.
Particular attention is drawn to the fact that the termination material in the areas 20 nearly fills the grooves 18 to serve as a "wire-like" conductor passing from the holes or apertures 15 to the areas 21. This arrangement ensures adequate thickness of the edge termination material particularly at edge 25. It is well known that, although silver paste materials are ideal for serving as conductors and for compatibility with known solders, they also have the disadvantage of tending to migrate into molten solder. The solder, as will later be explained, is deposited in automatic equipment, as fully described in United
States Patent No. 4 127 934, using wave solder baths and other known automatic techniques.In as much as the entire process of depositing the edge termination areas 20 and later described soldering techniques is intended to be fully automatic, slight variations in processing can lead to the application of a relatively thin layer at the edge 25. This relatively thin coat will tend to leach away from the substrate and migrate into the later applied solder. The grooves 1 8 provided by this embodiment of the present invention result in the "wire-like" conductive paths to ensure proper conductivity between the areas 20 and 21.
Typical resistive networks 26 (Figure 3) may be laid down on the surface 11 by known techniques utilising thick or thin film material, such as the well-known cermet resistors materials, one of which is described in United States Patent No. 3 639 274. The particular composition does not form a part of the present invention.
The resistive areas when of cermet material are screen printed or otherwise deposited to extend over the previously laid down conductive paths 27 which extend to and overlap the edge termination areas 21. The conductive strips 27 are also of a glassy matrix in which highly conductive metallic materials are mixed. The layers may be fired individually or co-fired as desired. It is generally preferred to utilise for the conductive paths or layers 27 a material that resists adhesion of solder to assist in preventing adhesion of solder to areas of the substrate where it is unwanted. For this reason, it is also preferable to permit the material of layer 27 to slightly overlap the termination material 20 at the upper edge of the planar surface 12.
Terminal leads 30 (Figure 4) are inserted in each of the openings 1 5 as disclosed in United
States Patents Nos. 4 127 934, 4 187 529 and 4 213 113, and solder pads 31 are automaticailv applied by transporting the substrate 11 with the leads 30 attached thereto through a waveform solder bath (not shown). During this assembly process, the leads are preferably attached to a carrier strip of a lead frame (not shown).
It is preferred to provide a conformal coating 32 as a means of protecting the resistive and conductive layers 26 and 27. Identification (not shown) may be printed directly on the conformal coating 32. The solder pads 31 act both as conductive material and to anchor the terminal leads 30.
A second method of improving conductivity between surfaces is shown as applied to dual inline package (Figures 5 and 6) which comprises a substrate 40 having a surface 36 arranged to receive a thick or thin film network 42 comprising a resistive layer 43 connected to leads 44 by means of conducting paths 45 overlying edge termination material layers 46 which extend from the surface 36 over the edge 38 on to the edge termination material layers 47 on surface 37.
Solder pads 48 are applied as described in connection with Figure 4 to anchor the leads 44 and a conformal coating 50 is later applied.
To improve the conductivity between the layers 46, 47, notches 35 are formed in the edge 38 to extend into both the planar surfaces 37 and 38. On applying the layers 46, 47 the edge termination material fills the notches 35 giving increased thicknesses of the material at the edge and thus improved conductivity between the surfaces 46, 47. Thus the deleterious effects of "leaching" or migrating of silver into the solder as the solder is applied to retain the leads in place is minimized.
It will be apparent that either the grooves of
Figures 1-4, or the notches 35 may be utilised in either the SIP or the DIP devices with equal facility. The two different devices, i.e. SIP and DIP, are merely shown as examples to indicate broad application of the present invention, which also may reside in various configurations of indented areas traversing between two adjoining planar surfaces.
Although the invention herein has been specifically described in connection with devices having leads projecting from one or more sides of a substrate, it will also be understood that, such as in the case of certain hybrid circuits (not shown), the provision of the notches 35 or grooves 18 is equally applicable to devices which have no leads. In fact, the invention finds application in instances where solder is not applied. The channels defined by the notches 35 or grooves 18 provide a ready means of assuring adequate "flow" during printing or other deposition of a layer, such as the edge termination areas or portions 21 and 46.
Claims (6)
1. In or for an electrical circuit component comprising a substrate of electrically insulating material, the substrate having a first surface, the first surface and an adjacent surface meeting in an edge and having deposited on them and the edge electrically-conductive termination material; a form of the substrate characterised by one or more identations in the edge, each indentation opening to each of said surfaces to receive a thickness of deposited termination material greater than that on the surfaces providing good conduction across the edge.
2. In or for an electrical circuit component, a substrate as claimed in claim 1, characterised by the or each indentation being a channel or groove extending from the edge across said adjacent surface to the location for a terminal lead, one end of the channel or groove penetrating the first surface.
3. In or for an electrical circuit component, a substrate as claimed in claim 1, characterised by the or each indentation being a notch penetrating both said surfaces.
4. An electrical circuit component substantially as hereinbefore described with reference to and as illustrated in Figures 1 to 4.
5. An electrical circuit component substantially as hereinbefore described with reference to and as illustrated in Figures 5 and 6.
6. A method of manufacturing an electrical circuit component including the steps of forming a substrate of insulating material having a circuitsupporting planar surface and an adjoining planar surface, these surfaces meeting in an edge, and indentations in the edge intersecting both of said surfaces, depositing conductive edge termination material to occupy the indentations and to overlie adjacent portions of said surfaces of the substrate, depositing on said circuit-supporting surface a layer of electrical circuit elements with conducting portions thereof electrically connected to the edge termination material including occupied indentations, mounted at least one terminal lead to project from the adjoining planar surface, and depositing a layer of solder on said lead and on the edge termination material on the adjoining surface and in the indentations.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18132980A | 1980-08-25 | 1980-08-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2082843A true GB2082843A (en) | 1982-03-10 |
GB2082843B GB2082843B (en) | 1984-09-19 |
Family
ID=22663824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8125160A Expired GB2082843B (en) | 1980-08-25 | 1981-08-18 | Electric circuit device |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS5745962A (en) |
CA (1) | CA1151257A (en) |
DE (1) | DE3133584A1 (en) |
FR (1) | FR2489044A1 (en) |
GB (1) | GB2082843B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2248345A (en) * | 1990-09-27 | 1992-04-01 | Stc Plc | Edge soldering of electronic components |
CN112074095A (en) * | 2020-10-10 | 2020-12-11 | 黄石星河电路有限公司 | Thin plate processing method with 0.4MM metal half-holes designed around |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3406537A1 (en) * | 1984-02-23 | 1985-08-29 | Brown, Boveri & Cie Ag, 6800 Mannheim | ARRANGEMENT OF A PERFORMANCE SEMICONDUCTOR COMPONENT ON AN INSULATING AND PROVIDED SUBSTRATE |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3873890A (en) * | 1973-08-20 | 1975-03-25 | Allen Bradley Co | Terminal construction for electrical circuit device |
JPS5089874A (en) * | 1973-12-12 | 1975-07-18 | ||
CA1055134A (en) * | 1975-09-02 | 1979-05-22 | Lawrence D. Radosevich | Terminal lead construction for electrical circuit substrate |
-
1981
- 1981-05-26 CA CA000378327A patent/CA1151257A/en not_active Expired
- 1981-06-16 JP JP9166881A patent/JPS5745962A/en active Pending
- 1981-08-18 GB GB8125160A patent/GB2082843B/en not_active Expired
- 1981-08-18 FR FR8115884A patent/FR2489044A1/en active Granted
- 1981-08-25 DE DE19813133584 patent/DE3133584A1/en not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2248345A (en) * | 1990-09-27 | 1992-04-01 | Stc Plc | Edge soldering of electronic components |
GB2248345B (en) * | 1990-09-27 | 1994-06-22 | Stc Plc | Edge soldering of electronic components |
CN112074095A (en) * | 2020-10-10 | 2020-12-11 | 黄石星河电路有限公司 | Thin plate processing method with 0.4MM metal half-holes designed around |
Also Published As
Publication number | Publication date |
---|---|
FR2489044A1 (en) | 1982-02-26 |
CA1151257A (en) | 1983-08-02 |
GB2082843B (en) | 1984-09-19 |
JPS5745962A (en) | 1982-03-16 |
DE3133584A1 (en) | 1982-07-01 |
FR2489044B3 (en) | 1983-06-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19920818 |