GB2069787A - Semiconductor switching device - Google Patents
Semiconductor switching device Download PDFInfo
- Publication number
- GB2069787A GB2069787A GB8103251A GB8103251A GB2069787A GB 2069787 A GB2069787 A GB 2069787A GB 8103251 A GB8103251 A GB 8103251A GB 8103251 A GB8103251 A GB 8103251A GB 2069787 A GB2069787 A GB 2069787A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- transistor
- switching device
- semiconductor switching
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 230000003321 amplification Effects 0.000 claims abstract description 15
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005304 joining Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/04126—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in bipolar transistor switches
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
A semiconductor switching device comprises a main switching element, for example, a darlington transistor, and a speed up transistor. A current amplification factor of the speed up transistor is established less than 1 to dissipate the stored electric charge of the main switching element. <IMAGE>
Description
SPECIFICATION
Semiconductor switching device
This invention relates to a semiconductor switching device with an improved switching characteristic.
A darlington transistor has the advantage of being able to control high electric power using a very small signal by reason that it has a high current amplification factor (Ffe). A conventional darlington transistor is shown in Figure 1. The collector of a first transistor 1 is connected to the collector of a second transistor 2, and the emitter of transistor 1 is connected to the base of transistor 2. Resistors 3 and 4 are connected between the base and emitter of transistors 1 and 2, respectively. Resistors 3 and 4 are provided to avoid amplification of the leakage current generated between the collector and base of transistors 1 and 2 when there is a rise in temperature.Resistor 3 is usually set to a comparatively high value so that the current amplification factor does not decrease in accordance with flow of current in resistor 3 when transistor 1 is turned on. The joining point between the base of transistor 1 and resistor 3 is a base electrode B, the common joining point of the collectors of transistors 1 and 2 is a collector electrode C, and the joining point between the emitter of transistor 2 and resistor 4 is an emitter electrode E.
When positive base current le, flows from base electrode 1 transistors 1 and 2 are turned on. However, to dissipate the electric charge stored in transistors 1 and 2 in the ON state and switch to the OFF state, negative base current Is, must flow. This is preferably accomplished by applying a reverse bias voltage between base electrode B and emitter electrode Efortheturn-offtime. However, in general, in darlington transistors, the area of the emitter of transistor 1 is larger than that of transistor 2, so that the electric charge stored in transistor 1 is less than that stored in transistor2 and transistor 1 turns off faster than transistor 2.Consequently, the negative base current 1B2 only flows from transistor 2 through resistor 3, and the value of base current 1B2 is such that the value of resistor 3 is chosen to be comparatively large. Transistor 2 does not turn off as fast as transistor 1 because the stored electric charge does not dissipate naturally. Thus, turn-offtime is not reduced by the flow of the base current B2 In such a manner, it is difficult to operate at high speed as the switching times, especially the storage time (Tstg) and the fail time (Tf), are long in the darlington transistor. Therefore, in the known device shown in Figure 2, a diode 5 is connected between the base and emitter of transistor 1 and the cathode of diode 5 is connected to the base electrode B.Thus, if transistor 1 is turned off, the stored electric charge of transistor 2 can be dissipated through diode 5, and the storage time (Tstg) and fall time (Tf) are reduced.
Figure 3 is a plan view of a monolithic construction of the traditional darlington transistor provided with the above-mentioned diode. Figure 4 is a sectional view taken on line 3-3' of Figure 3, and similar elements of these figures are assigned the same reference numbers. Referring to Figures 3 and 4, a P-type layer 11 is formed on an N-type semiconductor substrate 10. Three separate N-type regions 12, 13 and 14 are formed in P-type layer 11. Transistor 1 (shown in
Figures 1 and 2) is composed of N-type region 12 as the emitter region, partial regions 1 la and 1 inc just under and near N-type region 12 as the base region, and N-type substrate 10 as the collector region.
Transistor 2 is composed of N-type region 14 as the emitter region, partial regions lit and 11dofP-type layer just under and near N-type region 14 as the base region, and N-type substrate 10 as the collector region.
A base electrode 15 is provided on the exposed surface of partial region 1 Ia. A connecting electrode 16 is provided on the exposed surfaces of N-type region 12 and P-type layer 11. The sheet resistance of partial region 1 1c positioned just under N-type region 12 serves as resistor3 (shown in Figures 1 and 2). The sheet resistance of partial region 1 1d positioned just under N-type region 14 serves as resistor4 (shown in Figures 1 and 2). One end of this resistor is a shorted emitter portion 17. This shorted emitter portion 17 is connected to an emitter electrode 18 provided on the surface of N-type region 14.
The above-mentioned diode 5 (shown in Figure 2) is composed of N-type region 13 and a partial region 1 lie positioned just under and near region 13. An electrode 19 is provided on the exposed surface of
N-type region 13 as the cathode region of the diode, and is connected to base electrode 15. The exposed surface of partial region 1 lie which is used as the anode region of the diode is connected to connecting electrode 16. A collector electrode 20 is provided on the opposite surface of N-type substrate 10. In this arrangement, diode 5 (shown in Figure 2) is a part of an NPN transistor 21 (shown in Figure 5) which comprises N-type region 13 as the emitter region, partial region 11e as the base region and N-type substrate 10 as the collector region.
Figure 5 is the equivalent circuit of the device shown in Figure 4, and similar elements are assigned the same reference numbers as in Figures 1 and 2. If a reverse bias voltage is applied between emitter electrode E and base electrode B to turn off the darlington transistor, transistors 1 and 2 have the reverse bias voltage applied to them but transistor 21 has a forward bias voltage applied to it. Therefore, transistor 21 turns on and the collector current flows through this transistor 21. A new electric charge is thus stored in transistor 21. Thus, even if diode 5 (shown in Figure 2) is included in the darling- ton circuit, the switching speed in not increased.
An object of this invention is to provide an improved semiconductor switching device with increased switching speed, especially to free the stored electric charge in the semiconductor switching device during turn-off.
According to the present invention, a semiconduc
The drawings originally filed were informal and the print here reproduced
is taken from later filed formal copies.
tor switching device comprises a main semiconductor switching element and a speed up transistor connected to said main switching element, the current amplification of said speed up transistor being less than 1.
According to a second aspect of the present invention, a semiconductor switching device comprises a first region having a first conductivity type, a second region having a second conductivity type formed on the surface of said first region, a third and fourth region each having a first conductivity type formed separately from each other in the surface of said second region, a fifth region having a second conductivity type and an impurity density higher than 3 x 10'8/cm3 formed in the surface of said second region between said third and fourth regions and connected to said third region, and a sixth region having a first conductivity type and an impurity density higher than said fifth region formed in the surface of said fifth region and connected to said second region.
In order that the invention may be more readily understood, it will now be described, by way of example only, with reference to the accompanying drawings, in which:
Figures 1 and 2 are circuit diagrams of a prior art semiconductor switching device,
Figure 3 is a plan view of a prior art semiconductor device,
Figure 4 is a cross-sectional view taken on line 3-3' of Figure 3,
Figure 5 is an equivalent circuit diagram of the device shown in Figure 4,
Figure 6 is a cross-sectional view of an embodiment of this invention,
Figure 7 is a diagrammatic view of an impurity profile taken on line 6-6' of Figure 6, and
Figure 8 is a cross-sectional view of another embodiment of this invention.
This invention is based on the discovery that it is possible to raise the switching speed of a semiconductor switching device by changing a specific characteristic of a speed up transistor connected to the main switching element, namely, the speed up transistor must not operate normally, and the normal current amplification factor of this speed up transistor must be reduced to less than 1.
Figure 6 illustrates a sectional view of an embodiment of this invention. Similar elements of Figures 4 and 6 are given the same reference numbers. P-type layer 11 is formed in N-type semiconductor substrate 10. Two separate N-type regions 12 and 14 are formed in the surface of P-type layer 11. A highly doped P-type region 22 is formed in the surface of the P-type layer between the two N-type regions 12 and 14, and the impurity density of this region 22 is established higher than 3 x 10'8/cm3.
A highly doped N+#-type region 23 which has a
higher impurity density more than the above
mentioned highly doped P-type region 22 is formed
in the surface of region 22.
Transistor 1 enclosed by the dotted line is com
posed of N-type region 12 (emitter), partial regions
la and lic (base) and N-type substrate 10 (collector).
Transistor 2 is composed of N-type region 14 (emitter), partial regions 11b and 11d (base) and N-type substrate 10 (collector). Speed up ti-ansistor 21 is composed of highly doped no-type region 23 as the emitter region, highly doped P±type region 22 and partial region 1 1e as the base region and N-type substrate 10 as the collector region. Partial regions 1 1c and 1 le, just under and near N-type region 12, serve as resistor3 (shown in Figure 5) and partial regions ill and Ilb, just under and near N-type region 14, serve as resistor4 (shown in Figure 5).
A base electrode 15 is formed on the exposed surface of partial region 1 la. A connection electrode 24 is formed on the exposed surfaces of N-type region 12, partial region 1 1t and highly doped P±type region 22. An electrode 25 is formed on the surface of highly doped N±type region 23, and this electrode 25 is connected to base electrode 15. An emitter electrode 18 is formed on the exposed surface of N-type region 14. A collector electrode 20 is formed on the other surface of N-type substrate 10. An oxide film 26 protects the exposed P-N junctions. The equivalent circuit of the embodiment shown in Figure 6 is the same as Figure 5.
In the embodiment of this invention shown in Figure 6, the current amplification factor (hue) of speed up transistor 21, formed parasitically, is less than 1 since the impurity densities of highly doped N+region 23 and P-region 22 are very high. The reduced current injecting efficiency caused by the high density of the impurities and the reduced lifetime caused by Auger-recombination in the base region result in a low current amplification factor (H#). Speed up transistor 21 has only the baseemitter junction as an effectve PN junction. Thus the stored electric charge of the transistor 2 is effectively dissipated through speed up transistor 21 when the transistor 1 is turned off.The result is a reduced switching speed, particularly the storage time (Tstg) and fall time (Tf) are reduced and the switching speed of the darlington transistor is raised. The manufacturing method of this embodiment can be without major changes in steps. Highly doped
P±type region 22 is formed simultaneously with the
P±region for the ohmic contact, and thereafter highly doped N±region 23 is formed.
Figure 7 is a diagrammatic view of an impurity profile taken on line 6-6' of Figure 6 showing the device made by three diffusion steps.
In this Figure 7, the axis of abscissa expresses the distance (L1) in depth direction of N±type region 23, the distance (L2) in depth direction of P±type region 22, the distance (L3) in depth direction of P-type region 11, and the distance (L4) in depth direction of
N-type substrate 10. The axis of the ordinate expressesthe impurity density. Then, P-type region is indicated as the region having an impurity density higherthan 3 x 10181cm3.
In general, the following equation determines the current amplification factor (Hfe) of the NPN type transistor:
wherein:
WB is the width of the base,
Dp is the average value of the diffusion constant of holes, Dn is the average value of the diffusion constant of electrons,
Ln is the diffusion length of electrons into the base region, and QE and QB are effective electric charge densities of the emitter and base regions respectively.
It is necessary for the sum of the first and second parts of the above-mentioned equation to be greater than 1 in order to reduce the current amplification factor (He) to less than 1. One of the methods to real iso this purpose is that the impurity density of the emitter region is made lower than that of the base region. However, this method makes the process very complex because it must first reduce the surface impurity density of the base region by outdiffusion, etc., and must make the emitter region of lower impurity density than the base region.
Applicants have manufactured the darlington transistor having the profile shown in Figure 7.
Namely, Pf diffusion is done to a depth of 1 Oiim (L2)m with the surface impurity density being 2 x 1 019/cm3 on the wafer having the thickness Xjp (L1+L2+L3) 40,am. Thereafter, NF diffusion is done to the depth of 2.5clam (L1), with the surface impurity density being 1-2 x 1020/cm3 thereon, and the PN junction is made. The current amplification factor is thus 0.9.
By reducing the current amplification factor (H > e) of the device having the profile shown in Figure 7 to less than 1 the band gap narrowing resulting from the high impurity density of the emitter region reduces the injection efficiency, and increases the effect of Auger-recombination. The influence on the injection efficiency by the band gap narrowing becomes remarkable when the impurity density is higher than 1.85 x 1019/cm3. The influence on the lifetime of the electron by Auger-recombination becomes remarkable when the impurity density is higher than 3 x 1 0'9/cm3. Thus, the current amplification factor (Hf,) of transistor 21 formed parasitically can be less than 1, while the transistor reverse breakdown voltage is approximately 5 volts. This characteristic is practical.
Figure 8 illustrates another embodiment of this invention, especially applied to a gate turn-off thyris- tor. Similar elements as those of Figure 6 are given the same reference numbers and the detailed explanation is abbreviated. In Figure 8, the N-type substrate 10 of Figure 6 is replaced by two layers, a P-type region 30 and an N-type region 31, the base electrode is changed to gate electrode G, the emitter electrode changed to cathode electrode K, and the collector electrode changed to anode electrode A.
Nf -type region 23, P-type region 11, N-type region 31 and P-type region 30 define a parasiticthyristor, and this parasitic thyristor has the parasitic speed of the transistor which is composed of regions 23, 22, 11 and 31. This transistor has a current amplification factor less than 1, and does not operate as a normal transistor. The stored electric charge of the base region is dissipated smoothly through this transistor.
Although only a few exemplary embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications, for example, the changes of the conductivity type of the above-mentioned embodiments, are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the following claims.
Claims (8)
1. A semiconductor switching device comprising a main semiconductor switching element and a speed up transistor connected to said main switching element, the current amplification factor of said speed up transistor being less than 1.
2. A semiconductor switching device as claimed in claim 1, wherein said main switching element is a darlington transistor.
3. A semiconductor switching device as claimed in claim 1, wherein said main switching device is a thyristor.
4. A semiconductor switching device as claimed in claim 1, 2 or 3, wherein the said speed up transistor includes highly doped emitter and base regions having high impurity densities and the density of said base region being largerthanthatofsaid emitter region.
5. A semiconductor switching device as claimed in claim 4, wherein said density is higher than 3 x 1 0'8/cm3.
6. A semiconductor switching device comprising a first region having a first conductivity type, a second region having a second conductivity type formed on the surface of said first region, a third and fourth region each having a first conductivity type formed separately from each other in the surface of said second region, a fifth region having a second conductivity type and an impurity density higher than 3 x 0'3/cm3 formed in the surface of said second region between said third and fourth regions and connected to said third region, and a sixth region having a first conductivity type and an impurity density higher than said fifth region formed in the surface of said fifth region and connected to said second region.
7. A semiconductor switching device as claimed in claim 6, wherein said first region is divided into two regions having different conductivity types.
8. A semiconductor switching device substantially as hereinbefore described with reference to
Figures 6,7 and 8 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1615280A JPS56112751A (en) | 1980-02-13 | 1980-02-13 | Switching element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2069787A true GB2069787A (en) | 1981-08-26 |
| GB2069787B GB2069787B (en) | 1985-01-03 |
Family
ID=11908523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8103251A Expired GB2069787B (en) | 1980-02-13 | 1981-02-03 | Semiconductor switching device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS56112751A (en) |
| CA (1) | CA1154172A (en) |
| DE (1) | DE3104743C2 (en) |
| GB (1) | GB2069787B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304823A (en) * | 1991-12-30 | 1994-04-19 | Texas Instruments Incorporated | An equipment protection semiconductor integrated circuit |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126959A (en) * | 1980-03-12 | 1981-10-05 | Nec Corp | Semiconductor device |
| JPS62198148A (en) * | 1986-02-25 | 1987-09-01 | Sanyo Electric Co Ltd | Semiconductor device |
| DE3631957A1 (en) * | 1986-09-19 | 1988-03-31 | Siemens Ag | Circuit arrangement for turning off transistors in a Darlington circuit |
| JPH05243259A (en) * | 1992-03-03 | 1993-09-21 | Mitsubishi Electric Corp | Bipolar transistor, manufacture thereof, darlington transistor and manufacture thereof |
-
1980
- 1980-02-13 JP JP1615280A patent/JPS56112751A/en active Granted
-
1981
- 1981-02-03 GB GB8103251A patent/GB2069787B/en not_active Expired
- 1981-02-10 CA CA000370458A patent/CA1154172A/en not_active Expired
- 1981-02-11 DE DE19813104743 patent/DE3104743C2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5304823A (en) * | 1991-12-30 | 1994-04-19 | Texas Instruments Incorporated | An equipment protection semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3104743A1 (en) | 1982-01-07 |
| CA1154172A (en) | 1983-09-20 |
| JPS56112751A (en) | 1981-09-05 |
| GB2069787B (en) | 1985-01-03 |
| DE3104743C2 (en) | 1983-12-22 |
| JPS625346B2 (en) | 1987-02-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19990203 |