GB2063627A - Arrangement for determining a data slicing level for a bi-amplitude data pulse signal - Google Patents

Abstract

An arrangement for determining a data slicing level for a bi- amplitude data pulse signal comprising a framing code consisting of a plurality of data pulses forming a unique binary pattern followed by a sequence of coded data pulses. A register 30, which is initially set at zero, and a D-to-A convertor 31 provide an initial value of control voltage Vc for determining an initial slicing level. A register 19 records the framing code pattern during each framing code period as determined by a timing control element 34. The two types of error in the framing code pattern that is '1's received as '0's and '0's received as '1's are added in respective adder circuits 20 and 25 and the two totals S<1> and S<0> are summed in an adder circuit 27. A comparator 27 compares the total error SIGMA with a predetermined number M provided by a selector 28. Each time SIGMA > M, a gate 29, controlled by element 24, applies a stepping signal to the register 30. The count in the register 30 is fed to an adder circuit 32 where the error difference S<0>-S<1>, as determined by a subtractor circuit 33, is added to the register count. The new register number is then fed back to register 30 to modify the control voltage Vc. <IMAGE>

Description

SPECIFICATION Electrical data pulse slicing This invention relates to electrical data pulse slicing and more particularly to an arrangement for determining a data pulse slicing level.

The invention has a particular but nonexclusive application in television receiver apparatus in or for use in a television system of a character in which coded data pulses pertaining to alpha-numeric text or other message information are transmitted in a video signal in at least one telephone line in field-blanking intervals where no picture signals pertaining to normal picture information are present.

A television system of the above character is described in United Kingdom patent specification 1,370,535. A conventional television receiver for the system includes or has associated with it additional means comprising a data acquisition circuit to extract the coded data pulses from a received video signal. The extracted coded data pulses are stored in a storage device of the additional means and after a plurality of frame periods an entity of related message information, for example a page of text, has been received and stored.

The additional means also includes a decoding circuit for converting the stored message information, as read out from the storage device, into a video signal which is used to cause the display of the message information at the television receiver.

In the implementation of a practical data acquisition circuit for extracting coded data pulses from a received video signal, a difficulty that arises is to determine in the data acquisition circuit a suitable bias voltage level, relative to the received signal level, which serves as a so-called "slicing level". Pulse amplitudes in the received video signal are extracted in each pulse period as data pulses of one of two binary values (i.e. as 'l's or 'O's) according as the pulse amplitudes are greater than or less than the slicing level.

It is known to provide in the data acquisition circuit a data slicing arrangement which clamps the received video signal and slices it at a fixed d.c. level. However, this data slicing technique imposes the limitation that the level of the received video signal has to remain fairly accurately related to the fixed d.c. level at all times, which can cause problems, in particular when video signals may be received from different transmission sources.

With a view to avoiding the above limitation, adaptive data slicing techniques have been proposed. In a first known adaptive data slicing arrangement the slicing level is set automatically mid-way between positive and negative peaks of the received video signal and is corrected as necessary for each successive data pulse. In a second known adaptive data slicing arrangement, for use where a block of coded data pulses is preceded by a sequence of clock run-in pulses, the slicing level for the entire block of coded data pulses is set to be the mean amplitude of the pulses that form the clock run-in sequence.

These two known adaptive data slicing arrangements mentioned above have, in particular, been developed for a data acquisition circuit for receiving Teletext data as broadcast in the United Kingdom by the B.B.C. and the l.B.A. using their respective CEEFAX and ORACLE data transmission systems which are of the character previously referred to and which operate within the broadcast standards for the 625-line domestic television system as employed in the United Kingdom. In these two data transmission systems, television lines which contain a block of coded data pulses are referred to as television data lines.

A feature of these two data transmission systems is that the block of coded data pulses contained in each television data line includes, immediately after a sequence of clock run-in pulses for the lines, a plurality of pulses which are the same for each television data line and which form a "framing" or "start" code.

This framing code is used in a Teletext television receiver for synchronising the receiver's operation to receive the rest of the block of coded data pulses.

It is an object of the present invention to provide for a block of coded data pulses commencing with such a framing code an improved arrangement for determining a data slicing level, utilising the framing code.

According to the invention there is provided an arrangement for determining a data slicing level for slicing data in the form of a biamplitude binary data pulse signal comprising a framing code consisting of a plurality of data pulses forming a unique binary pattern followed by a sequence of coded data pulses, which arrangement is characterized in that it comprises: slicing level means for determining an initially preset data slicing level, means for recording from a data pulse signal that has been received using the preset data slicing level the 1 and 0 binary pattern of the data pulses that occur in a time period allocated to the framing code in the data pulse signal, means for determining whether this recorded pattern is an acceptable framing code pattern in that it contains less than a given number of bit errors, means for determining whether the recorded pattern, if acceptable, contains more O's recorded as 1 's or more 1 's recorded as O's relative to the correct framing code pattern, and means for causing increase or decrease of the data slicing level from its preset level to a corrected level according as, respectively, the recorded pattern contains more O's recorded as 1 's than 1 's recorded as O's, the increase or decrease being in proportion to the extent of the error, and the slicing level means supplying the corrected data slicing level for data slicing the coded data pulses that follow the framing code.

Thus, an arrangement according to the invention functions on the premise that if the initially preset data slicing level is too low relative to the bi-amplitude levels of the received data pulse signal, then there will be a tendency for O's to be decoded as 1 's, and an increase in the data slicing level will tend to correct the error in this sense. On the other hand, if the initially preset data slicing level is too high then there will be a tendency for 1 's to be decoded as O's and a decrease in the data slicing level will tend to correct the error in this opposite sense.

Where, as in the CEEFAX and ORACLE data transmission systems previously referred to, the data pulse signal includes a sequence of clock pulses (i.e. clock run-in pulses) preceding the framing code, the said time period may be extended to include at least part of this clock pulse sequence, whereby the number of bits in the recorded pattern is increased by such part of the clock pulse sequence.

The invention also extends to an arrangement for determining a data slicing level as set forth above, embodied in a television receiver for a television system of the character referred to. Such a television receiver can be adapted to display alpha-numeric text or other message information concurrently with, or as a selectable alternative to, normal picture information.

In order that the invention may be more fully understood reference will now be made by way of example to the accompanying drawings, of which: Figure 1 is a block diagram of a television transmission system of the character referred to; Figures 2 (a), 2 (b) and 2 (c) show explanatory diagrams relating to the data pulse coding and transmission of alpha-numeric text or other message information by the system of Fig. 1; and Figure 3 is a block diagram of an arrangement according to the invention for determining a data slicing level.

Referring to Fig. 1 of the drawings, which shows diagrammatically a television transmission system of the character referred to having a television receiver arrangement which is for displaying selectively either a television picture which is produced from picture information in a normal broadcast or cable television video signal, or alpha-numeric text or other message information which is produced from coded data pulses which are transmitted in the video signal in vertical or field-blanking intervals thereof. The possibility can also exist for displaying such message information concurrently with a television picture, for instance as sub-titles or captions which are superimposed on the television picture.

An incoming television video signal VS appears at an input lead 1 of the television receiver arrangement via its front end 2 which comprises the usual amplifying, tuning i.f.

and detector circuits.The front end 2 is assumed to be adapted to receive the video signal VS from a television transmitter 3 via a conventional over-air broadcast or cable transmission link 4. The transmitter 3 includes in known manner means for producing television picture information, means for producing alpha-numeric text or other message information, and further means for generating the appropriate composite television video signal containing picture signals representative of the picture information, and coded data pulses representative of the message information, together with the usual synchronising, equalizing and blanking signals which are necessary for the operation of the television receiver arrangement.

For normal picture display in the television receiver arrangement, the received video signal VS is applied to a selector circuit 5 which includes a selector switch 6. When the switch 6 is closed, the video signal VS is applied to a colour decoder 7 which produces the R,G and B component signals for the picture display, these component signals being applied via a video interface circuit 8 to the red, green and blue guns of a colour television picture tube 9. Scanning circuits 10 for the tube 9 receive the usual line and field synchronising pulses LS and FS from a sync. separator circuit 11 which extracts these synchronising pulses from the incoming video signal VS.

Coded data pulses representing message information in the video signal VS do not affect the picture display because they occur in one or more lines in the field-blanking interval when there is no picture display. Of the lines occurring in the field-blanking interval, most of them could be used to transmit coded data pulses reqresenting message information. However, in the BBC/IBA Teletext System at present, only lines 17/18 of even fields and lines 330/331 of odd fields of the 625 line broadcast television system are used in the United Kingdom. (See "Broadcast Teletext Specification", September, 1976, published jointly by the British Broadcasting Corporation, Independent Broadcasting Authority and British Radio Equipment Manufacturer's Association).

The video signal VS on the input lead 1 is also applied to a data acquisition circuit 12 which includes a data clock pulse generator (not shown) for deriving in known manner a data clock pulse train from the coded data pulses representing the message information.

It is assumed that the message information represented by the coded data pulses contained in the video signal VS is divided into different pages of information, and that each page is for display as a whole on the screen of the picture tube 9, with the coded data pulses for each page of information being repeated periodically in a recurrent cycle with or without updating of the information. It is further assumed that each page of message information is identified by means of a unique page address code which is included in the coded data pulses and defines the page number. The television receiver arrangement includes a code selector circuit 1 3 which controls the particular coded data pulses that are acquired by the data acquisition circuit 1 2 at any time.

(This control is indicated by a broad-arrow connection n representing the presence of a group of n parallel channels which form an nbit channel link for carrying n bits of information required for data selection-other groups of parallel channels forming multi-bit channel links in the television receiver arrangement are represented similarly as m, p, q and r numbers of channels and bits).

The acquired coded data pulses are clocked serially into the data acquisition circuit 1 2 by the data clock pulse train produced in the latter. From the data acquisition circuit 12, the acquired coded data pulses are fed in parallel groups of m bits to a data store 14. It is assumed that an mbit character byte is required for each character (or other item of information) contained in the message information. If for example, m =8, a character byte would comprise a character code consisting of 7 bits plus a single parity bit. The data store 14 can store a complete page of message information. In a typical Teletext transmission, each page of message information would contain up to 24 rows of characters, with each row containing up to 40 characters.

Thus, in order to identify the different characters of a page, it is furthermore assumed that the coded data pulses also include an address code for each character, this address code employing r bits and being fed to the data store 14 over an rbit channel link to control the storage therein of the character codes.

In view of the restricted transmission time which is available for transmitting the coded data pulses representing message information, for instance, sufficient time to transmit the coded data pulses for only one character row during a television line in the field-blanking interval, character data for a page of message information has to be stored row-by-row in the data store 14 over a relatively large number of television fields. This storing of character data row-by-row in the data store 14 is under the control of the address codes received from the data acquisition circuit 1 2 over the rbit channel link.

A character generator 1 5 of the television receiver arrangement is responsive to character data read out from the data store 14 to produce character generating data which can be used to derive what is effectively a new picture signal for displaying the characters represented by the stored character data. As mentioned previously, different characters are assumed to be represented by respective mbit bytes. The bits of the character code in each byte are fed in parallel from the data store 14 to the character generator 1 5 over a pbit channel link (p = 7).A character format for characters to be displayed can be a co-ordinate matrix composed of discrete elements arranged in rows and columns, this format being derived from a "read-only" memory which serves as the character generator 1 5 and which provides bits of character generating data in rows and columns, one row at a time. Since the character generating data is required as a modulation of a video signal in order to produce selective bright-up of the screen of the picture tube 9 to achieve character display, the character generating data is produced serially (as 1 's and O's) by using a parallel-to-serial convertor 1 6 t6 convert each row of bits of data read out from the character generator 15 (e.g. g= 5) into serial form.

In order to effect character display on the screen of the picture tube 9 using standard line and frame scans, the logic of the television receiver arrangement in respect of character display is so organised that for each row of characters to be displayed, ali the characters of the row are built up television line-bytelevision line as a whole, and the rows of characters are built up in succession. It thus takes a number of television lines to build up one row of characters.In the first television line concerned, character data read out from the data store 14 to the character generator 1 5 would cause the latter to produce character generating data in respect of the first row of discrete elements for the first character of the row, then in respect of the first row of discrete elements for the second character, and so on for the successive characters of the row. In the next television line, character generating data in respect of the second row of discrete elements for each character of the row would be produced in turn, and so on for the remaining television lines concerned.

The logic of the television receiver arrangement is organised by means of a clock pulse and timing pulse chain circuit 1 7 which provides appropriate clock and timing pulses to the data store 14, to the character generator 15, and to the data acquisition circuit 1 2. The circuit 1 7 is synchronised in operation with the scanning circuits 10 of the picture tube 9 by the line and field synchronising pulses LS and FS extracted from the incoming video signal VS by the sync. separator circuit 11.

The output from the convertor 1 6 is applied to a colour coder 1 8 which produces R', G' and B' component signals for character display, these component signals being also applied to the video interface circuits 8. The colour coder 1 8 can be controlled (in a manner not shown) by selected items of the char acter data in the data store 14 to provide a controlled colour character display. Of course, black-and-white picture and character display is also possible, in which event the colour decoder 7 and colour coder 1 8 would be omitted.

Fig. 2 (a) shows a waveform diagram which represents a Teletext television video signal for one television line which occurs in a fieldblanking interval and which includes coded pulse data. In this waveform diagram the line synchronising pulse for the television line concerned is represented at LS1, and the line synchronising pulse for the next television line is represented at LS2. The colour burst on the television line concerned and that on the next television line, are represented at CB1 and CB2, respectively. Assuming the television broadcast standards for 625-line systems as employed in the United Kingdom, the period of one television line (i.e. the period between the leading edges of successive line synchronising pulses) is 64 yes., as indicated.Further assuming the standard adopted in the United Kingdom for information transmission by digitally coded pulses in the field-blanking interval of such a 625-line system, then the television line shown would be line number 1 7 or 18 in an even field and line number 330 or 331 in an odd field. Such a television line is referred to as a television data line (as aforesaid) and can contain coded data pulses representing 360 binary bits which may be considered as 45 eight-bit bytes. The position of the coded pulse data in the television data line is indicated at CPD. The binary bit signalling rate is approximately 7Mbits/s, and the binary bit signalling levels are defined between a black level BL and a peak white level WL. The binary '0' level is the black level BL and the binary '1' lever is the level L.

Fig. 2 (b) shows a possible format for coded pulse data in a television data line. As mentioned above, the binary bits representing the coded pulse data are divided up into eight bytes 1,2 2,.... 20 ..... The first two bytes 1 and 2 comprise a sequence of clock run-in pulses which in the present example consist of a sequence of alternating bits 10101010/10101010. The third byte 3 comprises a framing or start code, e.g.

11100100, which a television receiver arrangement has to identify before it will respond to accept message information which is contained in the remaining eight-bytes 4, 5 20 . . . This identification of the framing code is effected (in known manner not shown) in the television receiver arrangement of Fig.

1 by the data acquisition circuit 12. The framing code is also used for the performance of the invention, as will be described next with reference to Fig. 3.

Fig. 2 (c) shows in idealised form the first part of a video signal waveform for a television data line showing the sequence of clock run-in pulses CL and the sequence of pulses which comprise the framing code FR. The first few coded data pulses which represent alphanumeric characters or other message information are shown at DP. The line synchronising pulse is represented at LS and the colour burst at CB.

In order to determine a slicing level for the incoming video signal waveform the arrangement shown in Fig. 3 is provided in the data acquisition circuit 1 2. This arrangement comprises a shift register 1 9 with serial input to which the received video signal VS is applied and a clock input to which are applied the data clock pulses dcp, which as aforesaid, are derived in known manner in the data acquisition circuit 1 2 from the coded data pulses in the received video signal VS.Each of the eight stages of the register 1 9 has an individual output of which, those pertaining to register stages that should contain a binary '0' of a correct framing code (i.e. 11100100) are connected to a first adder circuit 20, and those pertaining to register stages that should contain a binary '1' of a correct framing code are connected via respective invertor circuits 21-24 to a second added circuit 25. Thus, if a framing code has been received correctly, the register 1 9 will pass only binary O's to the adder circuit 20 and, likewise, the invertors 21-24 will pass only binary O's to the adder circuit 25.However, if any of the O's in the framing code have been received as 1's, then the register 1 9 will pass such 1 's to the adder circuit 20, whereas if any of the 1's in the framing code have been received as O's, then the invertors 21-24 wili pass corresponding 1's to the adder circuit 25.

The adder circuit 20 counts the number of 1 's applied to it and produces a 3-bit binary code S of the number, which is applied to a first set of inputs of a third adder circuit 26.

Likewise, the adder circuit 25 counts the number of 1's applied to it and produces a 3bit binary code S1 of the number, which is applied to a second set of inputs of the third adder circuit 26. In response to the codes SO and S1 the adder circuit 26 produces a 4-bit binary code 2: (= SO + S1) which represents their arithmetic total. The code 2; is applied to a first set of four inputs of a comparator circuit 27 to a seocnd set of four inputs of which is applied a 4-bit binary code M which represents a given number of bit errors. The code M is supplied by a manually preset switching device 28. If the number of bit errors in a received framing code is less than said given number (i.e. l; < M), then the comparator circuit 27 produces on output signal which is applied via an AND-gate 29 to the 'clock' input of a register 30.

This eight-stage number register 30 contains a number which is initially set to zero.

This number is supplied in binary form from the register stages to a digital-to-analogue convertor circuit 31 which is responsive thereto to produce a control voltage Vc which forms or determines a preset data slicing level for the data acquisition circuit (1 2 - Fig. 1).

The outputs of the number register 30 are connected to a set of eight inputs of an adder circuit 32. A set of four inputs of the circuit 32 is connected to the outputs of a subtractor circuit 33, to first and second sets of inputs of which are applied the 3-bit binary codes S and S', respectively. The subtractor circuit 33 is responsive to these codes S and S' to produce a resultant number in a 4-bit binary code which represents the algebraic difference between S and S' (i.e. SO-S'). This resultant number is added by the circuit 32 to the number given by the register 30 to produce a corrected number which is returned to the number register 30. As a result, the control voltage Vc is increased or decreased accordingly, to correct the data slicing level for the data acquisition circuit.

Since the register 30 is clocked by the output of the comparator 27, correction of the number held in the register 30 will occur only when the condition "E < M" is detected.

Furthermore, only those occurrences of Z < M which occur in an appropriate time period will be recognised, others being inhibited by the AND-gate 29. For this latter purpose, a second input of the AND-gate 29 is connected to the output of a timing control element 34.

This timing control element 34 determines, in response to input signals applied selectively to inputs 35, a time period for which the ANDgate 29 is open. This time period occurs in a television data line in the two-byte period which is occupied by the framing code (see Fig. 2 (b)). To achieve this the timing control element 34 can be arranged in known manner to produce an output signal to the AND-gate 29 in response to the line synchronising pulse LS applied to it, the output signal being produced after a suitable trigger delay and being terminated at the end of said time period. Depending on the frequency at which the data slicing level is to be corrected, the output signal from the element 34 may be produced in respect of each television data line, or in respect of each television field or frame, or possibly only in respect of each row or page of message information.Appropriate further input signals (e.g. the field synchronising pulse FS and row and page signals R, P) applied to the inputs 35 determine the frequency.

Therefore, it can be seen from the foregoing description that an arrangement according to the invention affords the advan'tage that if the initially preset data slicing level is too low then there will be an increase of the data slicing level to correct the tendency for O's to be coded as 1 's and, conversely, if the initially preset data slicing level is too high then there will be a decrease of the data slicing level to correct the tendency for 1 's to be decoded as O's. The time period determined by the timing control element 34 may be increase to include at least part of the clock pulse sequence which precedes the framing codes, the register 1 9 then including an appropriately increased number of stages for registering the additional 0 and 1 bits. The adder circuits 20 and 25 then have these additional bits to process, which gives the advantage of increased accuracy in determining the number of possible bit errors.

Claims (5)

1. An arrangement for determining a data slicing level for slicing data in the form of a bi-amplitude binary data pulse signal comprising a framing code consisting of a plurality of data pulses forming a unique binary pattern followed by a sequence of coded data pulses, which arrangement is characterised in that it comprises: slicing level means for determining an initially preset data slicing level, means for recording from a data pulse signal that has been received using the preset data slicing level the 1 and 0 binary pattern of the data pulses that occur in a time period allocated to the framing code in the data pulse signal, means for determining whether this recorded pattern is an acceptable framing code pattern in that it contains less than a given number of bit errors, means for determining whether the recorded pattern, if acceptable, contains more O's recorded as 1 's or more 1 's recorded as O's relative to the correct framing code pattern, and means for causing increase or decrease of the data slicing level from its preset level to a corrected level according as, respectively, the recorded pattern contains more O's recorded as 1 's than 1 's recorded as O's, the increase or decrease being in proportion to the extent of the error, and the slicing level means supplying the corrected data slicing level for data slicing the coded data pulses that follow the framing code.

2. An arrangement as claimed in Claim 1, for use where a sequence of clock pulses precedes the framing code, characterised in that said time period is extended to include at least part of the clock sequence, whereby the number of bits in the recorded pattern is increased by such part of the clock pulse sequence.

3. An arrangement as claimed in Claim 1 or Claim 2, embodied in a television receiver which is adapted to display alpha-numeric text or other message information concurrently with, or as a selectable alternative to, normal picture information.

4. An arrangement for determining a data slicing level, substantially as hereinbefore described with reference to Fig. 3 of the accompanying drawings.

5. An arrangement as claimed in Claim 4, embodied in a television receiver of a televi sion transmission system substantially as hereinbefore described with reference to Figs. 1 and 2 of the accompanying drawings.