GB2033699A

GB2033699A - Error detection

Info

Publication number: GB2033699A
Application number: GB7842852A
Authority: GB
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1978-11-01
Filing date: 1978-11-01
Publication date: 1980-05-21
Also published as: GB2033699B

Abstract

Repeatedly transmitted data blocks comprise groups of coded data pulses each group representing respective items of message information, and including a parity bit for error checking the group. Each information block comprising a plurality of groups has transmitted with it a plurality of error detection bits which can be used for error checking the information block as a whole, using a CRC. The data receiver arrangement comprises a data acquisition circuit DAC to which an incoming data stream DS is applied. The data stream PS is fed to a parity bit group error detector PBD which error checks each group of coded data pulses, error-free groups only being stored in a data store ST from which they can be applied to a utilisation device UD. A "whole message" error detector WMD error checks a stored information block as a whole using the CRC error detection bits. Thus an entire block need not be received error free before any group is stored, migration of errors amongst the group as blocks are repeatedly received being prevented. Application is to teletext transmission. <IMAGE>

Description

SPECIFICATION Data transmission This invention relates to serial data transmission systems requiring error detection, and to a method of data reception.

The invention relates more particularly to a data receiver arrangement of a type suitable for use in a data transmission system of a kind in which: data is transmitted in a plurality of discrete information blocks; the information blocks are transmitted successively in a recurrent cycle; each information block comprises groups of coded data pulses representing respective alpha-numeric characters or other items (e.g. graphics) of message information; each group of coded data pulses comprises a plurality of information bits and a parity bit which can be used for error detection in respect of the information bits of the group as received; and each information block has transmitted with it a plurality of error detection bits which can be used for error detection in respect of the information block as a whole.

In a data receiver arrangement of the above type, an entire information block has to be received correctly in a single transmission thereof in order for no error to be detected in respect of the information block as a whole. This poses the problem that the information block may have to be received a relatively large number of times in successive transmission cycles before a transmission occurs when the entire information block is received error free. Of course, errors detected in individual groups of coded data pulses may be acceptable for the information block to be utilised usefully, provided the number of such errors is not too great, but in some applications it may nevertheless be of importance to know when an entire information block, as received, is error free.

The reason for the above problem is that a group of coded data pulses which is received correctly in one transmission of an information block may be received with an error in it in a subsequent transmission of the information block, and vice versa.

According to the present invention this problem is mitigated by providing in a data transmission system of the above kind a method of data reception of an information block in which each group of received coded data pulses of the information block is error checked using the parity bit therein, only each group of received coded data pulses which is deemed to be error free by such error checking is passed to a data store for storage therein, and error-checking in respect of the information block as a whole is carried out on the received information block as readout from the data store.

Such a method in accordance with the invention has the advantage that a group of coded data pulses which is received correctly and thus stored in the data store in one transmission of the information block does not "corrupt" itself if it is received incorrectly in a subsequent transmission of the information block. As a consequence, the entire information block is likely to be received correctly (as stored) in a relatively fewer number of transmission cycles.

In carrying into effect a method of data reception according to the invention, the invention further provides a data receiver arrangement of the type specified above which comprises: data acquisition means for acquiring in succession groups of coded data pulses of a transmitted information block, parity bit detector means for error-checking each acquired group, data storage means for receiving for storage from the parity bit detector means only those groups of coded data pulses which are deemed by that detectorto be error free, and "whole message" error detector means responsive to an information block as stored in said data storage means for error checking the information block as a whole using the related error detection bits.

The invention has a particular but non-exclusive application to television receiver arrangement suitable for use in a television transmission system of a character in which coded data pulses representing alpha-numeric text or other message information are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals representing normal picture information are present. A television transmission system of the above character is described in United Kingdom patent specification No. 1,370,535.

The television receiver arrangement may include suitable television display means, or it may be adapted to feed a video signal containing decoded message information in to a separate television monitor. Also, it can be adapted to cause the display of alpha-numeric text ar other message information concurrently with, or as a selectable alternative to, normal picture information.

The invention also extends to a television receiver arrangement as set forth above, embodied in atele- vision transmission system of the character referred to which has provision for transmitting said plurality of error detection bits in cyclically transmitted information blocks.

The advantage of so applying a data receiver arrangement according to the invention is that such a television receiver arrangement already includes a parity bit detector for error checking individual groups of coded data pulses and a data store for storing received information blocks.

In order that the invention may be more fully understood reference will now be made by way of example to the accompanying drawings, of which: Figure 1 shows diagrammatically a data receiver arrangement according to the invention; Figure 2 shows diagrammatically a "whole message" error detector suitable for the arrangement of Figure 1; Figure 3 illustrates diagrammatically, data transmitted when a cyclic redundancy check is used for error detection; and Figure 4 shows diagrammatically a television receiver arrangement, embodying the invention, in a television transmission system of the character referred to.

Referring to the drawings, the data receiver arrangement shown in Figure 1 comprises a data acquisition circuit DAC to which an incoming data stream DS is applied. The data stream DS is transmitted by a transmitter TX and, as specified earlier in the specification, is assumed to have a format in which: data is transmitted in a plurality of discrete information blocks; the information blocks are transmitted successively in a recurrent cycle; each information block comprises groups of coded data pulses representing respective alpha-numeric characters or other items (e.g. graphics) of message information; each group of coded data pulses com prises a plurality of information bits and a parity bit which can be used for error detection in respect of the information bits of the group as received; and each information block has transmitted with it a plurality of error detection bits which can be used for error detection in respect of the information block as a whole.

The data stream DS is fed from the data acquisition circuit DAC to a parity bit error detector PBD which functions in known manner to check for, say, odd parity in each group of coded data pulses. Thus, for instance, if the information bits of a group of 7 coded data pulses are 1010000 then a parity bit 1 is added to the group as transmitted to provide an odd number of '1 's in the group. If the parity bit detector PBD detects an odd number of 'l's in the group, as received, then the assumption is made that the group has been received without error. However, if the parity bit detector PBD detects an even number of '1 's in a group as received, then the assumption is madethatthe group as received has an error in it.If the information bits of a group already contain an odd number of 'l's (e.g. 1110000), then a '0' is added as the parity bit.

The groups of coded data pulses which are assumed by the parity bit detector PBD to have been received correctly are fed from the latter two a data store ST. However, the groups of coded data pulses in which an error has been detected are not passed for storage and the previously stored groups retained. This has the effect that since the information blocks are repeatedly transmitted, the individual groups of coded data pulses which are received correctly can be stored progressively to build-up in the data store ST stored information blocks which are eventually without error.Without the presence of the parity bit detector PBD, the possibility would occur that a group received without error and stored in one transmission cycle may be received with an error and stored in a subsequent transmission cycle, thereby "corrupting" the error-free group which was stored previously. As a consequence, an entire information block to be stored would have to be received correctly in one transmission thereof in orderforthe information block to be stored without any errors therein.

The data receiver arrangement has a utilisation device UD (e.g. a visual display monitor) to which information blocks stored in the store ST can be applied for utilisation. A visual display monitor could usually accept an information block for utilisation, even though errors were still remaining therein.

The data receiver arrangement further includes a "whole message" error detector WMD to which information blocks stored in the data store ST and applied to the device UD are also applied. This detector WMD functions to apply an "error-free" signal to the device UD when it detects that an entire information block is error free. Thus, although the device U D may be able to function usually with an information block still containing error, it may nevertheless be important for the device UD to know when the information block applied to it is eventually error free.

The detector WMD can be of any suitable known form which can function to effect "whole message" error detection in response to the said plurality of error detection bits which are transmitted with each information block. One suitable detector for this purpose is Mullard device type GZF 1202 or Philips type 8X01 each of which is an encoder and decoder for data error detection; being used as an encoder at a transmitter for producing said plurality of error detection bits, and as a decoder at a receiver for performing error detection using said plurality of error detection bits. Details of these devices are given in Mullard Technical Information 5 and PhilipsTechni- cal Information 030, respectively.

Briefly, this particular device can perform inter-alia a cyclic redundancy check (CRC) with a choice of six generating code polynomials. As shown in Figure 2, the device essentially comprises polynomial select logic PSL by which a code polynomial can be selected at inputs Si. The selected code polynomial is used to control the gating of feedback information applied to exclusive-OR gates of a multi-bit shift register SR through which a data stream is fed between a data input Di and a data output Do. The shift register SR controls an error detector ED which pro vides an error signal ES. A mathematical evaluation of the operation of the device is now given.

As just mentioned, the "whole message" error detector WMD can be of a form which is adapted to effect error detection in an information block using a cyclic redundancy check (CRC). To evaluate the effectiveness of such a method of error detection, it is convenient to consider an information block in a mathematical form. One form which is used is a polynomial with a dummy variable term X. The lowest-order term, representing the least significant bit (LSB) is X" or 1, and the highest-order term, representing the most significant bit (MSB), is Xn.

Because the powers range from o to there are (n + 1 ) bits in the information block. The coefficients of the polynomial indicate whether an individual bit isO' or '1'. Thus a data stream G(X) of 10 bits can be represented in the following way: G(X) = 1110101101 = 1.X9 + 1.X8 + 1 + OX6 + 1.X6 + OX4 + 1.X3 + 1.X + OX + 1 = X9 + X6 + X7 + X6 + X3 + X2 + 1 By convention, the data stream G(X) is written with the MSB on the left. In practice, the MSB of the data is transmitted first. The degree n of the data polynomial is the power of the highest-order term, which is 9 in this example.The code polynomial P(X) can be described in a similar way to G(X), for example: P(X) =X+X3+X2+X+ 1 = 101111 To generate the check bitsfortransmission with the information block, the data polynomial is divided by the code polynomial to obtain a remainder. The remainder will be of a degree one less than that of the code polynomial, and will consist of the same number of bits as the degree of P(X). The data polynomial is followed by the remainder to form part of the information block which is transmitted as an entire message polynomial. This entire message polynomial as received, will be exactly divisible by the code polynomial if no errors were introduced during the transmission.

Modulo 2 arithmetic is used throughout the calculation to avoid the need to "carry" in the division, that is: 1 + 1 = 0 and 1 = It can be seen that subtraction is equivalent to addition in modulo 2 arithmetic.

The polynomial division of G(X) by P(X) is as follows: G(X) = Q(X) x P(X) + R(X), where O(X) is the quotient and R(X) is the remain der.

This gives: G(X) - R(X) = Q(X) - P(X) Since R(X) = -R(X), in modulo 2 arithmetic G(X) + R(X) = Q(X) > < x P(X) P(X) Before the division by P(X), every term in the message is multiplied by X" (n is the degree of P(X)). This multiplication effectively shifts the original data stream to create a number of zero positions which the remainder can occupy. For example, to divide G(X) by P(X), the power of G(X) is raised by the power of P(X).Thus: X8 G(X) = X14 + X13 + X12 + X10 + X8 + X7 + Xs This result is divided by P(X) using modulo 2 arithmetic to give the remainder: R(X) = X4 + X2 + X + 1 Adding the remainder to XSG(X) gives the entire message polynomial: F(X) - X14 + X13 + X12 + X10 + X' + X7 + X + X4 + X2 + X + 1 The above mathematical presentation is represented diagrammatically in Figure 3 which shows; firstly the data stream DS represented by the data polynomial G(X) with the most significant bit MSBI on the left and the least significant bit LSB on the right; secondly the remainder R represented by a remainder polynomial R(X); and thirdly, the transmitted message TM which is represented by the entire message polynomial F(X) = XnG(X) + R(X) and which has a higher order most significant bit MSB2.

If errors are introduced into the transmitted message TM during transmission, these can be considered as an error polynomial E(X), forming part of the received polynomial H(X), where H(X) = F(X) + E(X). The received polynomial H(X) is now divided by the code polynomial P(X). Because F(X) is divisible by P(X), the remainder of the division will be E(X)/P(X). In the cyclic redundancy check system assumed by way of example for the embodiment of Figures 1 and 2, a non-zero remainder indicates the presence of errors, and so if E(X) is not divisible by P(X) then the errors will be detected.For example: F(X) = X14 + X13 + X12 + X10 + XA + X7 + X + X4 + X2 + X + 1 = 111010110110111 H(X) = 110110100101111 (error bits underlined) =F(X)+(X12+X11 + X" + X7 + X4 + X3) = F(X) + X3(X + X' + X4 + X + 1) Therefore: E(X) = X3(X + X + X4 + X + 1) = X3E1(X) The error polynomial E(X) is reduced to its simp lest form, X3E1(X), and E1(X)-is divided by P(X). If the degree of E'(X) is less than that of P(X), then the error will be detected. If the degree of E1 (X) is grea- ter than that of P(X), then only error polynomials that are divisible by P(X) will remain undetected. In the example just given, E'(X) is not completely divisible by P(X).It is to be understood that the differences in performance between polynomials of the degree 16 are complex, especially when random errors are considered. Therefore, choice of a code polynomial should be on the basis of the kind of errors likely to be encountered. (Proc. I.R.E., 49 pages 228-235 "Cyclic Codes for Error Detection" is also of interest).

Referring now to Figure 4 of the drawings, which shows diagrammatically a television transmission system of the character referred to having atelevi- sion receiver arrangement which embodies the invention and which is for displaying selectively either a television picture which is produced from picture information in a normal broadcast on cable television video signal, or alpha-numeric text or other message information which is produced from coded data pulses which are transmitted in the video signal in vertical or field-blanking intervals thereof.

The possibility can also exist for displaying such message information concurrently with a television picture, for instance as sub-titles or captions which are superimposed on the television picture.

An incoming television video signal VS appears at an input lead 1 of the television receiver arrangement via its front end 2 which comprises the usual amplifying, tuning, i.f. and detector circuits. The front end 2 is assumed to be adapted to receive the video signal VS from a television transmitter 3 via a conventional over-air broadcast or cable transmission link4.The transmitter 3 includes in known manner means for producing television picture information, means for producing alpha-numeric text or other message information, and further means for generating the appropriate composite television video signal containing picture signals representative of the picture information, and coded data pulses representative of the message information, together with the usual synchronising, equalizing and blanking signals which are necessary for the operation of the television receiver arrangement.

For normal picture display in the television receiver arrangement, the received video signal is applied to a selector circuit 5 which includes a selector switch 6. When the switch 6 is closed, the video signal VS is applied to a colour decoder 7 which produces the R, G and B component signals for the picture display, these component signals being applied via a video interface circuit 8 to the red, green and blue guns of a colourtelevision picture tube 9. Scanning circuits 10 for the tube 9 receive the usual line and field synchronising pulses LS and FS from a synch. separator circuit 11 which extracts these synchronising pulses from the incoming video signal VS.

Coded data pulses representing message information in the video signal VS do not affect the picture display because they occur in one or more lines in the field-blanking interval when there is no picture display. Of the lines occurring in the field-blanking interval, most could be used to transmit coded data pulses representing message information. However, in the BBC/IBA Teletext System at present, only lines 17/18 of even fields and lines 330/331 of odd fields of the 625 line broadcast television system are used in the United Kingdom. (See "Broadcast Teletext Specification", September 1976, published jointly the the British Broadcasting Corporation, Independent Broadcasting Authority and British Radio Equipment Manufacturers' Association).

The video signal VS on the input lead 1 is also applied to a data acquisition circuit 12 which includes a data clock pulse generator (not shown) for deriving a data clock pulse train from the coded data pulses representing the message information.

It is assumed that the message information represented by the coded data pulses contained in the video signal VS is divided into different pages of information, and that each page is for display as a whole on the screen of the picture tube 9, with the coded data pulses representing each page of information being repeated periodically in a recurrent cycle with or without updating of the information. It is further assumed that each page of message information is identified by means of a unique page address code which is included in the coded data pulses and defines the page number.The television receiver arrangement includes a code selector circuit 13 which controls the particular coded data pulses that are acquired by the data acquisition circuit 12 at any time. (This control is indicated by a broad-arrow connection n representing the presence of a group of n parallel channels which form an n-bit channel link for carrying n bits of information required for data selection-other groups of parallel channels forming multi-bit channel links in the television receiver arrangement are represented similarly asm, o, p, q andr numbers of channels and bits).

The acquired coded data pulses are clocked serially into the data acquisition circuit 12 by the data clock pulse train produced in the latter. From the data acquisition circuit 12, the acquired coded data pulses are fed in parallel groups ofm bits to a parity bit error detector circuit 14 over an m-bit channel link, an m bit byte being required for each character (or other item of information) contained in the message information. It is assumed thatm = 8, so that a character byte comprises a character code consisting of 7 bits plus a single parity bit, and that the detector circuit 14 performs the same function as the "parity bit" error detector PBD in Figure 1 to check for odd parity in each character byte and to pass the character codefor storage only if the odd parity is detected.

The 7-bit character codes which satisfy the odd parity check are fed from the detector circuit 14 in parallel over an o-bit channel link (o = 7) to a data store 15. The data store 15 can store a complete page of message information. In a typical Teletext transmission, each page of message information would contain up to 24 rows of characters, with each row containing up to 40 characters. Thus, in order to identify the different characters of a page, it is furthermore assumed that the code data pulses also include an address code for each character, this address code employing r bits and being fed to the data store 15 over an r-bit channel link to control the storage therein of the character codes.As described in the publication "Broadcast Teletext Specification" mentioned previously, address codes relating to page and row identification for characters are error detected and protected using a Hamming Code, as it is important to identify correctly the storage locations for the character codes. However, the present invention is not concerned with this aspect of error detection which, therefore, is not considered further in the present specification.

In view of the restricted transmission time which is available for transmitting the coded data pulses representing message information, for instance, sufficient time to transmit the coded data pulses for only one character row during a television line in the field-blanking interval, character data for a page of message information has to be stored row-by-row in the data store 15 over a relatively large number of television fields. This storing of character data rowby-row in the data store 15 is under the control of the address codes received from the data acquisition circuit 12 overther-bitchannel link.

A character generator 16 of the television receiver arrangement is responsive to the character data stored in the data store 15 to produce character generating data which can be used to derive what is effectively a new picture signal for displaying the characters represented by the stored character data.

As mentioned previously, different characters are represented by respective 7-bit bytes. The bits of each byte are fed in parallel from the data store 15to the character generator 16 over ap-bit channel link (p = 7). A character format for characters to be displayed can be a co-ordinate matrix composed of discrete elements arranged in rows and columns, this format being derived from a "read-only" memory which serves as the character generator 16 and which provides bits of character generating data in rows and columns, one row at a time.Since the character generating data is required as a modulation of a video signal in order to produce selective bright-up of the screen of the picture tube 9 to achieve character display, the character generating data is produced serially (as 1's and 0's) by using a parallei-to-serial convertor 17 to convert each row of bits of data read out from the character generator 16 (e.g. q = 5) into serial form.

In order to effect character display on the screen of the picture tube 9 using standard line and frame scans, the logic of the television receiver arrangement in respect of character display is so organised that for each row of characters to be displayed, all the characters of the row are built up television line-by-television line as a whole, and the rows of characters are built up in succession. It takes a number of television lines to build up one row of characters.In the first television line character data from the data store 15 to the character generator 16 would cause the latter two produce character generating data in respect of the first row of discrete ele ments for the first character of the row, then in respect of the first row of discrete elements for the second character, and soon for the successive characters of the row. In the second television line, character generating data in respect of the second row of discrete elements for each character of the row would be produced in turn, and soon for the remaining television lines concerned.

The logic of the television receiver arrangement is organised by means of a clock pulse and timing pulse chain circuit 18 which provides appropriate clock and timing pulses to the data store 15, to the character generator 16, to the data acquisition circuit 12 and to the parity bit error detector circuit 14. The circuit 18 is synchronised in operation with the scanning circuits 10 of the picture tube 9 by the line and field synchronising pulses LS and FS extracted from the incoming video signal VS by the sync. separator circuit 11.

The output from the convertor 17 is applied to a colour code 19 which produces R1, G' and B' component signals for character display, these component signals being also applied to the video interface circuits 8. The colour coder 19 can be controlled (in a manner not shown) by selected items of the character data in the data store 15 to provide a controlled colour character display. Of course, black-and-white picture and character display is also possible, in which eventthe colourdecoder7 and colour coder 19 would be omitted.

The television receiver arrangement of Figure 4 further includes a "whole message" error detector circuit 20, an associated timing control circuit 21, and a second parallel-to-serial convertor 22. On the basis that the message information represented by the coded data pulses contained in the incoming video signal VS is divided into suitable information blocks (e.g. different pages of information or parts of these pages), and that each such information block has transmitted with it a plurality of error detection bits which can be used for error detection in respect of the information block as a whole, then these elements 20 to 22 function to produce on a lead 23 an "error free" signal when an information block interrogated by these elements is found to be error free.

This "error free" signal may be applied to the video interface circuits 8 to produce a visual indication of the "error free" condition on the screen of the picture tube 9. Where a page of displayed information is essentially numerical, for instance it is a page of "stock exchange" figures, the knowledge to a viewer that the displayed page is substantially free of errors caused during transmission of the message information would be highly desirable. The "error free" signal may also be otherwise used, for instance to provide an audible indication of the error free condition. Of course, the "errorfree" condition can be used in the inverse manner to indicate that a displayed page is not error free.

The detector circuit 20 performs the same function as the "whole message" error detector WMD in Figure 1 to check for errors in an information block as a whole as applied to it from a data store. The converter 22 serves to convert into serial form for application to the detector circuit 22 the 7-bit character bytes which are produced by the data store 15 in parallel on thep-bit channel link. The timing control circuit 21 is synchronized with the logic operations of the television receiver arrangement by the circuit 18 and serves to control access between the data store 15 and the detector circuit 20 for intervals occurring between writing character codes into and reading character codes from the data store 15. Alternatively, the normal timing for producing a display could be used with a buffer store (not shown) inserted between the store 15 and the serial-parallel convertor 22 to provide data to the error detector circuit 20 only once in respect of a stored information block and not repeatedly as is required for displaying the contents of the information block.

Claims

1. A method of data reception of an information block in a data transmission system of a kind in which; data is transmitted in a plurality of discrete information blocks; the information blocks are transmitted successively in a recurrent cycle; each information block comprises groups of coded data pulses representing respective alpha-numeric characters or other items of message information; each group of coded data pulses comprises a plurality of information bits and a parity bit which can be used for error detection in respect of the information bits of the group as received; and each information block has transmitted with it a plurality of error detection bits which can be used for error detection in respect of the information block as a whole; which method is characterised in that each group of received coded data pulses of the information block is error checked using the parity bit therein, only each group of received coded data pulses which is deemed to be error-free by such error-checking is passed to a data store for storage therein, and error-checking in respect of the information block as a whole is carried out on the received information block as read out from the data store.

2. A data receiver arrangement of the type specified for performing the method according to Claim 1, characterised in that it comprises data acquisition means for acquiring in succession groups of coded data pulses of a transmitted information block, parity bit detector means for errorchecking each acquired group, data storage means for receiving for storage from the parity bit detector means only those groups of coded data pulses which are deemed by that detectorto be error free, and "whole message" detector means responsive to an information block as stored in said data storage means for error-checking the information block as a whole using the related error detection bits.

3. A data receiver arrangement as claimed in Claim 2, characterised in that it is a television receiver arrangement suitable for use in a television transmission system of a character in which coded data pulses representing alpha-numeric text or other message information are transmitted in a video signal in at least one television line in field-blanking intervals where no picture signals representing normal picture information are present.

4. A data receiver arrangement in the form of a television receiver arrangement according to Claim 3, characterised in that it includes suitable television display means.

5. A data receiver arrangement in the form of a television receiver arrangement according to Claim 3, characterised in that it is adapted to feed a video signal containing decoded message information into a separate television monitor.

6. A data receiver arrangement in the form of a television receiver arrangement as claimed in Claim 3, Claim 4 or Claim 5, embodied in a television transmission system of the character referred to.

7. A data receiver arrangement substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.

8. A data receiver arrangement as claimed in Claim 7, having a "whole message" error detector substantially as hereinbefore described with reference to Figures 2 and 3 of the accompanying drawings.

9. A data receiver arrangement in the form of a television receiver arrangement substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.