GB2062961A - Integrated series-connected diodes - Google Patents
Integrated series-connected diodes Download PDFInfo
- Publication number
- GB2062961A GB2062961A GB8035263A GB8035263A GB2062961A GB 2062961 A GB2062961 A GB 2062961A GB 8035263 A GB8035263 A GB 8035263A GB 8035263 A GB8035263 A GB 8035263A GB 2062961 A GB2062961 A GB 2062961A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- layer
- semiconductor
- highly doped
- doped layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract 1
- 238000001816 cooling Methods 0.000 description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 239000004922 lacquer Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 235000011149 sulphuric acid Nutrition 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000001117 sulphuric acid Substances 0.000 description 2
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 description 1
- VYRNMWDESIRGOS-UHFFFAOYSA-N [Mo].[Au] Chemical compound [Mo].[Au] VYRNMWDESIRGOS-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000010210 aluminium Nutrition 0.000 description 1
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
An IC comprises a plurality of Schottky or p-n diodes connected in series by bridges (7) crossing isolation grooves, the lower region (3) of each diode being provided with an underlying more heavily doped layer (2) which is connected to one end of the appropriate bridge (7) by a conductive column (6). Preferably the conductive columns (6) are of metal and the diodes are supported by a semi-insulating substrate 1. The circuit is produced by forming the semiconductor layers (2,3) on the substrate (1), applying Schottky contacts (5), etching a recess and filling it with metal to form the conductive column depositing the bridging strips, utilising the metal layers as a mask for etching grooves down to the more heavily doped layer while undercutting the bridges, and then extending the grooves between the diodes and under the bridges down to the substrate. <IMAGE>
Description
SPECIFICATION
Semiconductor device
The invention relates to a semiconductor device having a substrate region, a layer-shaped semiconductor region of a first conductivity type which is situated on the substrate region and which is divided into at least first and second electrically separated island-shaped parts by a groove extending into the substrate region, each part comprising an electrode region which forms a rectifying junction with the adjoining semiconductor material, the electrode region of the first part and the region of the first conductivity type of the second part being connected electrically via a metal strip which bridges the groove.
The invention furthermore relates to a method of manufacturing such a semiconductor device.
A Asemiconductor device of the kind described is disclosed in British Patent Specification GB 1,244,759.
In manufacturing semiconductor devices for high frequencies, in particular of high frequency X-band generators, it is often necessary for diodes to be connected in series so as to increase the power of said devices.
This may be done by connecting individual diodes jn series. One of the disadvantages of this is that the manufacture of the diodes on the one hand and the mutual arrangement of the diodes on the other hand is carried out separately while in this manner non-flat structures are obtained.
In the semiconductor device as described in GB 1,244,759, the collector-base junctions of two npntransistors separated by a V-groove are connected in series via a metal bridge on the same semiconductor wafer. However, the manufacture of such a device requires a large number of masking and alignment steps.
It is the object of the invention to provide a semiconductor device in which two or more diodes are connected in series on the same semiconductor wafer, which device is compact and can be manufactured in a reproducible manner by means of relative- ly few aligning and masking steps.
According to the invention, a semiconductor device of the kind described in the opening paragraph is characterized in that the layer-shaped semiconductor region comprises a highly doped layer adjoin- ing the substrate region and a lower doped layer present thereon, and that the metal strip is connected to the highly doped layer by a column of electrically conductive material extending from the surface into the highly doped layer.
"Electrode region" is to be understood to mean in this Application the region across which a rectifying contact is formed with the material of the first conductivity type. In the case of a Schottky diode this is the region of the Schottky junction; in the case of a p-n diode this is the region of the second conductivity type which forms the p-n junction with the layer-shaped semiconductor region of the first conductivity type.
The conductive columns may consist of a metal or of a readily conducting semiconductor material, for example, highly doped polycrystalline silicon.
Advantageously an insulating or a so-called semiinsulating substrate region is used, although a substrate region of the second conductivity type which forms a blocking p-n junction with the layershaped region might also be used.
A preferred form of the device which can be manufactured with relatively few masking steps is characterized according to the invention in that the conductive column and the electrode region are both bounded by the said first groove and by a second groove which is present between the conductive column and the electrode region and extends from the surface to at most over a part of the thickness of the high doped layer.
The device in accordance with the invention can be manufactured in a particularly suitable manner according to a method which is characterized in that a highly doped and a lower-doped semiconductor layer of a first conductivity type are provided successively on an electrically substantially insulating substrate region, that at least two electrode regions with associated electrodes are realised on the lower doped semiconductor layer and form rectifying junctions with the said semiconductor layer, that a recess is then etched between said electrodes and extends into the highly doped layer, that said recess is filled with an electrically conductive material so as to form a conductive column, that an etchant-resistant metal strip is then provided which connects one electrode to the juxtaposed conductive column, that, while using all available electrodes and conductive columns as an etching mask, the semiconductor material is then etched away also below the metal strips in a first etching step down to at most over a part of the thickness of the highly doped layer so as to form grooves which surround the electrodes and the conductive columns, that the grooves between a conductive column and the juxtaposed electrode not connected thereto via a metal strip are then masked, after which the non-masked grooves are etched into the substrate region during a second etching step.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which
Figures 1 to 8 show the manufacture of a diode system according to the invention in successive stages.
According to the invention, a first highly doped semiconductor layer 2 (for example, of GaAs of the n++ conductivity type having a doping concentration of approximately 1018 atoms per cm3 and a thickness of approximately 5Fm) is provided on a substrate 1, in this example of semi-insulating gallium arsenide, see Figure 1, by means of epitaxial growth, for example, from the vapour phase, and then a second lower doped semiconductor layer 3 of the same material (for example, GaAs of then conductivity type having a doping concentration of approximatey 2.1 o16 atoms/cm3 and a thickness of approximately 4lim) is provided on top of said first layers 2.
In the manufacture of Schottky diodes, a photolacquer layer 4 is then provided which is exposed in
such manner that a number of windows situated at
regular distances from each other are formed, as
shown in Figure 2. A metal (5), for example alumi
nium, is then vapour-deposited in a vacuum and forms in an electrode region a Schottky contact with the semiconductor layer 3. After removing the
photolacquer by means of a usual solvent, the metal
which forms the electrodes 5 remains only in the
places where previously the windows were provided
in the photo-lacquer, as shown in Figure 3 (which
process is known by the English name of "lift off").
In manufacturing p-n diodes, according to various
known methods, a p-n junction is provided either by vapour-depositing an epitaxial layer of a conductiv
ity type which is opposite to the conductivity type of the already existing layer 2 and 3, or by forming
inside the semiconductor layer 3 electrode regions
of a different coductivity type, for example, by ion
implantation or by in-diffusion of dopants via windows. This is of no further significance for the
invention.
Starting from the stage shown in Figure 3, the semiconductor material is locally etched between the various electrodes 5 by means of a suitable etchant in such manner that a cavity is formed which extends down to preferably approximately the centre of the semiconductor layer 2. A suitable etchant for a semiconductor material, for example GaAs, is, for example, a mixture of sulphuric acid and hydrogen peroxide (H2SO4 = 5 parts by volume; H202 =
1 part by volume, H2O = 1 part by volume). This cavity is then filled with a readily conductive material, in this example by electrolytically growing a gold column 6 as shown in Figure 4.
The upper side of the device is then covered with a photolacquer which is exposed via a mask in such
manner that windows can be etched in parts of the surface which are present above a metal electrode 5 and also above an immediately adjacent conductive column 6. By vapour-depositing a thin metal layer consisting, for example, of a molybdenum-gold compound in a thickness of approximately 0.5 lim and after removal (by lift-off) of the remaining lacquer, only the metal strips 7 as shown in Figure 5 are left.
The semiconductor body is then etched again, preferably down to approximately the centre of the semiconductor layer 2, so that the various elementary diodes and gold columns protected by the metal electrodes 5 are separated from each other and the strips 7 are undercut so that they are formed into bridges as shown in Figure 6.
The upper side of the device is then covered again with a photolacquer layer 8 which is maintained only in the spaces between the columns 6 and the electrodes 5 not connected by a bridge so as to mask said spaces, while the etching treatment with the same solution is continued in the non-masked places, as is shown in Figure 7.
After etching down to the semi-insulating substrate 1 and after removing the remaining lacquer by means of a usual solvent, the structure shown in
Figure 8 is obtained. (Figure 8 is, in part, a perspective view).
As already stated, an etching liquid of sulphuric acid and hydrogen peroxide may be used for etching gallium arsenide; for this purpose may also be used a dilute solution of citric acid on another etchant.
The direction of the diodes is also shown diagram- matically in the conventional manner in Figure 8.
The device obtained forms a series arrangement of
diodes. While a metal (Al)/semiconductor (GaAsn) junction forms a diode, said diodes are interconnected by the metal bridge 7, the metal column 6 and a part of the n++ semiconductor layer, with which in this manner the upper side of one diode is connected to the lower side of the other diode and hence a series arrangement is obtained.
Since this circuit arrangement is provided on a semi-insulating substrate, said substrate at the same time serves as a mechanical support - all diodes are supported in the same manner and compactly - and as an electric insulation -the electrons do not penetrate into the substrate but flow through the highly doped n++ semiconductor layer. Since the substrate is comparatively thick, it also serves at least partly as a heat sink. However, it is not necessary for the circuit to be assembled in an envelope which comprises a cooling plate, for example of copper.
Such cooling plates are sufficiently known is those skilled in the art and will not be further described here. Since the device comprises a number of diodes which during their operation give off a comparatively large amount of thermal energy, and the lower side of the substrate which is to be connected to the upper side of the cooling plate is comparatively large, it is to be preferred to use special envelopes in which the upper side of the cooling plate is optically polished. It is to be noted that the cooling plate may also be provided differently; for example, it may be advantageous, since the heat dissipation takes place substantially in the upper part of the device, to provide the cooling plate on the upper side. According to this modified embodiment the cooling plate may not be of copper or of another electrically conductive material but, for example, may consist of an electrically non-conductive readily heat conductive material, for example, beryllium oxide. The metal strips 7 may be provided directly on the surface of the cooling plate.
It will be obvious that many variations are possible to those skilled in the art without departing from the scope of the invention. For example, other semiconductor materials, other metals and other etchants may be used. The various cavities in the upper side of the semiconductor body also be filled with any dielectric material.
Claims (8)
1. A semiconductor device having a substrate region, a layer-shaped semiconductor region of a first conductivity type which is situated on the substrate region and which is divided into at least first and second electrically separated island-shaped parts by a groove extending into the substrate region, each part comprising an electrode region which forms a rectifying junction with the adjoining semiconductor material, the electrode region of the first part and the region of the first conductivity type of the second part being connected electrically via a metal strip which bridges the groove, characterized in that the layer-shaped semiconductor region comprises a highly doped layer adjoining the substrate region and a lower doped layer present thereon, and that the metal strip is connected to the highly doped layer by a column of an electrically conductive material extending from the surface into the highly doped layer.
2. A semiconductor device as claimed in Claim 1, characterized in that the substrate region consists of an electrically substantially insulating material.
3. A semiconductor device as claimed in Claim 1 or 2, characterized in that the conductive column and the electrode region are both bounded by the said first groove and by a second groove which is present between the conductive column and the electrode region and extends from the surface to at most over a part of the thickness of the highly doped layer.
4. A method of manufacturing a semiconductor device as claimed in any of the preceding Claims, characterized in that a highly doped and a lower doped semiconductor layer of a first conductivity type are provided successively on an electrically substantially insulating substrate region, that at least two electrode regions with associated electrodes are realized on the lower doped semiconductor layer and form rectifying junctions with said semiconductpr layer, that a recess is then etched between said electrodes and extends into the highly doped layer, that said recess is filled with an electrically conductive material so as to form a conductive column, that an etchant-resistant metal strip is then provided which connects one electrode to the juxtaposed conductive column, that, while using all electrodes and conductive columns present as an etching mask, the semiconductor material is then etched away also below the metal strips in a first etching step down to at most over a part of the thickness of the highly doped layer so as to form grooves which surround the electrodes and the conductive columns, that the grooves between a conductive column and the juxtaposed electrode not connected thereto via a metal strip are then masked after which the nonmasked grooves are etched into the substrate region during a second etching step.
5. A method as claimed in Claim 4, characterized in that the conductive columns are manufactured by electrolytically depositing metal in the recesses.
6. A method as claimed in Claim 4 or 5, characterized in that during the first etching step the grooves are etched into the highly doped layer.
7. A semiconductor device substantially as herein described with reference to Figure 8 of the accompanying drawings.
8. A method substantially as herein described with reference to Figures 1 to 8 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7927480A FR2469804A1 (en) | 1979-11-07 | 1979-11-07 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE INCLUDING A DIODES ASSEMBLY IN SERIES AND DEVICE RESULTING THEREFROM |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2062961A true GB2062961A (en) | 1981-05-28 |
Family
ID=9231399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8035263A Withdrawn GB2062961A (en) | 1979-11-07 | 1980-11-03 | Integrated series-connected diodes |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5676583A (en) |
| CA (1) | CA1165009A (en) |
| DE (1) | DE3041232A1 (en) |
| FR (1) | FR2469804A1 (en) |
| GB (1) | GB2062961A (en) |
| NL (1) | NL8006019A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007142603A1 (en) * | 2006-06-09 | 2007-12-13 | Agency For Science, Technology And Research | An integrated shadow mask and method of fabrication thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07107940B2 (en) * | 1983-01-28 | 1995-11-15 | 三洋電機株式会社 | Shoutoki Barrier diode device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1244759A (en) * | 1968-12-11 | 1971-09-02 | Associated Semiconductor Mft | Improvements in and relating to methods of manufacturing semiconductor devices |
| DE2001468A1 (en) * | 1970-01-14 | 1971-07-22 | Philips Nv | Process for the manufacture of semiconductor components |
| DE2106540A1 (en) * | 1970-02-13 | 1971-08-19 | Texas Instruments Inc | Semiconductor circuits and processes for their manufacture |
| FR2335957A1 (en) * | 1975-12-17 | 1977-07-15 | Radiotechnique Compelec | Multilayer epitaxial monolithic rectifier bridge - includes Darlington pair formed on same silicon substrate |
| FR2363896A2 (en) * | 1976-09-01 | 1978-03-31 | Radiotechnique Compelec | Monolithic semiconductor integrated circuit chip - includes multi-layer structure providing full-wave rectifier and output amplifier |
| JPS5439582A (en) * | 1977-09-02 | 1979-03-27 | Nec Corp | Integrated composite diode device |
-
1979
- 1979-11-07 FR FR7927480A patent/FR2469804A1/en active Granted
-
1980
- 1980-10-30 CA CA000363613A patent/CA1165009A/en not_active Expired
- 1980-11-03 GB GB8035263A patent/GB2062961A/en not_active Withdrawn
- 1980-11-03 DE DE19803041232 patent/DE3041232A1/en not_active Withdrawn
- 1980-11-04 NL NL8006019A patent/NL8006019A/en not_active Application Discontinuation
- 1980-11-05 JP JP15477080A patent/JPS5676583A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007142603A1 (en) * | 2006-06-09 | 2007-12-13 | Agency For Science, Technology And Research | An integrated shadow mask and method of fabrication thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CA1165009A (en) | 1984-04-03 |
| FR2469804B1 (en) | 1983-04-29 |
| NL8006019A (en) | 1981-06-01 |
| JPS5676583A (en) | 1981-06-24 |
| FR2469804A1 (en) | 1981-05-22 |
| DE3041232A1 (en) | 1981-05-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |