GB2049363A - RF signal detectors - Google Patents
RF signal detectors Download PDFInfo
- Publication number
- GB2049363A GB2049363A GB8002592A GB8002592A GB2049363A GB 2049363 A GB2049363 A GB 2049363A GB 8002592 A GB8002592 A GB 8002592A GB 8002592 A GB8002592 A GB 8002592A GB 2049363 A GB2049363 A GB 2049363A
- Authority
- GB
- United Kingdom
- Prior art keywords
- transistor
- resistor
- base
- line
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012935 Averaging Methods 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 230000004044 response Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/22—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using conversion of ac into dc
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D1/00—Demodulation of amplitude-modulated oscillations
- H03D1/14—Demodulation of amplitude-modulated oscillations by means of non-linear elements having more than two poles
- H03D1/18—Demodulation of amplitude-modulated oscillations by means of non-linear elements having more than two poles of semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
- H03G3/341—Muting when no signals or only weak signals are present
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Noise Elimination (AREA)
Abstract
An averaging detector having a resistor R1 across the base and emitter of Q1, a capacitor C1 in a signal input line VIN to the base of Q2, the collectors of Q1, Q2 being connected to a positive line and the base of Q1 being connected to an output line Vo, together with the emitter of Q2 via a resistor R3, an inhibit switch such as a transistor Q3 responsive to noise blanking signals being between the base of Q2 and a zero voltage line, a resistor R4 and capacitor C2 being in parallel between the zero voltage line and the output line, the arrangement being such that on application of a voltage greater than the threshold voltage of Q1 successive positive and negative cycles alternately reverse bias and forward bias Q1, Q2 to achieve a balance between the half cycle charging through R3 and the continuous discharge through R4 to thereby provide a DC output proportional to the average input voltage waveform envelope. The detector may be used for a squelch, AGC or AM detector. <IMAGE>
Description
SPECIFICATION
Improvements in and relating to detectors
This invention relates to detectors and particularly to a so-called averaging detector.
An object of the invention is to provide an averaging detector with gain to provide a DC output proportional to the average input voltage waveform envelope.
The invention is particularly advantageous as the detector in the squelch circuit forming part of the noise blanking radio receiver described in co-pending Patent Application No. 7914881 but the averaging detector of the present invention is applicable to any system requiring an averaging detector with gain such as in an
AM, AGC radio.
According to the invention there is provided an averaging detector responsive to noise signals and responsive also to noise blanking signals produced in response to receipt of RF signals including noise signals, said averaging detector providing a DC output voltage proportional to the average level of the input voltage waveform envelope.
The invention will now be described by way of example only with particular reference to the accompanying drawings wherein:
Figure 1 is a detailed circuit of the averaging detector of the present invention;
Figures 2A to 2D are waveform diagrams of the signals present in the detector of Figure 1;
Figure 3 is a detailed circuit diagram of a modified averaging detector with threshold voltage reduction and
Figure 4 is a graph of the transfer function of the averaging detector with threshold offset.
Referring to Figure 1 ,the averaging detector comprises an NPN transistor Q1,#a capacitor C1 being connected in the VIN line and resistor R1 being connected across, the base and emitter of transistor Q. A resistor R2 is connected in series with capacitor C1 and to the base of a further NPN transistor 02. The collectors of transistors Q1, Q2 are connected to the +ve line and the base of transistor Q, is also connected to the output voltage line VO The emitter of transistor Q2 is connected via resistor R3 to the output voltage line VO and capacitor C2 and resistor R4 are connected in parallel between the OV line and the line VO An inhibit switch comprising a further NPN transistor Q3 is connected between the base of transistor Q2 and the
OV line, and this is used for blanking, as described hereafter.
With the circuit in the quiescent state i.e. Via=0, on application of a voltage greater than the threshold voltage 2VsE, the first positive going cycle of VIN, reverse biases transistor Q, and forward biases transistor
Q2. The impedance seen by capacitor C1 is high and mainly that of resistor R1 and the full positive swing available is followed by the emitter of transistor Q2 to charge capacitor C2 through resistor R3 forming a rectified average. As VIN goes negative, transistor Q2 is reverse biased at a higher voltage than it became forward biased in the previous cycle due to the charging of capacitor C2. Also transistor Q, becomes forward biased at a higher voltage for the same reason.When transistor Qi is forward biased, capacitor C1 sees a very low impedance and becomes charged to a potential difference equal to VO The next positive going cycle of VIN has a positive d.c. shift equal to VO This causes transistor Q2 to become forward biased in the same way as the first cycle but offset. Capacitor C2 receives a further charge and on the negative cycle of VIN, transistor Q becomes forward biased and charges up capacitor C1. This process is repeated until a balance is reached between the half cycle charging through resistor R3 and the continuous discharge through resistor R4.
The circuit described above is an averaging detector and can be used as the detector in FM squelch, where it exhibits greater immunity to very short duration spikes or bursts, than a peak detector. However, the averaging detector has application in circuits other than the radio receiver circuit of the present invention and could be used as an AGC detector as an AM detector.
In Figure 1 C1 R1 > }t C2 R4 n C2 R3 t For averaging
forV-2VBE > O Vo = oforV-2VBE S 0
In a modification of the circuit of Figure 1, the threshold voltage can be reduced by offsetting the voltage on the base of transistor QI by up to 2VBE above 0. One method using a pair of forward biased diodes is shown in Figure 3. In this circuit resistor R1 is connected between the base and collector of transistor Q1 and a pair of forward biased diodes D1, D2, are connected between the base of transistor Q, and output line VOF a capacitor C3 being connected across diodes D1, D2.
The inhibit switching transistor Q3 grounds the base of transistor Q2, to eliminate FM squelch lock for the duration of the random ringing occurring atthe IF limit frequency, the transistor a3 being turned on during and for a short time after the IF blanking pulse.
It should be noted that resistor R2 is not an essential part of the circuit of Figure 3, except when it is blanked by grounding the base of transistor Q2. Resistor R2 then prevents overload of transistor Q1. Resistor R1 defines with the transistor Q2 input impedance, the input time constant. Capacitor C1 should not approach the value of capacitor C2 to maintain small charging currents in transistor Q.
Claims (5)
1. An averaging detector including means responsive to noise signals and to noise blanking signals produced in response to RF signals including noise signals, and further means connected between an input voltage signal line and an output voltage line to produce a DC output voltage proportional to the average level of the input voltage signal waveform envelope.
2. An averaging detector as claimed in Claim 1 comprising a first transistor having a first resistor connected across the base and emitter thereof, a first capacitor connected in a signal input line and to the base of a second transistor, the collectors of the first and second transistors being connected to a positive voltage line and the base of the first transistor being connected to an output voltage line together with the emitter of the second transistor, via a second resistor, an inhibit switch being connected between the base of the second transistor and a zero voltage line, a third resistor and second capacitor being connected in parallel between the zero voltage line and the output voltage line, the arrangement being such that upon application of a voltage greater than the threshold voltage of the first transistor, successive positive and negative going cycles alternately reverse bias and forward bias the first and second transistors to achieve a balance between the half cycle charging through the second resistor and the continuous discharge through the third resistor to provide a DC output voltage proportional to the average level of the input voltage signal waveform envelope.
3. An averaging detector as claimed in Claim 2 wherein said inhibit switch comprises a third transistor.
4. An averaging detector as claimed in Claim 1 comprising a first transistor having a first resistor connected between the base and a positive voltage line, a first capacitor connected in a signal input line and to the base of a second transistor, the collectors of the first and second transistors being connected to the positive voltage line, a second resistor and second capacitor being connected in parallel between an output voltage line and a zero voltage line', and the base of the first transistor being connected to the output voltage line via a pair of forward biased diodes connected in parallel with a third capacitor, together with the emitter of the second transistor via a third resistor, the threshold voltage of the first transistor being reduced by offsetting the voltage on the base thereof and the first and second transistors being alternately reverse biased and forward biased on successive positive and negative going cycles to achieve a balance between the half cycle charging through the third resistor and the continuous discharge through the second resistor to provide a DC output voltage proportional to the average level of the input voltage signal waveform envelope.
5. An averaging detector substantially as hereinbefore described and as shown in Figures 1 and 2 or 3 and 4 of the accompanying drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8002592A GB2049363B (en) | 1979-04-30 | 1980-01-25 | Rf signal detectors |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB7914883 | 1979-04-30 | ||
GB8002592A GB2049363B (en) | 1979-04-30 | 1980-01-25 | Rf signal detectors |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2049363A true GB2049363A (en) | 1980-12-17 |
GB2049363B GB2049363B (en) | 1983-08-24 |
Family
ID=26271363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8002592A Expired GB2049363B (en) | 1979-04-30 | 1980-01-25 | Rf signal detectors |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2049363B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107817376A (en) * | 2017-11-15 | 2018-03-20 | 武汉合康智能电气有限公司 | A kind of negative half period waveform blanking amplitude sampling apparatus |
-
1980
- 1980-01-25 GB GB8002592A patent/GB2049363B/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107817376A (en) * | 2017-11-15 | 2018-03-20 | 武汉合康智能电气有限公司 | A kind of negative half period waveform blanking amplitude sampling apparatus |
CN107817376B (en) * | 2017-11-15 | 2023-09-05 | 武汉合智数字能源技术有限公司 | Negative half-cycle waveform blanking amplitude sampling device |
Also Published As
Publication number | Publication date |
---|---|
GB2049363B (en) | 1983-08-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |