GB2049363A

GB2049363A - RF signal detectors

Info

Publication number: GB2049363A
Application number: GB8002592A
Authority: GB
Original assignee: Motorola Ltd
Current assignee: Motorola Solutions UK Ltd
Priority date: 1979-04-30
Filing date: 1980-01-25
Publication date: 1980-12-17
Also published as: GB2049363B

Abstract

An averaging detector having a resistor R1 across the base and emitter of Q1, a capacitor C1 in a signal input line VIN to the base of Q2, the collectors of Q1, Q2 being connected to a positive line and the base of Q1 being connected to an output line Vo, together with the emitter of Q2 via a resistor R3, an inhibit switch such as a transistor Q3 responsive to noise blanking signals being between the base of Q2 and a zero voltage line, a resistor R4 and capacitor C2 being in parallel between the zero voltage line and the output line, the arrangement being such that on application of a voltage greater than the threshold voltage of Q1 successive positive and negative cycles alternately reverse bias and forward bias Q1, Q2 to achieve a balance between the half cycle charging through R3 and the continuous discharge through R4 to thereby provide a DC output proportional to the average input voltage waveform envelope. The detector may be used for a squelch, AGC or AM detector. <IMAGE>

Description

SPECIFICATION Improvements in and relating to detectors This invention relates to detectors and particularly to a so-called averaging detector.

An object of the invention is to provide an averaging detector with gain to provide a DC output proportional to the average input voltage waveform envelope.

The invention is particularly advantageous as the detector in the squelch circuit forming part of the noise blanking radio receiver described in co-pending Patent Application No. 7914881 but the averaging detector of the present invention is applicable to any system requiring an averaging detector with gain such as in an AM, AGC radio.

According to the invention there is provided an averaging detector responsive to noise signals and responsive also to noise blanking signals produced in response to receipt of RF signals including noise signals, said averaging detector providing a DC output voltage proportional to the average level of the input voltage waveform envelope.

The invention will now be described by way of example only with particular reference to the accompanying drawings wherein: Figure 1 is a detailed circuit of the averaging detector of the present invention; Figures 2A to 2D are waveform diagrams of the signals present in the detector of Figure 1; Figure 3 is a detailed circuit diagram of a modified averaging detector with threshold voltage reduction and Figure 4 is a graph of the transfer function of the averaging detector with threshold offset.

Referring to Figure 1 ,the averaging detector comprises an NPN transistor Q1,#a capacitor C1 being connected in the VIN line and resistor R1 being connected across, the base and emitter of transistor Q. A resistor R2 is connected in series with capacitor C1 and to the base of a further NPN transistor 02. The collectors of transistors Q1, Q2 are connected to the +ve line and the base of transistor Q, is also connected to the output voltage line VO The emitter of transistor Q2 is connected via resistor R3 to the output voltage line VO and capacitor C2 and resistor R4 are connected in parallel between the OV line and the line VO An inhibit switch comprising a further NPN transistor Q3 is connected between the base of transistor Q2 and the OV line, and this is used for blanking, as described hereafter.

With the circuit in the quiescent state i.e. Via=0, on application of a voltage greater than the threshold voltage 2VsE, the first positive going cycle of VIN, reverse biases transistor Q, and forward biases transistor Q2. The impedance seen by capacitor C1 is high and mainly that of resistor R1 and the full positive swing available is followed by the emitter of transistor Q2 to charge capacitor C2 through resistor R3 forming a rectified average. As VIN goes negative, transistor Q2 is reverse biased at a higher voltage than it became forward biased in the previous cycle due to the charging of capacitor C2. Also transistor Q, becomes forward biased at a higher voltage for the same reason.When transistor Qi is forward biased, capacitor C1 sees a very low impedance and becomes charged to a potential difference equal to VO The next positive going cycle of VIN has a positive d.c. shift equal to VO This causes transistor Q2 to become forward biased in the same way as the first cycle but offset. Capacitor C2 receives a further charge and on the negative cycle of VIN, transistor Q becomes forward biased and charges up capacitor C1. This process is repeated until a balance is reached between the half cycle charging through resistor R3 and the continuous discharge through resistor R4.

The circuit described above is an averaging detector and can be used as the detector in FM squelch, where it exhibits greater immunity to very short duration spikes or bursts, than a peak detector. However, the averaging detector has application in circuits other than the radio receiver circuit of the present invention and could be used as an AGC detector as an AM detector.

In Figure 1 C1 R1 > }t C2 R4 n C2 R3 t For averaging

forV-2VBE > O Vo = oforV-2VBE S 0 In a modification of the circuit of Figure 1, the threshold voltage can be reduced by offsetting the voltage on the base of transistor QI by up to 2VBE above 0. One method using a pair of forward biased diodes is shown in Figure 3. In this circuit resistor R1 is connected between the base and collector of transistor Q1 and a pair of forward biased diodes D1, D2, are connected between the base of transistor Q, and output line VOF a capacitor C3 being connected across diodes D1, D2.

The inhibit switching transistor Q3 grounds the base of transistor Q2, to eliminate FM squelch lock for the duration of the random ringing occurring atthe IF limit frequency, the transistor a3 being turned on during and for a short time after the IF blanking pulse.

It should be noted that resistor R2 is not an essential part of the circuit of Figure 3, except when it is blanked by grounding the base of transistor Q2. Resistor R2 then prevents overload of transistor Q1. Resistor R1 defines with the transistor Q2 input impedance, the input time constant. Capacitor C1 should not approach the value of capacitor C2 to maintain small charging currents in transistor Q.

Claims

1. An averaging detector including means responsive to noise signals and to noise blanking signals produced in response to RF signals including noise signals, and further means connected between an input voltage signal line and an output voltage line to produce a DC output voltage proportional to the average level of the input voltage signal waveform envelope.

2. An averaging detector as claimed in Claim 1 comprising a first transistor having a first resistor connected across the base and emitter thereof, a first capacitor connected in a signal input line and to the base of a second transistor, the collectors of the first and second transistors being connected to a positive voltage line and the base of the first transistor being connected to an output voltage line together with the emitter of the second transistor, via a second resistor, an inhibit switch being connected between the base of the second transistor and a zero voltage line, a third resistor and second capacitor being connected in parallel between the zero voltage line and the output voltage line, the arrangement being such that upon application of a voltage greater than the threshold voltage of the first transistor, successive positive and negative going cycles alternately reverse bias and forward bias the first and second transistors to achieve a balance between the half cycle charging through the second resistor and the continuous discharge through the third resistor to provide a DC output voltage proportional to the average level of the input voltage signal waveform envelope.

3. An averaging detector as claimed in Claim 2 wherein said inhibit switch comprises a third transistor.

4. An averaging detector as claimed in Claim 1 comprising a first transistor having a first resistor connected between the base and a positive voltage line, a first capacitor connected in a signal input line and to the base of a second transistor, the collectors of the first and second transistors being connected to the positive voltage line, a second resistor and second capacitor being connected in parallel between an output voltage line and a zero voltage line', and the base of the first transistor being connected to the output voltage line via a pair of forward biased diodes connected in parallel with a third capacitor, together with the emitter of the second transistor via a third resistor, the threshold voltage of the first transistor being reduced by offsetting the voltage on the base thereof and the first and second transistors being alternately reverse biased and forward biased on successive positive and negative going cycles to achieve a balance between the half cycle charging through the third resistor and the continuous discharge through the second resistor to provide a DC output voltage proportional to the average level of the input voltage signal waveform envelope.

5. An averaging detector substantially as hereinbefore described and as shown in Figures 1 and 2 or 3 and 4 of the accompanying drawings.