GB1585028A

GB1585028A - Colour television systems

Info

Publication number: GB1585028A
Application number: GB1756878A
Authority: GB
Original assignee: Indesit Industria Elettrodomestici Italiana SpA
Current assignee: Indesit Industria Elettrodomestici Italiana SpA
Priority date: 1977-05-10
Filing date: 1978-05-03
Publication date: 1981-02-18
Also published as: FR2390873A1; DE2820150A1

Description

(54) IMPROVEMENTS IN OR RELATING TO COLOUR TELEVISION SYSTEMS (71) We, INDESIT INDUSTRIA ELETTRODOMESTICI ITALIANA S.P.A., an Italian Company, of Str. Piossasco Km. 17, Rivalta, Turin, Italy, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: The present invention relates to a method of transmitting, during a number of television lines within the field blanking cycle of a colour television signal, additional data representative of pages of written text or graphics, the said data being introduced in the form of digital pulse sequences with a pre-established clock frequency and combined with additional pulse sequences containing control and synchronizing data, to a coder for use in such a method and to a receiver which can decode the transmitted text.

An experimental version of this system is currently being used in Great Britain and tested in a number of other countries including West Germany and Italy. This system is known as a Teletext and other similar systems are Ceefax and Oracle (both Registered Trade Marks).

On the Teletext system, data relative to a number of pages of written text or graphics (up to 100 different pages), each consisting of 24 lines of 40 characters, is put into digital (ISO 7) code using the NRZ system and transmitted during two lines (e.g. 15 and 16) of the field blanking cycle of a standard CCIR television signal. During each field, the data relative to two lines of text is transmitted, each preceded by: 1) a RUN-IN 2) a FRAMING CODE 3) a line address Besides the decoding system, the receiver contains a memory for recording all the lines on each page and a character generator for displaying the text or graphics.

The clock frequency used is 6.9375 Megabits/second. Operation of this system is fairly critical owing to the high level of accuracy required from the receiver for regeneration of the clock frequency and the relative scarcity of data (only two RUN-IN's per field, each consisting of eight oscillations). Both these reasons (high level of accuracy required and the scarcity of synchronizing data) explain the complexity, high cost and poor reliability of clock regenerators, which should not be so in that television receivers are articles of wide consumption which it should be possible to mass-produce at low cost.

In CCIR countries, the 6.9375 Megabit/second frequency is too high for the television channel width used (total 7 MHz) and the normal pass band on receivers making operation unreliable.

According to a first aspect of the invention, there is provided a method of transmitting additional information during a number of television lines only within field blanking cycles of a colour television signal wherein the additional data are representative of pages of written text or graphics, the data being introduced in the form of digital pulse sequences with a pre-established clock frequency and being combined with additional pulse sequences containing control and synchronizing data and the clock frequency is selected to equal the frequency of a colour sub-carrier or to equal the frequency of a colour sub-carrier plus or minus an integral multiple of the line frequency.

A second aspect of the invention provides a coder for introducing into colour television signals additional data representative of pages of written text or graphics coded into digital pulse sequences with a given clock frequency, the coder comprising means for coding the said additional data into digital pulse sequences with a clock frequency equal to the frequency of a colour sub-carrier or to the frequency of a colour sub-carrier plus or minus an integral multiple of the line frequency.

A third aspect of the invention provides a television signal receiver comprising means for decoding additional digital signals containing data representative of pages of written text or graphics occuring during field blanking cycles of a received colour television signal and with a clock frequency equal to the frequency of a colour sub-carrier or to the frequency of a colour sub-carrier plus or minus an integral multiple of line frequency and means for displaying the additional data obtained by decoding the additional digital signals.

A fourth aspect of the invention provides a decoder circuit for decoding signals transmitted by a method according to the first aspect of the invention, comprising means for decoding additional digital signals containing data representative of pages of written text or graphics, occurring during field blanking cycles of a received colour television signal and with a clock frequency equal to the frequency of a colour sub-carrier plus or minus an integral multiple of line frequency and means for feeding to a displaying means the additional data obtained by decoding the additional digital signals.

The invention will be further described in detail by way of a non-limiting example, with reference to the accompanying drawings in which: Figure 1 shows the data format and position for a number of transmission lines in an embodiment according to the invention; Figure 2 shows the block diagram of a signal decoder in an embodiment according to the invention; Figure 3 shows a more detailed block diagram of part of the Figure 2 circuits; Figure 4 shows schematically diagrams of waveforms in the Figure 3 circuit; and Figure 5 shows the block diagram of a signal receiver embodying the present invention.

The present invention originated from the fact that a normal colour television signal, such as the well known PAL system signal, contains highly accurate, reliably frequency data, to be more explicit, the colour synchronizing data transmitted at the start of almost all television lines in the form of a so-called "colour burst" of 10 oscillations at colour sub-carrier frequency.

The frequency of the sub-carrier on the PAL system is 4.43361875 MHz. The nature of the burst is such that it has a spectrum with a multiplicity of spectrum lines about 7.8 MHz apart, in the case of the PAL system, and 15.6 MHz if the phase-alternation-by-line characteristic of the PAL system is suppressed.

A clock frequency for the Teletext signal can therefore be selected to equal one of the aforesaid lines : for example, 6.43361875 MHz which corresponds to the 256th line in the alternating burst spectrum and the 128th in the non-alternating spectrum (4433618.75 + 128 x 15625 = 6433618.75). We know that not all of these spectrum lines have the same amplitude but they build-up a sort of festoon curve. The distance between the minimum and maximum ones is the inverse of the burst length.

Of course it is advisable for the frequency being regenerated to correspond to a maximum. In fact, the frequency shown above corresponds more or less to a maximum. In this way, it is possible for the clock regenerator inside the receiver to be synchronized by the burst in place of the RUN-IN so as to improve reliability of the regeneration circuit. The RUN-IN signal can even be done away with.

With a clock frequency of 6.43361875 (Megabits/second and no RUN-IN signal, a total of 41 characters can be arranged per line (52 x 6.43361875 = 334.5; 334.5 + 8 = 41.8) corresponding to 38 actual text characters, as explained below.

It is even possible for the colour sub-carrier oscillation with 4.43361875 MRz frequency (instead of 6.9375 MHz) to be used as a clock frequency for the Teletext signal. Using this lower frequency, receiver band width is no longer a problem in that any receiver has a band width sufficient for receiving it.

The colour burst is usually transmitted at the start of each line whenever colour signals are transmitted. In embodiments of this invention, it is transmitted whenever teletext signals are transmitted. In the case of a Television signal being transmitted using the known PAL system, the burst will be phase alternating for colour broadcasting and non-alternating (fixed phase or PAL OFF) for Teletext transmissions in black and white. The "colour killer" on PAL colour receivers operates normally in that it is controlled by the 7.8 KHz alternating burst. The Teletext data may be in colour even if normal viewing is black and white.

If fitted with a decoder and clock regenerator, even a normal black and white receiver will be able to receive the Teletext signal (in black and white).

By transmitting the burst every line, the clock regenerator is much less complex than in the case of only two RUN-IN signals per field. What is more, colour television sets are already provided with a regenerator in the form of a normal colour sub-carrier regenerator.

With a clock frequency of 6.9375 Megabits/second, a line of 52 microseconds usually accommodates: 52 x 6.9375 = 360 bits or 360 . 8 = 45 characters each of 8 bits (7 data bits and 1 parity bit).

These 45 characters are used as follows: 2 for the RUN-IN 2 for the FRAMING CODE 2 for the line address 40 for the text With a frequency of 4.43361875 Megabits/second, a 52 microsecond line can only accommodate: 52 x 4.43361875 = 230 bits or 230 . 8 = 28 characters. As the RUN-IN is no longer needed, these 28 characters can be used as follows: 1 for the FRAMING CODE 2 for the line address 25 for the text or: 1 for the FRAMING CODE 2 for the line address 5 for other codes or checks 20 for the text In the first case, using 4 television lines per frame (e.g. 15, 16, 20 and 21), 50 characters per line of text can be transmitted against 40 in the second, that is, the number currently transmitted. The 5 extra characters can be used for transmitting additional codes (e.g. for transmitting the page number in each line as opposed to the start of each page as currently used) and for more sophisticated error checks.

For the page headings at the start of each page, besides the normal control signals (RUN-IN, FRAMING CODE, ADDRESS), a further 8 additional control characters are currently transmitted.

The headings thus consists of: 5 normal control characters (including RUN-IN) 8 special control characters 32 text characters The embodiment of system described below has: 3 normal control characters 8 special control characters 17 text characters or: 3 normal control characters 9 special control characters 16 text characters Clearly, this is a great advantage for simplifying both the coder (the clock oscillator is replaced by the existing colour sub-carrier oscillator) and the decoder (the clock generator is no longer needed, for the same reason, if it is a colour set).

Reliability is also improved due thanks to: the use of a lower frequency for the clock; the transmission of a much more powerful sync signal (burst) for the clock; the possibility of inserting additional control characters.

The only requirement for obtaining all these advantages is the use of 4 television lines per field instead of 2. As these lines are already available, it is merely a question of designing the coder and decoder so that the former loads the first half of a given line of text into a given television line during the field retrace (e.g. line 15) then, following the control characters, the second half of the same line of text into the next consecutive television line (e.g. line 16). Following the control characters, it then loads the first half of the next line of text into another preselected television line (e.g. line 20) and, following the control characters, the second half of the same line of text into the next consecutive television line (e.g. line 21) and so on (e.g. first half in line 328, second half in line 329; first half in line 333, second half in line 334, etc.).

In the decoder, the inverse operation is performed, that is, by pairing the two half lines of text so as to reconstruct the original. The decoder is provided with a one-page memory into which the data is loaded gradually as it is received and decoded so as to display the whole page.

Instead of receiving one line at a time, the present system is designed for the memory to receive the text in half lines. In any case, the memory will always receive two complete lines of text per field. Up to now, we have only considered the case of a PAL colour television signal. However, what has been said also applies, subject to variations, to other colour television systems. Let us consider, for example, the SECAM system (registered trade mark) used in France.

The SECAM is a frequency-modulation sequential system in which two different frequencies, known as "red frequency" (4.40625 MHz) and "blue frequency" (4.25 MHz) are transmitted alternately at the start of consecutive television lines. Special identification bursts are also transmitted during the field retrace (lines 7-15). Using the present invention, the Teletext signal can be coded using the 4.40625 Megabit, second frequency as a clock frequency (or a frequency which is a multiple of line frequency, that is, a multiple of 15625 Hz, away from it).

In the receiver, the 4.40625 MHz frequency available at the start of the "red lines" can be sampled using a known electronic gate synchronized by the identification system on the set and operating at half-line frequency. This "red frequency" is then sent to the clock regenerator.

In the case of black and white transmissions with additional Teletext signals, the 4.40625 MHz "red frequency" is transmitted at the start of each line.

In this way, the colour killer on the set comes into operation and disables the colour channel and the clock regenerator receives the sync signal, in any case, from the 4.40625 MHz frequency, even if the half-line-frequency gate is not identified.

The following description will now describe a better way of using the characters made available on the system, using particularly simple circuit arrangements for signal generation and decoding.

In Figure 1, A, B, C and D indicate four data lines, each transmitted in digital code during the line scanning cycle, in the field blanking interval of a CCIR standard television signal. Numbers 1 to 25 indicate consecutive groups of 8 bits (bytes), each representing a given piece of data, usually a character in ISO 7 code with a parity bit. Lines A and B contain information relative to the page heading and lines C and D to a line of data. In more detail, byte No. 1, in line A, represents the starting code (STR) or FRAMING CODE, No.

2 and 3 the line and magazine address (ADR), No. 4 and 5 the page address - units (PNU) and tens (PNT) respectively, No. 6, 7, 8 and 9 the time data - minute units (TMU) and tens (TMT), hour units (THU) and tens (THT) respectively, No. 10 and 11 control characters (CTL) and No. 12-25 (CRT) the first 14 characters of visible data relative to the page heading. In line B, transmitted straight after, bytes No. 1, 2 and 3 are the same as on the foregoing line, bytes No. 4 and 5 are free, while bytes No. 6-25 contain the next 20 characters of text. In line C, bytes 1 to 5 are the same as on line A, while 6 to 25 contain the first 20 characters of text. In line D, bytes 1 to 3 are the same as on line C, 4 to 5 are free, while bytes 6 to 25 contain the second group of 20 text characters.

The start or framing code, transmitted on each line, is represented by the 11100100 binary sequence. The line address is zero for the page heading or a number between 1 and 24 for text lines. The page address is a number between 0 and 99, inserted every two transmission lines at the start of the text and is the same for all lines on the same page. The time and control characters are inserted at the start of each page heading. In Figure 2, the video signal generator 1 supplies a video output signal (S) to a sync separator circuit 2, a burst separator 4 and an adding circuit 5.

Circuit 2 supplies a horizontal-frequency signal (H) to gate signal generator 3 and buffer circuit 6 and a vertical-frequency signal (V) to control circuit 7 and generator 3 which, in turn, supplies an enabling signal (W) to circuit 6 and a burst-key signal to separator 4 and a first input of AND gate 12.

Circuit 7 has a data input (IN), a data and control output (DP) and an address output (AD). Both outputs are connected to data memory 8 and circuit 6 whose output (DS) is connected, through filter circuit 9, to adding circuit 5 at whose output (OUT) the final signal is made available. Outputs DP and AD have more than one connecting wire which is why they are drawn as busses.

The circuit 4 output is connected to a sub-carrier regenerating circuit 10 and detector circuit 11. The output of the latter is connected to a second inverting input by gate 12, the output of which is connected, through filter circuit 13, to adding circuit 5, while the output of circuit 10 is connected to a third input of circuit 12 and circuit 6.

An alternative operation mode is to deactivate or leave out circuits 2 and 10, drawn with a dotted line, in which case signals H, V, S and C are supplied directly by generator 1 (dotted line). The Figure 2 coder operates as follows.

The horizontal and vertical sync signals H and V are separated by circuit 2 from the PAL colour video signal at the output of video generator 1. They are then processed by generator 3 to provide a gate signal for the burst and an enabling signal for inserting the Teletext signal on to the required television lines. Separator circuit 4 then separates the colour subcarrier sync burst from the complete video signal to obtained a phase pull-in of regenerator 10 as 4.43361875 MHz frequency while gate 12 is kept disabled by amplitude detector 11. When in-coming data is received, control circuit 7 makes any necessary adjustments to the contents of data memory 8 and also picks out the data for transmission from the memory (2 lines of text) during the active field cycle. This is then sent to buffer circuit 6 from which it is later extracted, on the pre-arranged lines, during the frame retrace cycle, at the clock frequency of generator 10 (signal DS), filtered by low-pass filter 9 and added to the original video signal in circuit 5.

In this way, a complete video signal is made available at the output of circuit 5 containing additional data relative to pages of text.

In the case of a black and white signal, there are no bursts at the output of separator 4.

This leaves regenerator 10 free running (though it continues to oscillate at close to colour subcarrier frequency) which continues to control data transmission speed. At the same time, detector 11 enables gate 12 which transfers to band-pass filter 13 roughly ten oscillations per line of regenerator 10 which are then added to the other signals in circuit 5.

The result is an output signal containing fixed-phase bursts of the NTSC type.

Figure 3 shqws more detailed diagrams of the circuits shown in blocks 6, 7 and 8 of Figure 2. The signals and circuits common to Figure 2 are shown using the same letters and numbers respectively. Clock signal C is sent through delay circuit 35 to the clock input (CP) of flip-flop 33 and through AND gate 20 to the clock input (CP) of X 8 counter 21. The first two outputs of this counter are connected to the address inputs of RAM memories 29 and 30; to parallel-series converter circuit 31 and to the first two inverter inputs of an AND gate 25. The third output is connected, through AND gate 22, to the clock input.(CP) of a second 5-bit counter 23, to a third input of gate 25, and, through inverter 24, to a further address input of RAM memories 29 and 30 and to circuit 31.

Line-frequency signal H is sent to the clock input (CP) of a X 4 counter 26 and to the reset input (R) of counter 21 and counter 23, the 5 outputs of which are connected, in numerical order, to the 5 inputs of AND gate 27, the second and third of which are inverter inputs, as well as to further address inputs of memories 29 and 30.

The output of-gate 27 is connected to the second input of gate 20, to the fourth input of gate 25 - both inverter inputs - and to the set input (S2Of flip-flop 28. This has its reset input (R) connected to the output of gate 25 and its output Q to the control input of gate 22 and to a first input of NAND gate 34 which has its output connected to the reset input (R) of 33.

The vertical-frequency signal W for enabling the insertion of digital data is applied to the second input of gate 34 and the reset input (R) of X 4 counter 26, the output of which is connected to further address inputs of memories 29 and 30.

The vertical-frequency signal V is applied to an input of control unit 7 which receives the data for transmission at its data input (IN). Control circuit 7 supplies the line and page addresses, the data for loading into the memory and the read-print control to the respective inputs (ADD, D and R/W) of memory 30, the read-print control (R/W) to memory 29 and control signal sequences to circuit 31. Circuit 7 is also connected to the (ADD) addresses of memory 29 so as to be able to supply addresses in place of counters 21, 26 and 23 when memory 29 is in the "WRITE" condition.

The output of memory 30 is connected to the input of parity generator 32, in turn connected to the input of circuit 31. This has its output connected to the data input of memory 29 the output of which is connected to the data input (D) of flip-flop 33 at whose output the signal (DS) to be sent to circuit 9 of Figure 2 is made available.

The operation of the Figure 3 circuit will now be described with reference to Figure 4 which shows a number of wave forms present at various points on the Figure 3 circuit. Line "a" shows the clock signal at input C; line "b" the horizontal-frequency signal H; line "c" the clock signal at the input (CP) of counter 21; lines "d", "e" and "f" the three outputs of counter 21, starting with the least significant; lines "g" and "h" the two least and most significant outputs (weight 1 and 16 respectively) of counter.23; lines "i", "l" and "m" the reset input (R), set input (S) and output (Q) of flip-flop 28 and, finally, lines "n" and "o" the bit and byte count.

During the active field interval (signal V), control circuit 7, which may consist of a microprocessor programmed using known techniques, supplies enabling signals and addresses for transferring the data relative to 2 lines of text, contained in data memory 30, which can hold up to 100 pages of 24 lines and 40 characters, into buffer memory 29. As this is a serial memory (1K x 1 for accommodating 4 lines of 45 8-bit characters), the 7-parallel-bit data coming from data bank 30, to which an eighth parity bit is added by circuit 32, is converted into series by circuit 31 which receives 3 address bits (the least significant) common to memory 29.

Control circuit 7 also supplies circuit 31 directly with service data to be inserted at the start of each line, such as the start code and line and page addresses including safety bits using the Hamming code.

If required, control circuit 7 can also receive outside data (from a series data transmission terminal, for example) in which case it alters the contents of the relative data bank pages.

The data transfer cycle from memory 30 to 31 is repeated every field until all the pages in the memory have been transferred after which the cycle starts again. During each field retrace, therefore, memory 29 contains all the data (text and service relative to two lines of text for series transmission during four television lines. This is brought about by line-frequency (line blanking) signal H releasing counters 21 and 23 at the start of the active line cycle. Bit counter 21 then starts advancing at the first clock signal leading edge it receives (lines "b", "c" and "d" of Figure 4) while counter 23 advances every 8 bits to keep count of the bytes. The function of gate 27 is to wait for the counter to reach 25 after which it disables the clocks at the inputs of counter 21 (lines "a" and "c" of Figure 4) to stop the count and switch flip-flop 28. The function of gate 25 is to detect count 4 on counter 21 (line "i" of Figure 4) which is the instant chosen for starting transmission, delayed by a minimum of 3 and a maximum of 4 clock cycles, depending on the relative clock and line sync phase which may vary in time inthat the clock frequency is not a whole multiple of line frequency.

On each line, output Q of flip-flop 28 supplies the exact interval in which to insert the data corresponding to 25 x 8 clock cycles. The function of inverter 24 and gate 22 is to delay the bit and byte counts by 4 clock cycles, that is, to supply memory 29 with address 0...0 the instant data insertion is begun.

The X 4 counter 26, which is zeroed by field-frequency signal W and advances every line, completes the address of memory 25 which supplies an output pulse sequence corresponding to 4 transmission lines. Flip-flop 33 is a sampling-squaring circuit which samples the output of the memory at clock frequency and with a suitable phase (delay T) so as to supply a synchronous-switching output signal unaffected by delays in memory response. This flip-flop is disabled by gate 34 at the end of each set of data and kept disabled until the next set is begun. Number 50, in Figure 5, indicates the television signal receiver intermediatefrequency amplifier. This is connected to a video detector circuit 51 the output of which is connected to a video amplifier 52 and an audio processing and amplifying circuit 84. This has its output connected to loud speaker 85, band-pass filter 53, sync regenerating circuit 54 and processing circuit 60. The output of filter 53 is connected to chroma amplifying circuit 55 which supplies a subcarrier regenerating circuit 57 and demodulating circuit 56. This receives the output of regenerator 57 at a subcarrier input and supplies two colourdifference output signals (R-Y) and (B-Y) which are applied to two inputs of matrix circuit 58. The third input of this circuit is connected to the output of amplifier 52 which supplies three outputs to the first 3 inputs of switch circuit 59.

The output of processing circuit 60 is connected to an input (IN) of a series-parallel (1 to 8) converter circuit 61 the output of which is connected to a latch circuit 62 and key-word detector circuit 63.

The 8-bit output of circuit 62 is connected to a parity detector 69, decoding circuit 81, memory 82 and control circuit 76.

The output of circuit 63 is connected to an enabling input (OE) of circuit 62, a first input of switch 65, a first input of OR gate 70 and the reset input (R) of a X 8 counter 64. This has its input (CP) connected to the output of regenerator 57, a first output connected to the clock input (CP) of latch circuit 62 and a first input of switch circuit 66 and a second output connected to a second input of OR gate 70.

The second input and control input of switch 65 are connected to the two outputs (H) and (V) of circuit 54 respectively while the output is connected to the reset input (R) of a X 4 counter 72. This has its two outputs connected separately to two inputs of control circuit 76, decoding circuit 81 and NAND gate 73. The output of the latter is connected to a first input of OR gate 74 and a first input of AND gate 71 the output of which is connected to the clock input (CP) of counter 72.

The second input and control input of switch 66 are connected to the output of a one-sixth divider circuit 68 and output V of circuit 54 respectively while the output is connected to the second input of gate 71 and the clock input (CP) of a X 20 counter 75. This has a first (5-bit) output connected to control circuit 76 and memory 82 and a second output connected to the reset input (R) of circuit 63, the set input (S) of flip-flop 80 and the second input of OR gate 74. The reset input (R) is also connected to the output of gate 74.

Decoder circuit 81 has its output (line address) connected to control circuit 76 and the first address inputs of memory 82. The second address inputs of the latter are connected to the output of counter 75 and control circuit 76 while a further address input is connected to the output of flip-flop 80.

Control circuit 76 has yet another output connected to a first inverter input of OR gate 78 and, through condenser 79, to the reset input (R) of flip-flop 80, an output connected to the control inputs of switch 59 and circuit 84, two synchronizing inputs connected to outputs (H) and (V) of circuit 54 respectively as well as an input connected to keyboard 77. The output of circuit 69 is connected to the third input of OR gate 70. This has its output connected to the second input of OR gate 78 the output of which is connected to the read-write input (R-W) of memory 82.

Output H of circuit 54 is also connected to a first control input of a character generat6r 83 and a synchronizing input of oscillator 67 the output of which is connected to the clock inputs (CP) of frequency divider 68 and character generator 83. The latter also has- a second control input connected to output V of circuit 54, a data input connected to the data output of memory 82 and three outputs connected to three inputs of switch 59. Three colour signals R, G and B are made avai accurate vertical character alignment.

The advantages of the present invention will be seen from the description given.

Waiting time, in particular, is reduced by inserting the page address every half data transmission line which also provides the possibility of changing the order in which lines are transmitted.

A number of changes can be made to the system described. For example, it is possible to transmit 28 instead of 25 characters per line and insert the 5 service characters on alternate lines so as to have 51 text characters per line.

The clock frequency may differ from the colour subcarrier frequency by an amount equivalent to a multiple of line frequency. In this case, the clock regenerator in the receiver must have an additional oscillator, this too being phase synchronized by the burst.

Looking at Figure 5 which shows an example of a receiver if control circuit 76 consists of a suitably programmed microprocessor, it may be convenient to use this for performing functions which, in the example shown, are performed-by distinct circuits.

To those skilled in the art, it will be clear that many other changes can be made to the system described without departing from the scope of the present invention as defined in the appended claims.

WHAT WE CLAIM IS: 1. A method of transmitting additional information during a number of television lines only within field blanking cycles of a colour television signal wherein the additional data are representative of pages of written text or graphics, the data being introduced in the form of digital pulse sequences with a preestablished clock frequency and being combined with additional pulse sequences containing control and the clock frequency is selected to equal the frequency of a colour sub-carrier or to equal the frequency of a colour subcarrier plus or minus an integral multiple of the line frequency.

2. A method according to claim 1 wherein, for black and white broadcasting, a train of oscillations is transmitted at the start of each line with the frequency of said colour sub-carrier and with a constant phase in each line.

3. A method according to claim 1 wherein the signal representative of each line of the said pages of written text is transmitted over to adjacent television lines and at least one of the said control signals is inserted every first and omitted every second transmission line.

4. A method according to claim 3 wherein the said control signals omitted only every second line represent that page number of the data.

5. A method according to claim 4 wherein no control signals are transmitted every second line.

6. A method according to claims 3 and 4 wherein only a framing-code control signal is transmitted every second line.

7. A method according to any one of claims 3 to 5 wherein the control signals omitted are replaced by data characters.

8. A method according to any one of the preceding claims wherein no synchronising signals are transmitted during an active scanning cycle.

9. A method according to any one of the preceding claims wherein the television signal is a PAL colour signal.

10. A method according to claim 9 wherein the clock frequency is 4.43361875 MHz and the synchronising data comprises burst signals.

11. A coder for use in the method of claim 10, the coder being arranged to insert said additional data during said field blanking cycles of the colour television signal and comprising a clock signal generator circuit arranged to be synchronised in phase by the colour bursts of said colour television signal.

12. A coder according to claim 11 and which includes adding means, which, in the absence of a burst signal in the colour television signal, add to said colour television signal a number of clock signal oscillations during line retrace intervals.

13. A coder according to claim 12 and which includes a memory circuit arranged to be loaded with data representative of two lines of text or graphics during an active field cycle and to be read from during four line scanning cycles in a following field blanking interval.

14. A coder according to claim 13 and which includes a sampling circuit controlled by the clock generator and inserted in the path of an output signal of the memory circuit.

15. A television signal receiver comprising means for decoding additional digital signals containing data representative of pages of written text or graphics occurring during field blanking cycles of a received colour television signal and with a clock frequency equal to the frequency of a colour sub-carrier or to the frequency of a colour sub-carrier plus or minus an integral multiple of line frequency and means for displaying the additional data obtained by decoding the additional digital signals.

16. A receiver according to claim 15 and comprising a single circuit for regenerating both the colour sub-carrier and the clock frequency which circuit remains operative even

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. accurate vertical character alignment. The advantages of the present invention will be seen from the description given. Waiting time, in particular, is reduced by inserting the page address every half data transmission line which also provides the possibility of changing the order in which lines are transmitted. A number of changes can be made to the system described. For example, it is possible to transmit 28 instead of 25 characters per line and insert the 5 service characters on alternate lines so as to have 51 text characters per line. The clock frequency may differ from the colour subcarrier frequency by an amount equivalent to a multiple of line frequency. In this case, the clock regenerator in the receiver must have an additional oscillator, this too being phase synchronized by the burst. Looking at Figure 5 which shows an example of a receiver if control circuit 76 consists of a suitably programmed microprocessor, it may be convenient to use this for performing functions which, in the example shown, are performed-by distinct circuits. To those skilled in the art, it will be clear that many other changes can be made to the system described without departing from the scope of the present invention as defined in the appended claims. WHAT WE CLAIM IS:

1. A method of transmitting additional information during a number of television lines only within field blanking cycles of a colour television signal wherein the additional data are representative of pages of written text or graphics, the data being introduced in the form of digital pulse sequences with a preestablished clock frequency and being combined with additional pulse sequences containing control and the clock frequency is selected to equal the frequency of a colour sub-carrier or to equal the frequency of a colour subcarrier plus or minus an integral multiple of the line frequency.

when a colour burst in the television signal is non-phase-alternating and a -colour killer circuit which is operative when the burst signal is non-phase-alternating.

17. A receiver according to claim 15 or 16 and adapted for use with a PAL colour television signal.

18. A receiver according to claim 15 and adapted for use with a S.E.C.A.M. colour television signal.

19. A receiver according to claim 18 and including a clock regenerator operative at the frequency of the colour sub-carrier or at the frequency of the colour sub-carrier plus or minus a multiple of the line frequency.

20. A coder for introducing into colour television signals additional data representative of pages of written text or graphics coded into digital pulse sequences with a given clock frequency, the coder comprisng means for coding the said additional data into digital pulse sequences with a clock frequency equal to the frequency of a colour sub-carrier or to the frequency of a colour sub-carrier plus or minus an integral multiple of the line frequency.

21. A coder according to claim 20 and adapted for use with a PAL colour television signal.

22. A coder according to claim 20 and adapted for use with a SECAM colour television signal.

23. A television signal receiver comprising means for decoding additional digital signals containing data representative of pages of written text or graphics present during the field blanking cycles in a received colour television signal with a clock frequency equal to a colour sub-carrier frequency or to the frequency of a colour sub-carrier plus or minus an integral multiple of line frequency: means for displaying the additional data obtained by decoding the additional digital signals and a clock signal regenerator comprising an oscillator arranged to be phase-synchronised by colour sub-carrier bursts in the received colour television signal.

24. A receiver according to claim 23 wherein the clock regenerator is arranged to serve also as a colour sub-carrier regenerator.

25. A receiver according to claim 24 and comprising means for serial to parallel conversion, synchronised by the clock regenerator. of the additional digital signals.

26. A receiver according to claim 25 and including counting means controlled by the said clock signal for supplying a number corresponding to the position of each received character in a scanning line.

27. A receiver according to claim 26 and including a second oscillator circuit for controlling the width of the characters reproduced.

28. A receiver according to claim 27 and comprising a first set of switching means for connecting the counting means to the clock regenerator or to the second oscillator circuit during data reception and display. respectively.

29. A receiver according to claim 28 wherein the additional data display means includes a colour and luminance video signal matrix circuit. a character generating circuit and a second set of switching means for sending the signals from the first or second circuit to a video display.

30. A receiver according to claim 29 and comprising a control key-board connected to a control circuit which also acts on the second set of switching means.

31. A method of transmitting additional information with a colour television signal, such method being substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

32. A coder for inserting additional information into a colour television signal constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

33. A television receiver constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

34. A decoder circuit for decoding signals transmitted by a method according to any one of claims 1 to 10. comprising means for decoding additional digital signals containing data representative of pages of written text or graphics. occurring during field blanking cycles of a received colour television signal and with a clock frequency equal to the frequency of a colour sub-carrier plus or minus an integral multiple of line frequency and means for feeding to a displaying means the additional data obtained by decoding the additional digital signals.

35. A decoder circuit constructed and arranged to operate substantially as hereinbefore described with reference to, and as illustrated in the accompanying drawings.