GB1566540A - Amplified gate thyristor - Google Patents
Amplified gate thyristor Download PDFInfo
- Publication number
- GB1566540A GB1566540A GB22195/78A GB2219578A GB1566540A GB 1566540 A GB1566540 A GB 1566540A GB 22195/78 A GB22195/78 A GB 22195/78A GB 2219578 A GB2219578 A GB 2219578A GB 1566540 A GB1566540 A GB 1566540A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- gate
- diode
- thyristor
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003071 parasitic effect Effects 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 35
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 230000035945 sensitivity Effects 0.000 description 6
- 230000003321 amplification Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- OQCFWECOQNPQCG-UHFFFAOYSA-N 1,3,4,8-tetrahydropyrimido[4,5-c]oxazin-7-one Chemical compound C1CONC2=C1C=NC(=O)N2 OQCFWECOQNPQCG-UHFFFAOYSA-N 0.000 description 1
- 101100129922 Caenorhabditis elegans pig-1 gene Proteins 0.000 description 1
- 101100520057 Drosophila melanogaster Pig1 gene Proteins 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7428—Thyristor-type devices, e.g. having four-zone regenerative action having an amplifying gate structure, e.g. cascade (Darlington) configuration
Description
(54) AMPLIFIED GATE THYRISTOR
(71) We, CUTLER-HAMMER WORLD TRADE INC., a Corporation organised and existing under the laws of the state of Delaware, United States of
America, of 4201 North 27th Street, Milwaukee, Wisconsin 53216, United States of
America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a thyristor with an amplifier integrated in its gate.
A short-emitted thyristor is one which, for example, has electrode metallization ohnically contracting both a cathode emitter region and a cathode base region, wherein the cathode base region has a separate gate electrode connected thereto. This type of configuration decreases gate sensitivity because of the short, thus requiring greater gate current to drive the thyristor into conduction.
This configuration does, however, have the advantage of minimizing unwctilted temperature and dv/dt effects.
One known manner of increasing gate sensitivity, then, is to use a nonshortedemitter configuration wherein the electrode metallization on the cathode emitter does not also contact the cathode base. This may not be acceptable, however, in applications where temperature and dv/dt considerations cannot be sacrificed.
A known manner of increasing gate sensitivity, with a shorted-emitter configuration, is to include auxiliary means in the gate circuit of the power thyristor. Such means may be either discrete from or integrated on a common substrate with the power thyristor. In the case of the latter, it is known to integrate an auxiliary or pilot thyristor on the same substrate with a power thyristor for controlling gate current thereto. The pilot thyristor fires first in response to gate current applied thereto, after which the power thyristor fires in response to gate current enabled by conduction of the pilot thyristor, the latter gate current being that current flowing through the pilot thyristor in its low resistance, high current "on" state.
In accordance with the present invention, there is provided an amplified gate semicpnductor switch, comprising a thyristor having a gate and at least one diode integrated on a common substrate with said thyristor and connected to said gate. said diode and said substrate forming a parasitic transistor for amplifying gate current applied through said diode to said gate. In embodiments to be described herein, amplification is enabled by the parasitic transistor formed by the diode in conjunction with the substrate which affords additional gate current in the form of collector current. The junction formed by the thyristor anode region and the substrate is forward biased to afford a source of collector current for the parasitic transistor. Collector current flows from the substrate to the diode anode region to the diode cathode region, i.e. from collector to base to emitter, respectively.
In these embodiments, gate current flows through the diode to the thyristor.
Initial gate current applied to the diode anode region is effectively the base current applied to the base of the parasitic transistor. The final gate current applied to the thyristor is thus amplified because it comprises the initial gate current applied to the diode plus the additional collector current afforded by the parasitic transistor.
Gate sensitivity is also increased in another manner because the parasitic transistor action increases the injection efficiency of the thyristor emitter and hence the required value of gate drive current is reduced.
By both reducing the required value of gate drive current and simultaneously amplifying the applied gate current, these embodiments afford substantially increased gate sensitivity.
An advantageous feature of these embodiments is that the amplified gate current is substantially independent of both temperature and dv/dt induced variations in the performance of the parasitic transistor, whereby not to detract from the temperature and dv/dt insensitivity of a shorted-emitter thyristor.
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
FIGURE 1 is a section through a substrate showing thyristor 2 and a diode 4 integrated therein:
FIGURE 2 is a circuit diagram of Figure 1;
FIGURE 3 is an equivalent circuit diagram illustrating the parasitic transistor formed by the embodiment of Figure 1;
FIGURE 4 is a section through a second embodiment, like Figure 1, but with triple diode integration; and
FIGURE 5 is an equivalent circuit diagram illustrating the parasitic transistors formed by the embodiment of Figure 4.
There is shown in Fig. 1 an amplified gate thyristor constructed in accordance with the invention comprising a thyristor 2 and a diiode 4 integrated on a common substrate 6.
Thyristor 2 has four layers comprising: an anode emitter P type region 8; an anode base N type region 10, formed by a portion of substrate 6; a cathode base P type region 12; and a cathode emitter N type region 14. Regions 8 and 14 have anode and cathode terminals A and K, respectively, connected ohmically thereto.
A gate terminal G is ohmically connected to region 12 for gating the thyristor into conduction.
Diode 4 has a rectifying Junction 16 formed by P type anode region 18 and
N type cathode region 20. A gate terminal Gl is ohmically connected to diode anode region 18, and diode cathode region 20 is ohmically connected to region 12 of the thyristor.
Fig. 2 shows the schematic circuit diagram of the embodiment of Fig. 1. Gate current applied at Gl flows through diode 4 to trigger thyristor 2 into conduction whereby load current may flow from anode A to cathode K when a power source is connected thereacross. Gate current may also be applied at terminal G to trigger thyristor 2 into conduction.
It has been found that the gate current necessary to trigger thyristor 2 into conduction is substantially less when applied at terminal Gl than when applied at
G. This is because gate current applied at Gl is amplified by a parasitic transistor formed by diode 4 and substrate 6.
Referring to Fig. 1, N type region 20 forms an emitter; P type region 18 forms a
base, and N type substrate 6 forms a collector, thus forming an NPN transistor 22.
Electron flow is indicated by the dashed lines. Anode region 8 of thyristor 2 is positively biased and forms a collector connection to NPN transistor 22 through the forward biased anode-substrate PN junction 24.
Junction 24 is not an active junction with respect to junction 26 of the transistor because the distance therebetween is too great, i.e. minority carrier
injection from region 8 across junction 24 does not substantially affect the characteristics of junction 26. Junction 24 is, however, an active junction with respect to junction 28 of the thyristor because minority carrier injection across junction 24 does substantially affect the characteristics ofjunction 28. It is because juction 24 is inactive with respect to junction 26 that a parasitic transistor is formed by regions 6, 18 and 20; it is because junction 24 is active with respect tojunction 28 that a thyristor is formed by regions 8, 10, 12 and 14.
Fig. 3 shows the schematic circuit diagram of the parasitic transistor formed by the embodiment of Fig. 1. Substrate 6 forms the collector region of parasitic transistor 22, thus affording amplification of current applied at Gl. This amplified current triggers thyristor 2 into conduction. Base current Ig, flowing into terminal
Gl results in collector current BIg,, shown in solid line in Fig. I, where ss is the current gain of transistor 22. pIg1 is an additional forward bias current at the anodesubstrate junction 24, which increases the injection efficiency of anode emitter 8 of the thyristor. This additional current ,Blgl enables a lower initial gate current Ig, to be used.
The final amplified gate current Ig applied to the gate of the power thyristor is the initial gate current Ig, applied to the diode anode plus the additional collector current pIg, afforded by the parasitic transistor, i.e.
Ig = Ig1 + ssIg1 =( + I)lg, Fig. 4 shows a triple diode configuration as a modification of Fig. 1; and Fig. 5 shows the circuit diagram thereof. If only terminal G3 is driven, then, Ig2 = A31g3 + Ig3
= (ss3 + 1)Ig3
and
Ig1 = (ss2 + 1)Ig3
= (ss2 + 1)(ss3 + 1)Ig3
Thus the total additional bias current Ib across junction 24 is
Ib = ss1Ig1 + ss2Ig2 + ss3Ig3
= [ss1(ss2 + 1)(ss3 + 1) + ss2(ss3 + 1) + ss3]Ig3.
This additional forward bias current at the anode substrate junction 24 of thyristor
2 increases the injection efficiency of the anode emitter 8 of the thyristor. Thus the
gate gain
Ib 1g3 is
Ib
= ss1(ss2 + 1)(ss3 + 1) + ss2(ss3 + 1) + ss3
Ig3
The 's are not dependent upon location with respect to P type region 8, but only
upon the NPN parasitic transistor design.
Since metallization 30 ohmically contacts regions 12 and 14, thyristor 2 is of a
shorted-emitter design and thus has good temperature and dv/dt characteristics,
while still affording an amplified gate since, in Figs. 4 and 5,
Ig = (p1 + 1)Ig1
= (ss1 + 1)(ss2 + 1)Ig2
= (ss1 + 1)(ss2 + 1)(ss3 + 1)Ig3.
If the diodes are formed alike, then ss1 = ss2 = ss3 = ss, and
Ig = (ss + 1) Ig3.
More generally, Ig = (p + 1 )nIgn where n is the number of diodes integrated on the
same substrate with the thyristor. For example, with a typical ss = 9, the triple diode
integration shown in Fig. 4 yielded gate current amplification on the order of 103.
As aforenoted, ssIg1 is an additional forward bias current at anode-substrate
junction 24. This additional bias current increases the injection efficiency of anode
emitter 8 with respect to thyristor 2 and hence reduces the required gate drive
current otherwise needed to trigger thyristor 2. Increasing the injection efficiency
of anode emitter 8 increases that respective a of the thyristor, whereby less gate
current is necessary to raise the sum of the thyristor 's to unity.
Besides the temperature insensitivity of thyristor 2 enabled bv the shorted
emitter configuration thereof, the present invention also enables the amplified gate
current Ig to be insensitive to temperature induced variations of the parasitic transistor performance, as will presently be explained.
The equation from above Ig = (ss1 + 1)Ig1 is modified to include temperature induced collector leakage current Is1, Ig = (ss1 + 1)(Ig1 + Is1) where Is1 is the leakage current at the collector-base junction 26, Fig. 1 of the parasitic tarnsistor, and thus
Ig = (ss1 + 1)Is1 + (ss1 + 1)Ig1.
Accounting for the collector leakage currents Is2 and Is3 for the second and third transistors, respectively, Fig. 4, it fallows:
Ig1 = (ss2 + 1)(Ig2 + Is2)
Ig = (ss,+ I)ls, + (A, + 1)(ss2 + 1)(Ig2 + Is2)
= (ss1 + 1)Is1 + (ss1 + 1)(ss2 + 1)Is2 + (ss1 + 1)(ss2 + 1)Ig2
Ig2 = (ss3 + 1)(Ig3 + Is3)
Ig = (ss1 + 1)Is1 + (ss1 + 1)(ss2 + 1)Is2 +
(ss1 + 1)(ss2 + 1)(ss3 + 1)Is3 +
(ss1 + 1)(ss2 + 1)(ss3 + 1)Ig3
If ss1 = ss2 = ss3 = ss, Is1 = Is2 = Is3 = Is, the last equation for Ig can be written
Ig = (ss + 1) Ig3 + Is(ss + 1)[1 + (ss + 1) + (ss + 1)]
= (ss + 1) Ig3 + Is(ss + 4ss + 6ss + 3).
The collector leakage current can be written in terms of current density Js and area As so that Is = AsJs where As is the area of the collector-base junction, e.g. 26,
Fig. 1, of the parasitic transistor and Js is the current density thereat. Substituting into the last equation for Ig,
Ig = (ss + 1) Ig3 + AsJs(p3 + 4,B2 + 6ss + 3).
The temperature induced current is the term As Js (ss + 4ss + 6ss + 3), hence to reduce temperature sensitivity of Ig it is seen that (ss + 1) Ig3 must be substantially greater than the temperature induced current, i.e.
(ss + 1) Ig3 As Js(ss + 4ss + 6ss + 3), whereby (ss + 1) Ig3 will be the dominant term in the last-noted equation for Ig, and
AsJs(ss + 4ss + 6ss + 3) can be disgregarded as insignificant with respect thereto. For a typical ss of 9, (ss + 1) is approximately equal to (ss + 4ss + 6ss + 3), i.e. 10 is approximately equal to 1.11 x 10 , respectively, and hence the above-noted condition for temperature independency is
Ig3
Ig3 AsJs or equivalently As .
Js
Current density Js is typically on the order of 10-5 amps per square centimeter at 4000K, and a typical gate triggering current Ig3 is typically on the order of 10-5 amps. Thus
Ig3 10-5 amps
= 1 cm.
Js 10-5 amp/cm
Hence, in order to achieve temperature insensitivity of Ig, the following must be satisfied:
As < I square centimeter.
The dimensions of P type region 18, Fig. 1, are typically about 6 mils by 6 mils by 2 mils deep. The leakage current will appear over the area of P type region 18, thus,
As = (6 mils x 6 mils) + (2 mils x 6 mils x 4)
= 84 mils2
= 5.4 x 10-4 cm2.
Since 5.4 x 10-4 cm2 is much less than 1 cm2, it is thus seen that the above requirement for temperature insensitivity is met. Even for large diodes, e.g. 60 mils by 40 mils by 2 mils whereby As + 1.8 x 10-2 cm2, the above requirement is met and
Ig is temperature independent.
The requirement for dv/dt insensitivity is similar to the temperature insensitivity requirement explained above. Keeping the collector area of the parasitic transistor small will keep the dv/dt induced base current small relative to the applied gate current Ig,, Fig. 1, or Ig3, Fig. 3.
It is recognised that various modifications of the present invention are possible within the scope of the appended claims, for example, though an SCR is specifically disclosed in Fig. 1, a bilateral thyristor configuration can easily be constructed.
Claims (23)
1. An amplified gate semiconductor switch, comprising a thyristor having a gate and at least one diode integrated on a common substrate with said thyristor and connected to said gate, said diode and said substrate forming a parasitic transistor for amplifying gate current applied through said diode to said gate.
2. A switch according to claim 1, wherein said diode comprises first and second contiguous regions of opposite conductivity types, for said gate current to be initially applied to said first region of said diode, said second region of said diode being connected to said gate, and wherein said substrate comprises one of the emitter and collector of said parasitic transistor, said second region of said diode comprises the other of the emitter and collector of said parasitic transistor, and said first region of said diode comprises the base of said parasitic transistor, said substrate forming a junction with an opposite conductivity type region of said thyristor which Junction is inactive with respect to said diode and is biased to provide a current source for said parasitic transistor to thus amplify gate current initially applied to said first region of said diode, being said base of said parasitic transistor, whereby to apply an amplified gate current to said gate.
3. A switch according to claim 1, wherein said gate comprises a gate region of one conductivity type in said thyristor, said diode comprises a first region of said one conductivity type contiguous to a second region of opposite conductivity type, said second region of said diode being ohmically connected to said gate region of said thyristor whereby said diode is connected in series-aiding direction with said gate such that initial gate current applied to said first region of said diode flows through said diode to said gate.
4. A switch according to claim 3, wherein said substrate is of said opposite conductivity type and forms a collector of said parasitic transistor, said first region of said diode forming a base of said parasitic transistor, and said second region of said diode forming an emitter of said parasitic transistor, whereby current appliedto said gate comprises said initial gate current plus additional collector current afforded by said parasitic transistor, said additional collector current being enabled by application of said initial gate current to said first region of said diode which is said base of said parasitic transistor, whereby said initial gate current is amplified.
5. A switch according to claim 4, wherein said thyristor comprises an anode region of said one conductivity type which forms a junction with said substrate which is inactive with respect to said diode, said junction being biased to afford a source of said collector current.
6. A switch according to claim 5, wherein the action of said parasitic transistor increases the injection efficiency across said junction with respect to said thyristor, whereby to reduce the required value of gate current necessary to trigger said thyristor into conduction.
7. A switch according to claim 5, wherein said thyristor comprises four contiguous layers: the first layer being said anode region of said one conductivity type which forms an anode emitter; the second layer being a portion of said suusiraie of said opposite conductivity type which forms an anode base; the third layer being said gate region of said one conductivity type which forms a cathode base; and the fourth layer being a region of said opposite conductivity type which forms a cathode emitter.
8. A switch according to claim 7, wherein said four layers of said thyristor are aligned in said substrate and wherein said diode is laterally offset therefrom to insure that said junction between said thyristor anode region and said substrate is inactive with respect to said diode.
9. A switch according to claim 8, wherein said diode is isolated from said thyristor gate region by said substrate.
10. A switch according to claim 8. wherein said second region of said diode is isolated from said substrate by said first region of said diode, and wherein said first region of said diode is isolated from said thyristor gate region by said substrate.
11. A switch according to claim 7, comprising an anode electrode ohmically connected to said first layer of said thyristor, and a cathode electrode ohmically connected to both said third and fourth layers of said thyristor, to thus afford a shorted-emitter thyristor.
12. A switch according to claim 11, arranged so that the amplified gate current is substantially independent of temperature and dv/dt induced variations in the performance of said parasitic transistor.
13. A switch according to claim 12, arranged so that thermally induced collector leakage current across the junction between said substrate and said second region of said diode, which is the collector-base junction of said parasitic transistor, is at least one order of magnitude less than said gate current.
14. A switch according to claim 1, arranged so that the action of said parasitic transistor increases the injection efficiency across an emitter-base junction of said thyristor whereby to reduce the required value of gate current necessary to trigger said thyristor into conduction.
15. A switch according to claim 1, arranged so that the amplified gate current is substantially independent of temperature induced variations in the performance of said parasitic transistor.
16. A switch according to claim 15, arranged so that thermally induced collector leakage current across said parasitic transistor is at least one order of magnitude less than said gate current.
17. A switch according to claim 1, arranged so that the amplified gate current is substantially independent of dv/dt induced variations in the performance of said parasitic transistor.
18. A switch according to claim 14, arranged so that the amplified gate current is substantially independent of temperature and dv/dt induced variations in the performance of said parasitic transistor, and said thyristor is of shorted-emitter configuration to afford temperature and dv/dt insensitivity of said thyristor.
19. A switch according to claim 1, comprising a plurality of said diodes integrated on said common substrate with said thyristor and serially connected to said gate, said diodes and said substrate forming a plurality of parasitic transistors for amplifying said gate current applied serially through said diodes to said gate.
20. A switch according to claim 19, wherein each said diode comprises first and second contiguous regions of opposite conductivity types, the second region of a preceding diode being connected to the first region of an immediately succeeding diode, said gate current being initially applied to the first region of the first said diodes, the second region of the last of said diodes being connected to said gate, said second regions of said diodes forming one of the emitter and collector of the respective parasitic transistor, said substrate forming the other of the emitter and collector of the respective parasitic transistor, and said first regions forming the base of the respective parasitic transistor, said substrate forming ajunction with an opposite conductivity type region of said thyristor which junction is inactive with respect to said diodes and is biased to provide a current source for said parasitic transistors, such that amplified current from each preceding parasitic transistor is applied to the base of the immediately succeeding parasitic transistor whereby each succeeding parasitic transistor amplifies amplified current from the immediately preceding parasitic transistor.
21. A switch according to claim 20, wherein said gate comprises a gate region of one conductivity type in said thyristor, said second regions of said diodes are of opposite conductivity type and comprise emitters of said parasitic transistors, said first regions of said diodes are of said one conductivity type and. are ohmically connected to the second region of the immediately preceding diode, said second
region of said last diode being ohmically connected to said gate region, whereby
gate current initially applied to said first region of said first diode flows serially through said diodes to said gate region, and wherein said substrate is of said opposite conductivity type and forms a common collector for said parasitic transistors, said substrate forming said junction with a thyristor region of said one conductivity type separate from said gate region, said junction providing a common source of collector current for said parasitic transistors, whereby current applied to said gate region comprises initial gate current applied to said first region of said first diode plus additional collector currents supplied from said junction through each of said parasitic transistors.
22. A switch according to claim 21, wherein said diodes are formed alike and each has a current gain p whereby the ratio of said current applied to said gate region and said initial gate current applied to said first region of said first diode is equal to ( + 1)", where n is the number of said diodes.
23. An amplified gate semiconductor switch, substantially as herein described with reference to Figures 1 and 3 or 4 and 5 to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US86074277A | 1977-12-14 | 1977-12-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1566540A true GB1566540A (en) | 1980-04-30 |
Family
ID=25333922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB22195/78A Expired GB1566540A (en) | 1977-12-14 | 1978-05-24 | Amplified gate thyristor |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5480092A (en) |
| DE (1) | DE2846697A1 (en) |
| FR (1) | FR2412169A1 (en) |
| GB (1) | GB1566540A (en) |
| IT (1) | IT7869170A0 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0118309A2 (en) * | 1983-03-03 | 1984-09-12 | Texas Instruments Incorporated | Semi conductor device and starter circuit for a fluorescent tube lamp, provided with such a semi conductor device |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5617067A (en) * | 1979-07-20 | 1981-02-18 | Hitachi Ltd | Semiconductor switch |
| SE423946B (en) * | 1980-10-08 | 1982-06-14 | Asea Ab | TYRISTOR DEVICE FOR SELF-IGNITION |
| DE3240564A1 (en) * | 1982-11-03 | 1984-05-03 | Licentia Patent-Verwaltungs-Gmbh | CONTROLLABLE SEMICONDUCTOR SWITCHING ELEMENT |
| EP0108874B1 (en) * | 1982-11-15 | 1987-11-25 | Kabushiki Kaisha Toshiba | Radiation-controllable thyristor |
| ATE32483T1 (en) * | 1984-07-12 | 1988-02-15 | Siemens Ag | SEMICONDUCTOR CIRCUIT BREAKER WITH THYRISTOR. |
| FR2727571A1 (en) * | 1994-11-25 | 1996-05-31 | Sgs Thomson Microelectronics | THYRISTOR WITH SENSITIVITY IN CONTROLLED RETURN |
-
1978
- 1978-05-24 GB GB22195/78A patent/GB1566540A/en not_active Expired
- 1978-08-31 JP JP10697578A patent/JPS5480092A/en active Pending
- 1978-09-20 IT IT7869170A patent/IT7869170A0/en unknown
- 1978-10-26 DE DE19782846697 patent/DE2846697A1/en not_active Withdrawn
- 1978-12-14 FR FR7835264A patent/FR2412169A1/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0118309A2 (en) * | 1983-03-03 | 1984-09-12 | Texas Instruments Incorporated | Semi conductor device and starter circuit for a fluorescent tube lamp, provided with such a semi conductor device |
| US4629944A (en) * | 1983-03-03 | 1986-12-16 | Texas Instruments Incorporated | Starter circuit for a fluorescent tube lamp |
| EP0118309B1 (en) * | 1983-03-03 | 1990-05-23 | Texas Instruments Incorporated | Semi conductor device and starter circuit for a fluorescent tube lamp, provided with such a semi conductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2412169B3 (en) | 1981-10-09 |
| JPS5480092A (en) | 1979-06-26 |
| DE2846697A1 (en) | 1979-06-21 |
| FR2412169A1 (en) | 1979-07-13 |
| IT7869170A0 (en) | 1978-09-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |