GB1561953A

GB1561953A - Photodiodes

Info

Publication number: GB1561953A
Application number: GB3288177A
Authority: GB
Original assignee: Western Electric Co Inc
Current assignee: AT&T Corp
Priority date: 1976-08-06
Filing date: 1977-08-05
Publication date: 1980-03-05
Also published as: DE2734726A1; FR2360998B1; JPS5341193A; JPS6155791B2; DE2734726C2; CA1078948A; FR2360998A1

Description

(54) IMPROVEMENTS IN OR RELATING TO PHOTODIODES (71) We, WESTERN ELECTRIC COMPANY, INCORPORATED of 222 (formerly of 195) Broadway, New York City, New York State, United States of America, a Corporation organised and existing under the laws of the State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The invention relates to photodiodes.

The advent of the laser and its promise as a carrier source for optical communications has stimulated widespread interest in the development of photodetectors with high sensitivity to weak signals and fast response to light intensity modulations. An optical receiver, which usually includes a photodetector and an amplifier at its output, should satisfy certain general performance criteria according to H. Melchior, J. of Luminescence, Vol. 7, pp. 39W414 (1973): that is, (1) large response (quantum efficiency) at the wavelength of the incident optical signal; (2) sufficient electrical bandwidth (i.e., speed of response) to accommodate the information bandwidth; and (3) minimum excess noise introduced by the detection and amplification process.

One common type of photodetector is the photodiode which contains as an essential element a depleted semiconductor region with a high electric field that serves to separate electron-hole pairs photoexcited through band-to-band excitation. High speed photodiodes are usually connected to a relatively low impedance so as to allow the photoexcited carriers to induce a photocurrent in the load circuit while they are moving through the high field region.

Photodiodes for detecting visible and near infrared radiation are commonly operated at relatively large reverse bias voltage in order to reduce carrier drift time and lower the diode capacitance without introducing excessively large dark currents (Melchior supra at 397). In a reversed biased p-i-n photodiode, for example, with radiation incident on the p-layer the radiation which is not reflected at the surface penetrates some distance into the photodiode material before it is absorbed and generates photocarriers. Electrons and holes generated within the high field region of the junction (i-layer), and minority carriers which diffuse from the p- and n-layers to the junction before recombination, are collected across the high field region and contribute to the photocurrent.

The actual quantum efficiency and speed of response of photodiodes depends strongly on the wavelength of operation and the diode material and design. Silicon photodiodes, for instance, are preferably used in the near ultraviolet and in the infrared up to about l,um. But, because of its strongly varying light penetration depth, silicon photodiodes have to be optimized for each wavelength of interest (Melchior supra at 400). The speed of response is reduced at the longer wavelengths as the width of the high field region increases.

Dark currents in photodiodes limit the sensitivity to weak light signals and can originate either from the bulk or from the surface. Surface leakage currents, which are a problem especially in high resistivity silicon photodiodes, can be reduced by special surface treatments and various guard ring structures. On the other hand, bulk leakage currents in silicon photodiodes are mainly due to carrier generation within the space charge layer. For carefully processed silicon diodes dark currents as low as 10-610-8 A/mm3 of depleted volume have been attained (Melchior supra at 405).

One particularly useful type of photodiode is the avalanche photodiode (APD) which combines the detection of optical signals with internal amplification of the photocurrent. Internal current gain takes place in an APD when carriers gain sufficient energy by moving through a high field region of a highly reverse biased junction to release new electron-hole pairs via the mechanism of impact ionization. The current gain of an APD fluctuates due to the statistical nature of the carrier multiplication process. Even for spatially uniform avalanche regions the statistical gain variations give rise to noise in excess of multiplied shot noise and is usually characterised in terms of an excess noise factor given by:

where < iM2 > is the mean square noise current at the output of the APD divided by the mean square noise < iph2 > of the primary photocurrent multiplied by the square of the average gain M. In a silicon APD the ionization rate a of electrons is much larger than the ionization rate A for holes (e.g., p.02 to .2) and, as a consequence, F(M) increases much more rapidly for hole injection than for electron injection (Melchior supra at 409). This consideration suggests that a silicon n±p-7r-p+ APD be back illuminated (i.e., light made incident on the p±layer remote from the junction so that electrons are injected into the multiplication region) rather than front illuminated (i.e., light made incident on an n±layer near the junction so that holes are also injected into the multiplication region).

H. W. Ruegg illustrates the application of this principle in the design of an n±p-ap+ silicon APD described in IEEE Transactions on Electron Devices, Vol. ED-14, No. 5, pp.

239-251(1967). In this type of APD, which is particularly useful for high speed detection at GaAs laser wavelengths, carrier multiplication is constrained to the narrow n±p region and the wider region acts mainly as a collector for photoexcited electrons generated by light made incident on the p+4ayer. Ruegg (at 247, column 1) points at that "the optimized device requires the illuminated surface (the p+layer) to be opposite to the p-n junction in order to assure pure electron injection into the multiplication region". Consequently, it is required that the "total device thickness in this case must be of the order of the penetration depth of the light to be detected" (2O30 m for GaAs laser wavelengths). Ruegg goes on to add that "(s)ince wafers of this thickness cannot be handled, the only obvious solution was to etch local cavities (at the sites of devices) into a considerably thicker silicon wafer".

Unfortunately, the need to etch uniformly thick cavities, or equivalently to thin the substrate by lapping, increases substantially the cost of manufacturing this type of APD.

Cost increases also result because the thinned wafers are difficult to handle, are easily broken, tend to warp making mask alignment difficult, and present difficulty in packaging.

One alternative, therefore, is to form the structure on a thick p+ region and to use front-illumination through the n±layer so that the wafer does not have to be thinned.

But, as mentioned previously, mixed hole and electron injection occurs with an attendant increase in noise. In prior art front-illuminated n±p-7r-p+ silicon APDs (e.g., U.S. Patent 3,886,579 granted to Ohuchi et al on May 27, 1975) the structures have not been optimized to reduce excess noise, to produce low leakage currents and to be reliable in the long term. It is questionable, therefore, whether such devices are useful in an optical communication system in which receiver sensitivity is typically -55 dBm (e.g., at a .825,am wavelength and a 44.7 megabit/sec data rate). Naturally, then, it would be advantageous to reduce the noise penalty and dark currents in a reliable APD without employing unduly complex processing so that the generally lower cost and case of handling advantages of a front-illuminated APD can be exploited.

According to the present invention there is provided a silicon photodiode comprising: a high-resistivity, 'type silicon epitaxial layer formed on a high-conductivity p±type silicon substrate; an annular. p-type channel-stop region diffused into the n-type layer; an n±type layer, sufficiently thin to be transparent to light at the wavelength to which the photodiode is sensitive, formed in the 'r-type layer and enclosed by and separate from the channel-stop region; a coating on the n±type layer effective as an anti-reflection coating for light at the said wavelength; electrical contacts to the substrate, the channel-stop region and the n±type layer.

and means adapted to reduce the magnitude of electric fields developed in use at the annular portion of the surface of the n-type layer remote from the substrate between the n±type layer and the channelstop region.

Some photodiodes and fabrication methods embodying the invention will now be described by way of example with reference to the accompanying drawings, of which: Fig. I is an isometric part sectional view of an n±p-or-p+ silicon APD fabricated in accordance with the invention; Fig. 2 is a graph of the electric field and multiplication factor profile calculated for the APD shown in Fig. 1; and Fig. 3 is a cross-sectional view of an n±7r-p+ silicon photodiode fabricated in accordance with the invention.

With reference now to the drawing, Fig. 1 depicts a silicon avalanche photodiode (APD) fabricated in accordance with one embodiment of the invention. The structure of the APD will be first described, then its operation and fabrication.

The APD shown in cross section in Fig. 1, comprises a p±silicon substrate 10 on which is epitaxially grown a high resistivity it-type silicon layer 12. A p-layer 14 is formed in the top major surface of layer 12 and a thin n±layer 16 is formed in p-layer 14. This portion of the structure defines an elementary n±p-7r-p+ APD in which the player is the multiplication region. In a practical device, however, the configuration is adapted to meet the requirements of the system in which the APD is to function. In particular, an n-type guard ring 18 is formed in it-layer 12 so as to surround p-layer 14 and n±layer 16. The n±layer 16 extends laterally beyond the p-layer 14 so as to overlap the guard ring which prevents edge break-down of the n±p junction under normal operating conditions. The n±layer also serves as a contact layer for an annular metal contact and field plate 20 (e.g., PtSi- Ti-Pt-Au or Al) to which the positive terminal of a bias voltage source (not shown) is connected.

In addition, a p-type channel stop 22 is formed in 7c-layer 12. The channel stop which surrounds, but is in spaced relation to, the guard ring 18, serves to prevent inversion layers at the surface of high resistivity layer 12. An annular metal contact and field plate 24 (e.g., PtSi-Ti- Pt-Au or Al) is made to the p-type channel stop 22 and thereby to the p±substrate 10.

Contact to the substrate 10 is also made via a metal layer 26 (e.g., Ti-Au) formed on its bottom surface. Another metal layer 30 (e.g., Au) is formed on a ceramic mounting block 32. A conductive epoxy layer 28 or other suitable means (e.g., a solder preform) is used to bond the APD block 32. The negative terminal of the bias voltage source is connected to metal layer 30 and optionally to channel stop field plate 24.

In order to reduce the accumulation of ions in or on the surface of dielectric layer 35 above the surface portions 34 of the p-7r metallurgical junction, the channel stop field plate 24 overlaps the junction portion 34, thereby reducing both noise and leakage current and improving reliability. For the same reason the guard ring field plate 20 overlaps the surface portion 36 of the n-it metallurgical junction.

In order to reduce the reflection of radiation 38 to be detected, the n±layer 16 is covered with an anti-reflection coating comprising a thin layer 40 of SiO2 and a quarter wavelength thick layer 42 of Si3N4.

These layers also serve to passivate the surface. Note than SiO2 and Si3N4 layers are also formed between the guard ring and channel stop, but the SiO2 layer there is thicker because some SiO2 remained from prior processing steps to be subsequently described.

In operation, a reverse bias sufficiently high (typically several hundred volts) to fully deplete layer 12 and p-layer 14 (laterally to lines 13 and vertically to the substrate 10) is applied across the contacts 20 and 30, and radiation 38 is made incident on the active area of the device, a circular zone 44 in the centre of the guard ring. The radiation generates photoexcited carriers primarily in the layer. These carriers are multiplied in the high field p-layer 14.

Electrons are collected in the n±layer 16 and holes are collected in the p±substrate 10. The resulting photocurrent flows in a load (not shown) connected across contacts 20 and 30. Because this device is frontilluminated mixed carrier injection occurs.

That is, radiation incident on n±layer 16 generates holes which are injected into the p-layer where they are multiplied, and the same radiation which penetrates to the player and layer generates electrons which are injected into the multiplication region.

In order to approach the low noise performance of pure electron injection (i.e., of a back-illuminated APD), the n±layer is made very thin and the electric field profile is shaped as shown in Fig. 2. That is, the field is nearly zero in the n±layer, rises very steeply near the n±p junction and has a substantially triangular shape in the p-layer.

The triangular profile produces multiplication with extremely low noise for electrons entering near the p-it interface (x2), as well as relatively low noise (compared to a rectangular field profile) for mixed hole and electron injection in the player resulting from front-illumination.

Note that the thinness of the n±layer also serves to reduce optical absorption therein and thereby to support high quantum efficiency. Otherwise a substantial number of minority carriers generated in the n+layer would recombine before reaching the high field region of the p-layer.

Although the graph of Fig. 2 represents only theoretical calculations, the essential characteristics have been realized in an n+ - p-lr-p' silicon APD fabricated, in accordance with an illustrative embodiment of the invention, as follows: (1) on a low dislocation density, p-type silicon substrate 10 doped with boron to about 5x1017-l.2x1018 cm-3, a high resistivity ( > 300Q-cm) epitaxial silicon layer 12 was grown about 30 to 60 Lm thick.

Preferably the epitaxial layer is more than 35 ,um thick in order to collect at least 95% of the carriers photoexcited by radiation at about 0.825 ,um. The epitaxial layers were grown in a reactor using -dichlorosilane (SiH2CI2) as the silicon source. The growth rate was 3.5 ym/min at a deposition temperature of about 1100--1200 degrees C. Diborane was used as a dopant source and prior to growth a one micron, in situ, HCI etch was performed at 1160 degrees C.

Because these high resistivity layers are grown on heavily doped substrates, care should be exercised to control autodoping from the substrate; (2) a layer of SiO2 was then formed on the epitaxial layer by oxidation of the silicon in a moist O2 ambient at 1050 degrees C for 2 hrs. Using standard photolithographic techniques an opening was made in the oxide to allow formation of guard ring 18; (3) phosphorus was then diffused into the opening by predepositing a phosphorus glass layer therein from a POCI3 source at 900 950 degrees C for 15-30 min. The phosphorus glass layer was removed, and the phosphorus was diffused into the underlying portions of epitaxial layer 12 by heating at 1100--1200 degrees C for 3060 min. (not critical) in an atmosphere of N2+0.1% 03. In order to reduce the number of crystalline defects created in the layers, the intermediate device structures (wafers) were placed in a furnace idling at a temperature of about 900 degrees C, and then the temperature was gradually increased (e.g., at W8 degrees Clmin) to 1100 1200 degrees C. For the same reason the temperature was ramped down to 900 degrees C after diffusion took place for the prescribed time. This diffusion step formed the n-type guard ring 18; (4) oxidation and masking step (2) was repeated to form an opening for the channel stop; (5) boron was then diffused into the opening by predepositing a boron glass layer therein from a BN source at 950975 degrees C for 1-2 hrs. The boron glass layer was removed and the boron was then diffused into the underlying portions of epitaxial layer 12 by heating at 1100-1200 degrees C for 3060 min. (not critical) in an atmosphere of essentially 100ass 02. For the same reason described in step (3) the furnace temperature was ramped between 900 degrees C and the drive-in temperature. This diffusion step formed the p-type channel stop 22; (6) oxidation and masking step (2) was again repeated to form an opening closed by and partially overlapping guard ring 18.

Boron ions were then implanted into the top surface of epitaxial layer 12. The energy and dose were 30150 KeV and " 6xl012 cm-2, respectively. Controlling the dose to within +5 for a given device design was particularly important. If the dose were too high, for example, the entire heating cycle (i.e., time and temperature of all subsequent steps involving heating) would have to be modified to longer times and/or higher temperatures, if possible. Conversely, if the initial dose were too low, the device would have a very small gain and high breakdown voltage; (7) after implantation, the boron ions were driven into the epitaxial layer by heating at about 11501250degrees C for 2-8 hrs. in an atmosphere of 0.1-1.0% O2 in nitrogen or argon. At 1200 degrees C for 4 hrs., for example, this step formed a p-layer 14 (the multiplication region) about 6 ym thick. However, this layer is 2-12 m thick for the processing ranges given although 57 pm us preferred for an APD having M=100 at 300 V. As in steps. (3) and (5) the furnace temperature was ramped between 900 degrees C and the drive-in temperature: (8) the entire wafer was then reoxidized at about 1050 degrees C for I hr.

The oxide was stripped only from the backside of the substrate 10; (9) using a POCI3 source, a phosphorus glass layer was then formed on the backside of the substrate 10. Other phosphorus sources, such as PBr3, are also suitable for this predeposition as well as for previous phosphorus predepositions. Phosphorus was diffused into the backside by heating at about 1000--1100 degrees C for 30--60 min.

in an atmosphere of substantially N2+0. 1% 02. Strain and/or misfit dislocations caused by the phosphorus atoms was effective in gettering impurities (especially fastdiffusing metallic impurities) and other defect nucleation sites. This step played a significant role in reducing dark currents in our APDs. As in steps (3) and (5) the furnace temperature was ramped between 900 degrees C and the diffusion temperature; (10) next, the phosphorus glass layer on the backside was removed and the wafer was re-oxidized at about 900 degrees C for 10 min. Using standard photolithographic techniques the oxide was masked and an opening was formed for the n+4ayer 16; (11) the n±layer 16 was formed by a phosphorus predeposition (i.e., deposition of a phosphorus glass layer from POCI3) followed by heating at about 920930 degrees C for 2030 min. in an atmosphere of substantially N2+ 1.0% O2. The glass layer was then removed. This step resulted in an n±layer about 0.3 urn thick. Subsequent heating steps increased the thickness to about 0.4 urn, the prefefred value, although a range of 0.1-1.0 um is suitable.

Alternatively, the n±layer can be formed from an arsenic predeposition of by arsenic ion implantation and drive-in. This step compensates the previously implanted boron and thereby determines the depth of the p-n+ junction. The time and temperature are critical in that deeper diffusions reduce the total charge in the p-layer and increase the breakdown voltage. In addition, this step in conjunction with the implant-drive steps (6) and (7) establishes the desired triangular electric field profile.

(12) at this intermediate stage the devices were tested to measure their current-voltage characteristics and leakage currents. Those diodes which met specification were subjected to subsequent processing. Those which did not, but which were overdoped in the critical p-layer 14, were heated in an effort to bring them to specification. Testing and reheating can be repeated until the device meets specification.

(13) those devices which met specification were coated with a thin layer 40 (about 10W200 angstroms) of SiO2 by a wellknown dry oxidation process; (14) then, the SiO2 layer was subjected to an anneal at about 850950 degrees C for 1030 min. in an atmosphere of about 15% HCI in N2. This step is important for reducing leakage current because it effectively getters or traps mobile ions such as Na ions in the oxide; (15) after gettering, a quarter wavelength layer 42 of Si3N4 (about 1000 Angstroms for A as measured in the material) was deposited on SiO2 layer 40 using a chemical vapour deposition process; layers 40 and 42 served to passivate the device from external contamination, and in the active region enclosed by guard ring 18, served as an anti-reflection coating; (16) contact windows were then opened in layers 40 and 42 for field plates 20 and 24; (17) the substrate (initially about 500 nm thick) was then etched or lapped on the backside to remove about 75 urn of material and thereby remove the phosphorus layer created by prior diffusion steps (e.g., gettering step (9)). In order to reduce contact resistance, boron ions were implanted in the backside at about 3e50 KeV to a dose of 2--4x 10'5 cam~2. The boron ions were then activated by heating in an N2 atmosphere at about 750--800 degrees C for 30--60 min.

(18) using suitable masking, metal was deposited to form the guard ring and channel stop field plates 20 and 24 from a PtSi-Ti-Pt-Au metallization. In order to avoid ion accumulation at the surface portions 34 and 36 of the it-p and its junctions, these field plates were made to overlap the respective metallurgical junctions. Because the oxide-nitride layers are thin over these regions and because high reverse bias voltages are applied, impulse noise due to surface microplasmas and/or leakage current would result without this overlapping configuration; (19) the device was then annealed at 300-320 degrees C in an atmosphere of N2+8-l5% H2 for about 16-24 hrs. in order to reduce surface state density and anneal the Au in the contact layers to improve bondability; (20) finally, Ti-Au alloy layer 26 was deposited on substrate 10. Using a conductive epoxy layer 28 the APD was bonded to Au layer 30 on ceramic mounting block 32.

Using the foregoing procedure, n±p-7r-p+ silicon APDs were fabricated in which, for example: the p±substrate 10 was 500 urn thick; the epitaxial 7t-layer 12 was 50 urn thick and had a resistivity of greater than 3009-cm; the ion-implanted p-layer 14 was about 6 pm thick and had a substantially triangular electric field profile; and the n+layer was about 0.4 urn thick. The diameter of the active zone was about 100 urn, the inside and outside diameters of the guard ring were 180 urn and 290 urn, respectively, and those of the channel stop were 350 urn and 460 urn, respectively.

Radiation from a double heterostructure GaAs-A1GaAs junction laser operating c.w.

at room temperature (=0.825 ym) was coupled through an optical fibre to the active region of the APD.

This APD operated between full depletion of p-layer 14 and it-layer 12 at 100V and breakdown at 375V. Over this voltage range current gains of five to several hundred were attained. At a gain of 100 the excess noise factor was only 4 to 6 over the shot noise limit. The total dark current was only about 10-" A and that portion which is eventually multiplied was about 10-13 A.

The quantum efficiency exceeded 95 v and the response speed was about 1 ns. When incorporated into an optical receiver, sensitivity at 0.825 turn and 44.7 megabit/sec was -55 dBm. From a reliability standpoint, the mean time to failure was approximately 103--104 hours based on bias stress aging tests at 200 degrees C.

The specific values for the more important parameters used to fabricate the foregoing APD were as follows: in step (3), phosphorus was diffused at 1200 degrees C for 1 hr.; in step (5), boron was diffused at 1150 degrees C for I hr.; in step (6), boron ions were implanted at an energy of 150 KeV to a dose of 5.5x10'2 cm-2~5 ; in step (7), the boron ions were driven in at 1200 degrees C for 4 hrs; in step (9). the phosphorus glass layer on the backside was heated at 1100 degrees C for I hr.; in step (it), phosphorus glass layer on the p-layer was heated at 925 degrees C for 30 min.; and in step (14, the SiO2 layer was annealed at 900 degrees C for 10 min. in N2+5 , HCI.

It has been found that the foregoing APD fabrication process, excluding the ion implantation and drive-in steps, is also an effective way to make n±7r-p silicon photodiodes having high quantum efficiency ( > 90 SO at GaAs-A1GaAs wavelengths) short response times (e.g., 1 ns at 100V or 4 ns at 5V), low dark current (e.g., 10-" A), low capacitance (e.g., 1.5 pf at 10V) and good reliability (e.g., means time to failure 104 hours). This kind of detector is particularly useful in systems where gain in the photodiode is not essential-for example, low data rate, short distance, LED optical systems.

Reference will be made to Fig. 3 where components corresponding to those of Fig.

1 have been given identical numerals to facilitate comparison. Thus, the process illustratively comprises the steps of: (1) epitaxially growing a high resistivity ( > 300Q- cm) rr-type silicon layer 12 about 30--60 ym thick on a high conductivity p±type silicon substrate 10; (2) forming an n-type guard ring 18 in the layer 12 by a predeposition and diffusion of phosphorus; (3) forming a p-type channel stop 22 around the guard ring 18 by a predeposition and diffusion of boron; (4) introducing phosphorus into the backside of p±substrate 10 from a POCI3 or other suitable source by heating at about 100Cr--110 the APD gain region; that is, because the gain-voltage characteristic of an APD is pressure sensitive, placing metallization over the guard rings, rather than on the n+layer, means that operations such as bonding leads, and test probing will not affect the APD characteristic.

WHAT WE CLAIM IS: 1. A silicon photodiode comprising: a high-resistivity it-type silicon epitaxial layer formed on a high-conductivity p±type silicon substrate; an annular p-type channel-stop region diffused into the type layer; an n±type layer, sufficiently thin to be transparent to light at the wavelength to which the photodiode is sensitive, formed in the type layer and enclosed by and separate from the channel-stop region; a coating on the n±type layer effective as an anti-reflection coating for light at the said wavelength; electrical contact to the substrate, the channel-stop region and the n±type layer; and means adapted to reduce the magnitude of electric fields developed in use at the annular portion of the surface of the it-type layer remote from the substrate between the n±type layer and the channel stop region.

2. A photodiode as claimed in claim 1 including a passivation coating on the said annular portion of the surface of the it-type layer.

3. A photodiode as claimed in claim 1 or claim 2 wherein the electric field reducing means includes a diffused n-type guard ring laterally enclosing and in contact with the n±type layer and separate from the channelstop region.

4. A photodiode as claimed in claim 3 wherein the n±type layer at its periphery overlaps the guard ring.

5. A photodiode as claimed in claim 3 or claim 4 wherein the electrical contact to the n±type layer makes contact to the n+ layer via the guard ring.

6. A photodiode as claimed in claim 4 wherein the electrical contact to the n±type layer makes direct electrical contact with only that portion of the n±type layer which overlaps the guard ring.

7. A photodiode as claimed in any of the preceding claims wherein the electric field reducing means includes a first field-plate electrode conductively connected to the electrical contact to the channel-stop region and overlying and insulated from the outer edge of the said annular portion of the surface of the type layer and a second field-plate electrode conductively connected to the electrical contact to the n±type layer and overlying and electrically insulated from the inner edge of the said annular portion of the surface of the it-type region.

8. A photodiode as claimed in any of the preceding claims including a diffused p-type layer underlying and forming a junction with the n*-type layer so that the photodiode is a n±p-7r-p+ avalanche photodiode.

9. A photodiode as claimed in claim 8 wherein in use the electric field in the p-type layer varies substantially linearly with depth from a first value close to the junction between the p-type layer and the n±type layer to a lower value at the opposite face of the p-type layer.

10. A photodiode as claimed in claim 9 wherein in use the electric field in the n+type layer is substantially zero except in the near neighbourhood of the junction with the p-type layer.

11. A photodiode as claimed in any of the preceding claims wherein the 7c-type layer has a resistivity of at least 300 Ohm-cm and a thickness in the range 30 to 60 micrometres.

12. A photodiode as claimed in -claim 11 wherein the thickness of the it-type layer is greater than 35 micrometres.

13. A photodiode as claimed in any of the preceding claims wherein the thickness of the n±type layer is in the range 0.1 to 1.0 micrometres.

14. A photodiode substantially as herein described with reference to Figs. 1 and 2 or to Fig. 3 of the accompanying drawings.

15. A method of making a photodiode as claimed in any of claims 8 to 10 wherein the p-type layer is formed by implantation of boron ions followed by a heat treatment to cause the implanted ions to diffuse into the epitaxial layer.

16. A method of making a photodiode as claimed in any of claims 1 to 14 or a method as claimed in claim 15 wherein a phosphorus-diffusion gettering process is performed on the backside of the substrate.

17. A method of making a photodiode as claimed in any of claims 1 to 14 or a method as claimed in claim 15 or claim 16 wherein at each dopant-diffusion step the temperature of the silicon is gradually raised to the diffusion temperature from a lower temperature and after diffusion the temperature is gradually lowered again.

18. A method as claimed in claim 17 wherein the lower temperature is about 900 degrees C, and the gradual raising and lowering of the temperature is at a rate in the range 4 to 8 degrees C/minute.

19. A method of making a photodiode as claimed in claim 2 or any of claims 3 to 14 with claim 2 or a method as claimed in any of claims 15 to 18 with claim 2 wherein the passivation coating is made by forming a layer of silicon dioxide on the surface of the

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. the APD gain region; that is, because the gain-voltage characteristic of an APD is pressure sensitive, placing metallization over the guard rings, rather than on the n+layer, means that operations such as bonding leads, and test probing will not affect the APD characteristic. WHAT WE CLAIM IS:

1. A silicon photodiode comprising: a high-resistivity it-type silicon epitaxial layer formed on a high-conductivity p±type silicon substrate; an annular p-type channel-stop region diffused into the type layer; an n±type layer, sufficiently thin to be transparent to light at the wavelength to which the photodiode is sensitive, formed in the type layer and enclosed by and separate from the channel-stop region; a coating on the n±type layer effective as an anti-reflection coating for light at the said wavelength; electrical contact to the substrate, the channel-stop region and the n±type layer; and means adapted to reduce the magnitude of electric fields developed in use at the annular portion of the surface of the it-type layer remote from the substrate between the n±type layer and the channel stop region.

silicon and annealing the silicon dioxide layer in an atmosphere containing HCI.

20. A method of making a photodiode as claimed in any of claims 1 to 14 or a method as claimed in any of claims 15 to 19 including an annealing process carried out in a reducing atmosphere subsequently to the formation of the contacts to the channel-stop region and the n+ layer.

21. A method, substantially as herein described with reference to Fig. 1 or Fig. 3 of the accompanying drawings, of making a silicon photodiode.