GB1533576A - Computer systems - Google Patents

Computer systems

Info

Publication number
GB1533576A
GB1533576A GB3913075A GB3913075A GB1533576A GB 1533576 A GB1533576 A GB 1533576A GB 3913075 A GB3913075 A GB 3913075A GB 3913075 A GB3913075 A GB 3913075A GB 1533576 A GB1533576 A GB 1533576A
Authority
GB
United Kingdom
Prior art keywords
slave
master
highway
mother board
slaves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3913075A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Computer Technology Ltd
Original Assignee
Computer Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Computer Technology Ltd filed Critical Computer Technology Ltd
Priority to GB3913075A priority Critical patent/GB1533576A/en
Priority to JP51113784A priority patent/JPS5240039A/en
Publication of GB1533576A publication Critical patent/GB1533576A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)

Abstract

1533576 Data transmission COMPUTER TECHNOLOGY Ltd 22 Sept 1976 [24 Sept 1975] 39130/75 Heading H4P Transfer of data from m master logic devices to s slave logic devices takes place through a highway constituted by s groups of m conducting paths. As described in relation to a computer system, the highway is provided by a printed circuit board 1 (the mother board), which is associated with daugher boards 2 carrying masters 3 and slaves 4. Each master can communicate with each slave, and the priority of each master is uniquely determined by the mother board as is the slave port address of each slave. Further, the mother board, through its highway, always carries information as to the status of all the slaves to all the masters and an addressed slave can lock-on to an instructing master whilst appearing busy to all others.
GB3913075A 1975-09-24 1975-09-24 Computer systems Expired GB1533576A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB3913075A GB1533576A (en) 1975-09-24 1975-09-24 Computer systems
JP51113784A JPS5240039A (en) 1975-09-24 1976-09-24 Information transfer device and computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3913075A GB1533576A (en) 1975-09-24 1975-09-24 Computer systems

Publications (1)

Publication Number Publication Date
GB1533576A true GB1533576A (en) 1978-11-29

Family

ID=10407802

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3913075A Expired GB1533576A (en) 1975-09-24 1975-09-24 Computer systems

Country Status (2)

Country Link
JP (1) JPS5240039A (en)
GB (1) GB1533576A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1980001628A1 (en) * 1979-01-31 1980-08-07 Techn Marketing Inc A multi-layered back plane for a computer system
EP0015054A1 (en) * 1979-01-17 1980-09-03 Fanuc Ltd. Bus connection systems
EP1425593A1 (en) * 2001-09-14 2004-06-09 Rambus Inc. Built-in self-testing of multilevel signal interfaces

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0015054A1 (en) * 1979-01-17 1980-09-03 Fanuc Ltd. Bus connection systems
WO1980001628A1 (en) * 1979-01-31 1980-08-07 Techn Marketing Inc A multi-layered back plane for a computer system
EP1425593A1 (en) * 2001-09-14 2004-06-09 Rambus Inc. Built-in self-testing of multilevel signal interfaces
EP1425593A4 (en) * 2001-09-14 2005-01-12 Rambus Inc Built-in self-testing of multilevel signal interfaces

Also Published As

Publication number Publication date
JPS5240039A (en) 1977-03-28

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee