GB1520627A - Microprogrammed controller with fault detection in memory addressing - Google Patents

Abstract

1520627 Microprogrammed prosessors HONEYWELL INFORMATION SYSTEMS ITALIA SpA 30 March 1977 [30 March 1976] 13378/77 Heading G4A In a microprogram controlled data processor, the address of an accessed microinstruction in read-only store 8 is incremented by 1 and ŒK in units 114, 115 (Fig. 3) respectively, one of these addresses being selected to fetch the next microinstruction in dependence on whether a condition specified by the currently accessed microinstruction is met or not, the parity of the selected address being compared with a parity bit stored at one of two associated locations of the accessed microinstruction. The address of the next microinstruction in a routine is derived by decoding predetermined bits of the current microinstruction to select, if the condition is not satisfied or if the microinstruction is a simple operating microinstruction (1) the output of incremeter 114 (if bit 0 = 0, bit 24 = 0, bit 25 = 0), (2) the output of a first register RR1 (bit 0 = 0, bit 24 = 1), (the output of the incremeter 114 being stored in this register as a return address when bit 0 = 1, bit 1 = 0 and bit 2 = 1) or (3) the output of a second register RR2 (bit 0 = 0, bit 25 = 1), (the output of the incrementer 114 being stored in this register when bit 0 = 1, bit 1 = 0 and bit 3 = 1). If the condition is satisfied or if the microinstruction is an absolute unconditional jump microinstruction either the current address incremented by ŒK (K being given by bits 17- 21 of the accessed microinstruction) or an absolute address given by bits 10-21 of the current microinstruction is selected in dependance on whether bit 1 is 1 or 0 respectively. When a microinstruction is accessed, the parity bits for the two possible next addresses (+1, ŒK) are fed on lines 56, 67 (Fig. 4) to error detection circuitry. If the address incremented by 1 is saved in registers RR1 or RR2 the parity bit on line 56 is stored in bistable 50 or 51 respectively. When the next address on line 38 is used to access the microstore 8 its parity is compared with, if the condition is satisfied, the parity on line 67 or, of the condition is not satisfied, with the bit on line 56 or the contents of bistable 50 or 51, an error signal 73 being generated if the address is incorrect.