GB1505580A - Data processing apparatus - Google Patents

Data processing apparatus

Info

Publication number
GB1505580A
GB1505580A GB49305/75A GB4930575A GB1505580A GB 1505580 A GB1505580 A GB 1505580A GB 49305/75 A GB49305/75 A GB 49305/75A GB 4930575 A GB4930575 A GB 4930575A GB 1505580 A GB1505580 A GB 1505580A
Authority
GB
United Kingdom
Prior art keywords
address
page
logical
data
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB49305/75A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of GB1505580A publication Critical patent/GB1505580A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

1505580 Address translation FUJITSU Ltd 1 Dec 1975 [30 Nov 1974] 49305/75 Heading G4A An address translation system for converting logical addresses representing the page and line of a program to a physical address representing the location of the addressed item in main memory comprises a first (page map) address converter 7 (Fig. 2) and a second (page table) address converter 8, the second converter only being used for pages which are shared between two or more programs. The system also includes an associative memory 6 in which the logical addresses of the most frequently used items are stored with their real page address, at comparison between the logical address of a desired item held in register 5 and a stored logical address the real page address being read out to register 12 where it is combined with the line number (from register 5) to derive the address to access the main memory. If it is not in the associative memory (or if the data is invalid, represented by a "0" bit in Section A) map pointer registers 14 are accessed, one being selected by section PN of the logical address to read out an address designation which is used in conjunction with the page number LPN 0 to address page maps 16 in the main store to read out the physical page address RPA, validity data A and control data X, Y. The data Y indicates whether the information is in the main store or whether transfer from an auxiliary memory is necessary. The data X when set to "1" indicates that the page is shared with another program and that the page table converter 8 must be accessed using the address read out from the page map 16 to index an address in a table pointer register 24 holding the address of the page table 26. The address RPA read from the table is combined with the line number of the logical address to derive the complete physical address. Consequently when the physical addresses of pages shared between several programs are changed only the table 26 has to be altered.
GB49305/75A 1974-11-30 1975-12-01 Data processing apparatus Expired GB1505580A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13806774A JPS5540950B2 (en) 1974-11-30 1974-11-30

Publications (1)

Publication Number Publication Date
GB1505580A true GB1505580A (en) 1978-03-30

Family

ID=15213189

Family Applications (1)

Application Number Title Priority Date Filing Date
GB49305/75A Expired GB1505580A (en) 1974-11-30 1975-12-01 Data processing apparatus

Country Status (6)

Country Link
US (1) US4037209A (en)
JP (1) JPS5540950B2 (en)
DE (1) DE2551740A1 (en)
ES (1) ES443078A1 (en)
FR (1) FR2293007A1 (en)
GB (1) GB1505580A (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5454536A (en) * 1977-10-08 1979-04-28 Fujitsu Ltd Data processor
US4277826A (en) * 1978-10-23 1981-07-07 Collins Robert W Synchronizing mechanism for page replacement control
JPS5792383A (en) * 1981-09-17 1982-06-08 Matsushita Electric Ind Co Ltd Fluorescent indication tube
US4511964A (en) * 1982-11-12 1985-04-16 Hewlett-Packard Company Dynamic physical memory mapping and management of independent programming environments
JPS60107156A (en) * 1983-11-16 1985-06-12 Hitachi Ltd Data processing system
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4868738A (en) * 1985-08-15 1989-09-19 Lanier Business Products, Inc. Operating system independent virtual memory computer system
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US7447069B1 (en) 1989-04-13 2008-11-04 Sandisk Corporation Flash EEprom system
US7190617B1 (en) * 1989-04-13 2007-03-13 Sandisk Corporation Flash EEprom system
EP0675502B1 (en) * 1989-04-13 2005-05-25 SanDisk Corporation Multiple sector erase flash EEPROM system
EP0522178B1 (en) * 1991-01-23 2000-06-14 Seiko Epson Corporation Data store and image processing system comprising said data store
JP2826028B2 (en) * 1993-01-28 1998-11-18 富士通株式会社 Distributed memory processor system
DE10163342A1 (en) * 2001-12-21 2003-07-10 Elektro Beckhoff Gmbh Unterneh Data transmission method, serial bus system and connection unit for a passive bus device
US7085897B2 (en) * 2003-05-12 2006-08-01 International Business Machines Corporation Memory management for a symmetric multiprocessor computer system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3412382A (en) * 1965-11-26 1968-11-19 Massachusetts Inst Technology Shared-access data processing system
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
US3902164A (en) * 1972-07-21 1975-08-26 Ibm Method and means for reducing the amount of address translation in a virtual memory data processing system

Also Published As

Publication number Publication date
JPS5162944A (en) 1976-05-31
FR2293007B1 (en) 1979-04-27
US4037209A (en) 1977-07-19
ES443078A1 (en) 1977-04-16
FR2293007A1 (en) 1976-06-25
DE2551740A1 (en) 1976-08-12
JPS5540950B2 (en) 1980-10-21

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19931201