GB1475471A - Floating point apparatus and techniques - Google Patents

Abstract

1475471 Floating point arithmetic unit DATA GENERAL CORP 13 Jan 1975 [21 Jan 1974] 1414/75 Heading G4A In a floating point processor, Fig. 1, the mantissas of first and second floating point operands A, B obtained in hexadecimal form from the memory bus of a central processing unit (not shown) are loaded into 56-bit registers 23, 24 respectively, the absolute value of the difference of their exponents being calculated by an exponent logic unit 26 whose output is fed to a hexadecimal sealer 27 to shift the appropriate mantissa the required number of hexadecimal digit positions so that the exponents become equalized. The hexadecimal sealer 27, as shown in detail in Fig. 2, comprises two groups of fourteen 4-bit registers A 1 -A 14 , B 1 -B 14 (and stages MQ 1 -MQ 14 of an intermediate register 22 holding the exponent and mantissa), the least significant bit positions of registers A, B and MQ being connected via multiplexers 28<SP>1</SP> to sealer 27 whose outputs are coupled to respective shift inputs of the registers A, B and MQ. The arrangement is such that a hexadecimal digit in any one of registers A, B and MQ can be transferred to any digit position of the same, or another, register in four clock pulses, the amount of left or right shift being determined by a scale code input to sealer 27. Normalization, i.e. the production of an oper- and in one of the A or B registers whose most significant digit is non-zero, may also be effected in a single step by use of a scale code value (representing the position of the first non- zero digit) produced by a mantissa logic unit 33. Floating point instructions are initially received from the memory bus by an instruction buffer 11 and thence pass to timing control and logic circuitry 13 if no floating point instruction is currently being processed. If no floating point error (division by zero, mantissa overflow &c.) is detected by a controller 39, a floating point operand is fetched from main memory by circuitry 13 and stored in register 22. The mantissa of the corresponding operand is then loaded into the A register and checked by a shift encoder 34 to see if it is all zeros; if it is the entire register is cleared since the operand is zero. Registers 23, 24 have their contents respectively left and right shifted by one bit position each time they are loaded from mantissa logic unit 33, to aid in multiplication and division operations. Either single or double precision operands may be processed.