GB1312791A - Arithmetic and logical units - Google Patents
Arithmetic and logical unitsInfo
- Publication number
- GB1312791A GB1312791A GB3591870A GB3591870A GB1312791A GB 1312791 A GB1312791 A GB 1312791A GB 3591870 A GB3591870 A GB 3591870A GB 3591870 A GB3591870 A GB 3591870A GB 1312791 A GB1312791 A GB 1312791A
- Authority
- GB
- United Kingdom
- Prior art keywords
- excl
- result
- parity
- bit
- operand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
- Logic Circuits (AREA)
Abstract
1312791 Arithmetic and logic unit INTERNATIONAL BUSINESS MACHINES CORP 24 July 1970 [31 July 1969] 35918/70 Heading G4A In an arithmetic and logical unit, the parity of the result of a logical operation performed on a pair of operands is predicted in response to the bit values of the operands and control signals indicative of the logical operation, and compared with the actual parity of the result. Fig. 3 shows the nth bit stage of a parallel ALU capable of binary addition, AND, OR and EXCL-OR operations. The stage receives signals at 70, 110 to select the operation, operand bits A n , B n carry outputs C n-1 , C n-2 , C n-3 from the three next lower order stages and A n-1 , VB n-1 , A n-2 , VB n-2 from the two next lower order stages, and produces a result bit R n , carry bit C n , parity bit PF n , and A n VB n . Circuit 18 produces the AND and OR of A n , B n , one being selected at 24 to form PF n . For addition, carry generatcr 20 and sum generator 22 are used as shown, their outputs being EXCL-ORed at 36 to feed R n . For OR, an AND gate 116 passes the output of OR 62 to R n . For AND, an AND gate 118 fcrms A n AND B n and passes it to R n . For EXCL-OR, the outputs of circuit 18 are passed to AND 104 in sum generator 22, using inverter 94, the upper input of OR 102 and the lower input of OR 106, the output of AND 104 being passed to R n . Checking logic forms the EXCL- OR of the parity of operand A and the inverse of the parity of operand B and EXCL-ORs the result with either the EXCL-OR of the PF bits (in the case of AND or OR) or the EXCL-OR of the carries C (in the case of add). The result is compared (EXCL-ORed) with the inverse of the EXCL-OR of the result bits R, a 1 indicating error. As modifications, the operand bits A n , B n could be applied directly to 20, 22 or 24, or not applied directly to 26<SP>1</SP> (the output of 18 being used instead).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19691938912 DE1938912C (en) | 1969-07-31 | Arithmetic and logical unit with error checking |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1312791A true GB1312791A (en) | 1973-04-04 |
Family
ID=5741461
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB3591870A Expired GB1312791A (en) | 1969-07-31 | 1970-07-24 | Arithmetic and logical units |
Country Status (6)
Country | Link |
---|---|
US (1) | US3649817A (en) |
JP (1) | JPS5213066B1 (en) |
CA (1) | CA931270A (en) |
CH (1) | CH510303A (en) |
FR (1) | FR2056229A5 (en) |
GB (1) | GB1312791A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2125591A (en) * | 1982-08-14 | 1984-03-07 | Int Computers Ltd | Checking sequential logic circuits |
US4556976A (en) * | 1982-08-14 | 1985-12-03 | International Computers Limited | Checking sequential logic circuits |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3911261A (en) * | 1974-09-09 | 1975-10-07 | Ibm | Parity prediction and checking network |
US4035626A (en) * | 1976-03-29 | 1977-07-12 | Sperry Rand Corporation | Parity predict network for M-level N'th power galois arithmetic gate |
US4084253A (en) * | 1977-01-03 | 1978-04-11 | Honeywell Information Systems Inc. | Current mode arithmetic logic circuit with parity prediction and checking |
US4084252A (en) * | 1977-01-03 | 1978-04-11 | Honeywell Information Systems Inc. | Current mode 5-bit arithmetic logic unit with parity |
GB1595479A (en) * | 1977-01-03 | 1981-08-12 | Honeywell Inf Systems | Digital logic circuitry |
JPS53160255U (en) * | 1977-05-24 | 1978-12-15 | ||
US4914579A (en) * | 1988-02-17 | 1990-04-03 | International Business Machines Corporation | Apparatus for branch prediction for computer instructions |
US4924424A (en) * | 1988-04-25 | 1990-05-08 | International Business Machines Corporation | Parity prediction for binary adders with selection |
GB2293469A (en) * | 1994-09-22 | 1996-03-27 | Secr Defence | Error detection in arithmetic circuit. |
US9037355B2 (en) * | 2007-11-05 | 2015-05-19 | Deere & Company | Control assembly for auxiliary hydraulics |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3111578A (en) * | 1959-12-31 | 1963-11-19 | Ibm | Utilizing predicted parity |
US3342983A (en) * | 1963-06-25 | 1967-09-19 | Ibm | Parity checking and parity generating means for binary adders |
GB1054203A (en) * | 1963-12-04 | |||
US3555255A (en) * | 1968-08-09 | 1971-01-12 | Bell Telephone Labor Inc | Error detection arrangement for data processing register |
-
1970
- 1970-06-02 FR FR7020086A patent/FR2056229A5/fr not_active Expired
- 1970-07-16 CA CA088340A patent/CA931270A/en not_active Expired
- 1970-07-24 CH CH1122870A patent/CH510303A/en not_active IP Right Cessation
- 1970-07-24 GB GB3591870A patent/GB1312791A/en not_active Expired
- 1970-07-28 JP JP45065528A patent/JPS5213066B1/ja active Pending
- 1970-07-29 US US59220A patent/US3649817A/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2125591A (en) * | 1982-08-14 | 1984-03-07 | Int Computers Ltd | Checking sequential logic circuits |
US4556976A (en) * | 1982-08-14 | 1985-12-03 | International Computers Limited | Checking sequential logic circuits |
Also Published As
Publication number | Publication date |
---|---|
DE1938912A1 (en) | 1971-02-11 |
CH510303A (en) | 1971-07-15 |
US3649817A (en) | 1972-03-14 |
FR2056229A5 (en) | 1971-05-14 |
JPS5213066B1 (en) | 1977-04-12 |
DE1938912B2 (en) | 1972-10-19 |
CA931270A (en) | 1973-07-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PCNP | Patent ceased through non-payment of renewal fee |