GB1404961A - Measurement of timing jitter on pcm systems - Google Patents

Abstract

1404961 Phase detectors; transistor circuits STANDARD TELEPHONES & CABLES Ltd 7 Dec 1972 56487/72 Headings H3A and H3T A PCM regenerator comprises: means for producing a clock signal from the output pulses; switching means for producing from the clock signal a squarewave signal of the same frequency; a sawtooth generator including a capacitor charged at a constant rate and discharged in response to the squarewave; and a sample and hold circuit in which the sawtooth is sampled by the data output pulses. Limiter and sawtooth generator, Fig. 3.- A sinewave clock signal, produced by means not shown, is clipped in limiter T1, T2 to produce a square wave, which is amplified by T3, T4 and differentiated to produce short duration pulses from T5. These pulses are fed to transistor T6 to turn it on and short capacitor C1. In between pulses, C1 charges linearly from constant current source T7 to produce a sawtooth output which is applied to input 41 of the gate and store circuit, Fig. 4. Switch S may be included to switch in a different value capacitor. Gate and store circuit, Fig. 4.-The PCM signal whose timing is to be detected is in the form of bipolar pulses, which are applied to input 42. The pulses are rectified, amplified by transistors T9, T10, T11 and fed to transistor T12 which produces short sampling pulses. These pulses are then applied via long-tailed pair T14, T14 to the gating input of gate T16, T17. During a sampling pulse capacitor C2 charges to the value of the instantaneous value of the sawtooth applied at 41, T18, T19 isolating the capacitor from the output 43.