GB1379269A - Semiconductor device manufacturing process - Google Patents

Semiconductor device manufacturing process

Info

Publication number
GB1379269A
GB1379269A GB4576572A GB4576572A GB1379269A GB 1379269 A GB1379269 A GB 1379269A GB 4576572 A GB4576572 A GB 4576572A GB 4576572 A GB4576572 A GB 4576572A GB 1379269 A GB1379269 A GB 1379269A
Authority
GB
United Kingdom
Prior art keywords
region
holes
oxide
etching
body surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4576572A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intersil Corp
Original Assignee
Intersil Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intersil Inc filed Critical Intersil Inc
Publication of GB1379269A publication Critical patent/GB1379269A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Memories (AREA)

Abstract

1379269 Semi-conductor devices INTERSIL Inc 4 Oct 1972 [13 July 1972] 45765/72 Heading H1K A method for diffusing impurities of the same conductivity type into different regions of a semiconductor body to produce different dopant concentrations using a single accurately aligned mask comprises producing an apertured mask 13 on an oxide layer on a semi-conductor body surface, etching the oxide to a predetermined depth, Fig. 1c, marking some of the holes, and continuing etching of the remaining holes, Fig. 1E until a desired oxide thickness remains on the body surface. Further holes may then be masked and the remaining holes may be extended, by etching, to the body surface, Fig. 1G, where a heavy dopant concentration may be produced by diffusion into the body to form, for example, an isolation region. The masking may then be removed, and the previously masked holes extended until they also reach the body surface. A lighter doping concentration may then be diffused into the newly-exposed region and also into the heavily doped first region. Three apertures 21, 22, 23 may be used to produce respectively an isolation region, a base region and a resistive region. The depth at which etching is stopped may be determined by the colour of the oxide thereat. The advantage of small masks, e.g. 24, covering the unfinished holes is that alignment is not critical. A further region of the opposite conductivity type may be diffused into the isolation region, through the same aperture, to form a conductive strip for interconnection purposes as described and claimed in Specification 1,379,270. The body may be of silicon, the oxide silicon oxide, and aluminium may be used to interconnect regions to form an integrated circuit for memory applications.
GB4576572A 1972-07-13 1972-10-04 Semiconductor device manufacturing process Expired GB1379269A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US27157272A 1972-07-13 1972-07-13

Publications (1)

Publication Number Publication Date
GB1379269A true GB1379269A (en) 1975-01-02

Family

ID=23036150

Family Applications (2)

Application Number Title Priority Date Filing Date
GB4576572A Expired GB1379269A (en) 1972-07-13 1972-10-04 Semiconductor device manufacturing process
GB14474A Expired GB1379270A (en) 1972-07-13 1972-10-04 Integrated circuit manufacturing process

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB14474A Expired GB1379270A (en) 1972-07-13 1972-10-04 Integrated circuit manufacturing process

Country Status (7)

Country Link
JP (1) JPS588127B2 (en)
CA (1) CA998778A (en)
DE (1) DE2245368A1 (en)
FR (1) FR2192382B1 (en)
GB (2) GB1379269A (en)
IT (1) IT966758B (en)
NL (1) NL7211634A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3957552A (en) * 1975-03-05 1976-05-18 International Business Machines Corporation Method for making multilayer devices using only a single critical masking step
US4135954A (en) * 1977-07-12 1979-01-23 International Business Machines Corporation Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers
JPS5558569A (en) * 1978-10-24 1980-05-01 Mitsubishi Electric Corp Manufacture of semiconductor device
US4243435A (en) * 1979-06-22 1981-01-06 International Business Machines Corporation Bipolar transistor fabrication process with an ion implanted emitter
JPS5654062A (en) * 1979-10-09 1981-05-13 Fujitsu Ltd Production of semiconductor device
JPS5792862A (en) * 1980-12-01 1982-06-09 Mitsubishi Electric Corp Manufacture of semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR986067A (en) * 1949-03-02 1951-07-26 Road indicator
US2669457A (en) * 1950-04-07 1954-02-16 George R Culbertson Synchronized vehicle motion controlled record reproducing talking unit
US2965720A (en) * 1957-03-29 1960-12-20 Bumstead Robert Tape recorder monitoring system and start-stop device therefor
US3575575A (en) * 1969-01-06 1971-04-20 David W Kean Tape and tape transport providing distance synchronized messages
FR2165319A5 (en) * 1971-12-20 1973-08-03 Deldalle Michel

Also Published As

Publication number Publication date
CA998778A (en) 1976-10-19
IT966758B (en) 1974-02-20
JPS588127B2 (en) 1983-02-14
NL7211634A (en) 1974-01-15
FR2192382B1 (en) 1976-08-20
GB1379270A (en) 1975-01-02
JPS4940062A (en) 1974-04-15
DE2245368A1 (en) 1974-01-24
FR2192382A1 (en) 1974-02-08

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee