GB1358308A - System for the transmission of information representative of a transition between two states - Google Patents

Abstract

1358308 Digital transmission DE STAAT DER NEDERLANDEN TEN DEZE VERTEGENWOORDIGD DOOR DE DIRECTEUR-GENERAAL DER POSTERIJEN TELEGRAFIE EN TELEFONIE 28 Sept 1971 [1 Oct 1970] 45098/71 Heading H4P In a system for transfer of point of time and direction of a transition having at the transmitter a scanning device for scanning the input at a fixed repetition rate and controlling an encoding device which comprises means for representing, in a code word having a fixed number of bits, e.g. 4 or 5, the direction of a transition and its place in a fixed pattern, the pattern being repeated at a selected multiple of the repetition rate, the invention resides in an encoding device which assigns within the code word 3 bits which are characteristic of the state after transition. At the receiver a reforming device includes a shift register having one stage more than the fixed number, and a logic circuit effecting a "two out of three" majority decision on three places in the shift register. At the transmitter input signals s are scanned under the control of clock pulses in a D-type trigger circuit RT the output from which is passed to a shift register comprising six D-type trigger circuits BS-ST the shift register being driven by transitions AT- of a -4 arrangement of J-K flip-flops BT, AT receiving clock pulses c. A single shot trigger circuit P1 is connected to detect 0#1 transitions of s by means of output rt from RT, and trigger circuit P2 1#0 transitions by means of an output rt. Outputs #p1, #p2 are connected to inputs of RS, QS, PS for simultaneously bringing them into one of two states. The other outputs p1, p2 are connected to inputs of an encoding device comprising AND gates K1-K8 and NOR gates L1-L4. A switch SW enables stage AS to be by-passed thence develop a pattern of code words, 4 or 5 bits in registers BS-PS which are transmitted through stage ST to line. At a 4 bit receiver, Fig. 3, incoming signals sr are fed to a clock pulse sync. circuit CL, clock pulses cl from which are fed to a trigger circuit CT which clocks a shift register BR-NR also receiving input signals sr, majority decision being performed by NAND gates C1-C3 and D1, D2 tapped from the outputs of QR-NR. The position of bits contained in a code word is determined by NAND gates N5, N6 through H1, H2 which combine inputs as shown in the Fig. The reforming device also includes J-K trigger circuit ET having h1, h2, d1, d2 inputs and clock pulses cl, the outputs et, et controlling single shot trigger circuits p3, p4, et also being the output from the arrangement. Depending on the position of an error the majority decision circuit may be accelerated or retarded. A 5 bit receiver is described with reference to Fig. 2 (not shown).