GB1297699A - - Google Patents

Abstract

1297699 Data storage SIEMENS AG 17 March 1970 [18 March 1969] 12658/70 Heading G4C [Also in Division H3] In a circuit which blocks spurious pulses occurring between perodic data slots, e.g. pulses resulting from redundant flux charges in a magnetic tape system and occurring between adjacent bits of the same value, the blocking period is controlled by a disconnectible circuit in dependence upon the rate of occurrence of ouput pulses. In Figs. 2 and 3 the leading edges of pulses N act via a Nand gate G4 of a bi-stable circuit G3, G4 to effect setting to the state in which A1 is "zero" and A2 "one". This enables a Nand gate Gl so that the positive going edge of the pulses is inverted in G1 and cuts off TO. After a delay t, capacitor C has charged to the threshold level of Nand gate G2 and the "zero" output of this restores the bi-stable circuit. Pulse Al thus lasts from the end of the delay until the leading edge of the input pulse and the output M, which is used in means not shown to control the blocking, is extended to the trailing edge of the input pulse. In order to adjust the blocking period to accord with the data rate represented by T, the charging supply is varied inversely with the rate. The supply is obtained from the pulses M by a circuit (Fig. 4) in which the pulses are amplified at V and filtered by C2, C3, R3 to obtain an average value which is taken out at US via an emitter follower E.F. During the starting period a fined voltage at US may be provided from ST via T3. This is switched in by changing the state of a bistable circuit G8, G9 to short the base of EF1 through T5 and to remove the short through T4 at the base of EF2. To allow for pulses of different duty cycle the M pulses may be obtained by combining in gate G6 (Fig. 4) pulses M1, M2 of different delay obtained from two circuits used alternately (Fig. 5, not shown).