GB1296199A - - Google Patents

Abstract

1296199 Decoder KING & DONNE Ltd 21 May 1970 24670/70 Heading G4H A decoder for decoding signals consisting of trains of like digital pulses, the number thereof representing time intervals between like amplitudes of an analogue signal, comprises means for producing a second, rectangular waveform which changes level midway between the changes of level of the trains of digital signals, and means coupling the second signal to a function generator to produce a decoded output signal. The input is fed to a dual shift register 411 together with the outputs of a clock 402 whose frequency has been divided by 2. The elements 420 to 429 of the dual shift register record a "1" when the incoming signal is a "1", and the elements 430 to 439 of the dual shift register records a "1" when the incoming signal is a "0"; thus the two halves of the circuit function in a similar manner. When a 1 reaches unit 429 of shift register 411 it sets AND gate 449 via gate 406 and then causes gate 406 to close, via delay 513. This in turn causes all the AND gates 449, 448 &c. to open if shift register 411 has a 1 in the corresponding unit, and this causes the contents of shift register 411 to be transferred to shift register 408, and in turn to shift register 526. The parallel outputs of the shift register 526 feed a digital to analogue converter 500, which in turn feeds a voltage inverting unit 504 which converts low voltages to high voltages and vice versa. The voltage thus produced is fed to a modulating unit 502. The output of shift register 408 is fed out in serial form by means of clock pulses from clock 402. Since these clock pulses have twice the frequency of those driving shift register 411, the digitally encoded signal contained in the serial output of shift register 408 changes its amplitude, i.e. goes from "0" to a "1" or vice versa half way between amplitude changes of the incoming signal. The outputs of shift register 408 is also fed to modulating unit 502 whose output thus comprises pulses of variable duration and variable amplitude. The output of this unit is fed to integrator 509 to produce a triangular waveform with peaks of equal amplitude, which is fed to a function generator 511 which produces a variable sine wave output. The left- and right-hand sides of the circuit function in a similar manner and operate alternately. Shift register 524 causes a gate 508 to be closed whenever there is no input into the circuit. In an alternative embodiment the digital-toanalogue conversion is carried out by means of exclusive OR gates (527 to 535), Fig. 2 (not shown), whose inputs are fed from shift register 526, and whose outputs control a series of gates, which in turn control a number of weighted resistors. In yet another embodiment. Fig. 3, the dual shift register 411 feeds directly via an AND gate bank to a shift register 408, whose output is fed out serially at twice the speed at which the input signal is advanced down shift register 411. This output is fed out through an integrator 508 so that the output of the circuit is a triangular waveform.