GB1278927A - A method of manufacturing a lead frame for a semiconductor device - Google Patents

A method of manufacturing a lead frame for a semiconductor device

Info

Publication number
GB1278927A
GB1278927A GB4925270A GB4925270A GB1278927A GB 1278927 A GB1278927 A GB 1278927A GB 4925270 A GB4925270 A GB 4925270A GB 4925270 A GB4925270 A GB 4925270A GB 1278927 A GB1278927 A GB 1278927A
Authority
GB
United Kingdom
Prior art keywords
plate
lead frame
portions
manufacturing
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4925270A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1278927A publication Critical patent/GB1278927A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

1278927 Semi-conductor devices HITACHI Ltd 16 Oct 1970 [29 Oct 1969] 49252/70 Heading H1K. A method of forming a lead frame from a metal plate comprises selectively removing a photoresist coating from portions of the plate, and plating the exposed portions, exposing further portions of the plate and removing these secondly exposed portions in order to form the lead frame. The plate may be electroplated with gold, and the second portions removed by etching. The photoresist may be of positive or negative type, and be exposed via a suitable mask. The plate may be an alloy of iron, cobalt and nickel.
GB4925270A 1969-10-29 1970-10-16 A method of manufacturing a lead frame for a semiconductor device Expired GB1278927A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8600469 1969-10-29

Publications (1)

Publication Number Publication Date
GB1278927A true GB1278927A (en) 1972-06-21

Family

ID=13874521

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4925270A Expired GB1278927A (en) 1969-10-29 1970-10-16 A method of manufacturing a lead frame for a semiconductor device

Country Status (2)

Country Link
FR (1) FR2066647A5 (en)
GB (1) GB1278927A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2129612A (en) * 1982-09-30 1984-05-16 Sumitomo Metal Mining Co Manufacture of carrier tapes
FR2871335A1 (en) * 2004-06-02 2005-12-09 Possehl Electronic France Sa S METHOD FOR SELECTIVELY DEPOSITING A GALVANIC COATING ON A MINIATURIZED ELECTRICAL CIRCUIT REALIZED BY CHEMICAL ENGRAVING
CN114481239A (en) * 2022-04-06 2022-05-13 新恒汇电子股份有限公司 Flexible lead frame preparation process capable of avoiding electroplating of blind holes

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3960561A (en) * 1975-04-10 1976-06-01 International Business Machines Corporation Method for making electrical lead frame devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2129612A (en) * 1982-09-30 1984-05-16 Sumitomo Metal Mining Co Manufacture of carrier tapes
FR2871335A1 (en) * 2004-06-02 2005-12-09 Possehl Electronic France Sa S METHOD FOR SELECTIVELY DEPOSITING A GALVANIC COATING ON A MINIATURIZED ELECTRICAL CIRCUIT REALIZED BY CHEMICAL ENGRAVING
WO2005125292A1 (en) * 2004-06-02 2005-12-29 Possehl Electronic France S.A. Method for the selective deposition of a galvanic coating on a miniaturised electric circuit created by etching
CN114481239A (en) * 2022-04-06 2022-05-13 新恒汇电子股份有限公司 Flexible lead frame preparation process capable of avoiding electroplating of blind holes
CN114481239B (en) * 2022-04-06 2022-06-24 新恒汇电子股份有限公司 Flexible lead frame preparation process capable of avoiding electroplating of blind holes

Also Published As

Publication number Publication date
FR2066647A5 (en) 1971-08-06

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees