GB1231287A - - Google Patents

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Publication number
GB1231287A
GB1231287A GB1231287DA GB1231287A GB 1231287 A GB1231287 A GB 1231287A GB 1231287D A GB1231287D A GB 1231287DA GB 1231287 A GB1231287 A GB 1231287A
Authority
GB
United Kingdom
Prior art keywords
word
byte
processing
time
operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1231287A publication Critical patent/GB1231287A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/04Addressing variable-length words or parts of words
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

1,231,287. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 15 Aug., 1968 [27 Sept., 1967], No. 39071/68. Heading G4A. A data processing system comprises a main store having word positions for storing variable length multi-word operands which start and end at any byte position within a word position, means to transfer at least one operand from the main store to an auxiliary store a word position at a time, and a processing unit for identically processing successive words of at least one operand stored in the auxiliary store, a byte at a time or a word at a time according to predetermined conditions, under the control of control data from the main store. The auxiliary store can hold a word (four 8-bit bytes) of each of two operands from the main store, the main store addresses (word and byte) of the first byte of each operand, and a count field. The count field specifies the number of bytes per operand, except in decimal operations when the two halves of the field specify the numbers of bytes in the two operands respectively. The count field can be decremented by the arithmetic and logic unit as processing proceeds. The byte portions of the addresses stored in the auxiliary store can be transferred to and stored in a sub-unit (byte) accessing and modifier circuit which can increment and decrement them (according to whether bytes are taken going leftwards or rightwards along the words). This circuit also stores a 4-bit mask which is updated as each byte is processed to indicate which byte positions are to be overwritten when results of the processing are returned to overwrite one operand in the main store. Processing involving two operands is done a byte at a time unless the circuitry detects that bytes to be combined are correspondingly positioned in their respective words when complete words are processed a word at a time, but incomplete words (e.g. the last word position, if the operand does not end on a word boundary) are still processed a byte at a time. Processing involving a single operand can be done a word at a time for incomplete words. Processing is serial by byte even in the "word at a time" processing. In "word at a time" processing, the system remains in execute mode during the processing of a complete word, using the same control data (a microprogramme word read from main store into a control register) repetitively, and only then transfers to another mode, whereas with "byte at a time" processing, transfer to another mode occurs after each byte. The other modes provided are for transfer of words between the main and auxiliary stores and updating of the count field. Modes are changed by microprogramme branching under control of the incremented/ decremented byte addresses in the sub-unit accessing and modifier circuit and the decremented count field from the auxiliary store via a status register.
GB1231287D 1967-09-27 1968-08-15 Expired GB1231287A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US67108167A 1967-09-27 1967-09-27

Publications (1)

Publication Number Publication Date
GB1231287A true GB1231287A (en) 1971-05-12

Family

ID=24693067

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1231287D Expired GB1231287A (en) 1967-09-27 1968-08-15

Country Status (2)

Country Link
ES (1) ES358539A1 (en)
GB (1) GB1231287A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0066360A1 (en) * 1981-05-21 1982-12-08 Kabushiki Kaisha Toshiba Integrated circult information precessor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0066360A1 (en) * 1981-05-21 1982-12-08 Kabushiki Kaisha Toshiba Integrated circult information precessor

Also Published As

Publication number Publication date
ES358539A1 (en) 1970-04-16

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees