GB1388593A - Output format control for electronic computers - Google Patents

Abstract

1388593 Digital calculator ING COLIVETTI & C SpA 19 April 1972 [22 April 1971] 18224/72 Headings G4A and G4H A digital calculator includes a recirculating memory comprising two registers containing a series of digits and symbols respectively and is arranged serially to read the digits from the first register with the symbols from the second register interposed in the series of digits in appropriate positions. The calculator is similar to that described in Specification 1,259,210 which is referred to, but includes two one character (eight bit) shift registers KA, KB. Specification 1,103,384 is also referred to. General.-The calculator includes a delay line store LDR containing sixteen registers each storing thirty-one eight-bit characters, the registers being interleaved at bit level. Corresponding bits from all registers are available simultaneously at the output of serial/parallel converter 19. A read only memory contains program sub-routines accessed by "jump" instructions, (see Specification 1,259,210). Two single character shift registers KA and KB may be interposed in the circulation path of a selected delay line register so as to shift that register relative to the others. The shift registers may be connected to adders 34, 35 to function as counters, see "Arithmetic operations in Digital Computers"-Richards p. 198. Output to peripheral.-Data from one of the delay line registers may be transferred to a peripheral, e.g. a printer, with punctuation symbols inserted between selected digits. Numeric data is loaded in register A (output LA from converter 19) and the symbols in the appropriate character locations of register M (output LM). Switching network 97 connects shift register KA in the circulation loop of register M for a number of delay line cycles until the contents of registers A and M are aligned. Register A is then connected to shift register KB which functions as an output buffer. The digits in register A are read out serially until a symbol is detected in the M register at the character position corresponding to that in the A register which is about to be read out. The symbol is read from register M via KB and the serial read out from register A resumed. Fixed length data.-Arrangements are provided for limiting to 15 the number of digits used in calculations by discarding digits of lesser significance. During a circulation of register A the number of digits is counted by shift register KA, in conjunction with adder 34, in increasing order of significance starting with the least significant digit, the contents of the counter having been preset to 15. The digits read from the register are prevented from recirculating until the counter, which has a maximum count equal to the number of digit positions in the register, i.e. 31, overflows. Subsequent digits are then recirculated so that the number of digits in register A at the end of the cycle is 15. Fixed/floating point conversions.-Initially register A contains a fixed point number and register M a single zero digit which contains a decimal point. The decimal points in the registers are aligned by relative shifting (see above) and a bi-stable (N7) is set to 1 by the decimal point in register A and reset to zero by a non-zero digit following the point so as to indicate whether the contents of register A are greater than or less than one. If the contents are less than one register A is connected to shift register KA so as to be shifted one place left during each cycle, adder 34 subtracting one from the (initially zero) contents of register M. The process continues until the decimal point in register M is aligned with the most significant non-zero digit in register A. The relative shifting is then halted and a decimal point written in register A aligned with that in register M. Register A thus contains the mantissa and register M the exponent. If the contents of register A are greater than one the procedure is similar except that register M is circulated via shift register KB and adder 35 adds one into register M for each cycle. The floating point representation may be written in a single register as a fixed point number whose integral part represents the mantissa. Reverse conversions from floating point (represented as a fixed point number, see above), to fixed point are described. The single number is separated into integral and decimal portions stored in registers M and A respectively. The sign of the exponent is tested and if negative causes register A to be recirculated via shift register KB, adder 35 adding one into register M at each cycle until the contents of M are zero when the decimal point in register A is erased and rewritten aligned with that in register M. If the exponent sign is positive the procedure is similar except that register A is recirculated via shift register KA, adder 34 subtracting one from register M at each cycle.