GB1184932A - Sequence of Operations Performance Controller - Google Patents

Abstract

1,184,932. Timed control of electric circuits. INTERNATIONAL BUSINESS MACHINES CORP. July 6, 1967 [July 15, 1966], No. 31089/67. Heading G3T. Apparatus for controlling the performance of a series of operations, of, for example, traffic signals, comprises (a) means for measuring elapsed time (b) a recirculatory storage system for storing representations of the nature and specified time duration of each operation, (c) means for selecting and initiating performance of an operation (d) means for comparing the measured elapsed time from the initiation of the performance with the specified time duration of a selected operation, and (e) means for terminating said performance when the measured elapsed time equals said specified time duration. The described embodiment utilizes the techniques of an electronic digital computer and comprises a clock pulse generator 7, Fig. 1, controlling the flow of data in a memory loop including a shift register, having cells CSC-1 to CSC-10, and a delay line 233. The data is represented in Fig.2 as arranged in ten fields A to J of twelve bit positions BP1 to BP12. The bits SC in Field A represent sixtieths of a second, and the bits ETC in Field B seconds, of elapsed time. In Fields C to J the bits SSLI sequence the loading of the memory from the computer interface 13, the bits S1FA, S2FA, &c., denote the first and second functions, &c., to be performed, the bits S1SR denote which state is active, and the bits S1TO, S2TO, etc. denote the scheduled durations of the various functions. The bits SC and ETC are produced by a "sidereal time control" 11, the time base of which is derived from a 60 cycle power supply. At the commencement of a programme the S1FA bits are stored in an output function buffer 14 and a register 15, and the S1TO bits stored in a buffer 16. The S1SR bit in Field C is a binary one to indicate that the Field C is active. Elapsed time is counted in Field B in response to timing pulses produced by the "sidereal time control" 11, and when the elapsed time equals the scheduled duration stored in the buffer 16 a comparator 17 activates the active state control 18 to stifle the S1SR-1 bit from Field S to Field D, so that the operations controlled by the Field C are terminated and those controlled by the Field D commanded, to be terminated and followed in a similar manner by those controlled by Fields E to J.