US3302170A - Traffic light control buffer - Google Patents

Description

Jan. 31, 1967 R. A. JENSEN ETAL TRAFFIC LIGHT CONTROL BUFFER 2 Sheets-Sheet 1 Filed April 28, 1964 FIG.1

CENTRAL PROCESSOR PERIOD DURATION VALUES PERIOD I READ-IN 1 i 17C 18C "' 19C 17a 18b 7/CL00K PULSES I 21 20c I 19b I READ IN coIITRoI BUFFER BUFFER I BUFFER CONTROLLER CONTROLLER CONTROLLER (FIG. 2) 5 (FIR 2I \IRb (FIG. 2) 5 I f I 23 I #431:

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I vENToRs ROBERT A.JENSEN WILBUR J. LEVINE ATTORNEY Jan. 31, 1967 Filed April 28, 1964 R. A. JENSEN ETAL TRAFFIC LIGHT CONTROL BUFFER FIG.2

2 Sheets-Sheet L:

L AND INPUT PERIOD DURATION PERM) REALHN OFFSET OFFSET.

VALUES CLOCK READ III CONTROL wg 19M: 'ZIN'PULSES /2o AND 5 1 COUNTER nuauma AN RED PERIOD L REGljzTER I AND 52 52 57 I AND ANDLIL GREEN PERIOD REGISTER I 59' -45 WAND 53 HR {73 IIEI) AND 55 I16 3-wAY AMBER PERIOD 5 AND AND EXCLUSIVE REGISTER 1 E OR 2 AND ADVANCE" 3 IIIIIII; GREEII AMBER GI GI 27R 27G J 27A INV 3/ SYNCHRONIZING 27 25 N ADVANCE SIGNAL United States Patent 3,302,176 TRAFFIC LIGHT CONTROL BUFFER Robert A. Jensen, Peekskill, and Wilbur J. Levine, Poughkcepsie, N.Y., assignors to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Apr. 28, 1964, Ser. No. 363,147 7 Claims. (Cl. 340-41) This invention relates to systems for controlling traffic lights, and more particularly to a buffer controller which stores commands from a central processor and independ ently guides the operation of a traffic light.

The high density of trafiic in cities has brought about the use of highly complex control systems for controlling tratlic lights to relieve the traffic congestion. Some of the control systems sample the trafiic at various points in the city and process the samples at a central processor to determine the manner in which the individual traffic lights should be operated in order to provide the most effective use of the roads.

Other control systems are based on the variation in traffic caused by rush hours and other disturbances during the days. These systems alter the operation of the traffic lights to accommodate the adjustment in tralfic flow during certain times of the day and night.

Often the control system described above employ a central processor which processes the data and computes the optimum manner in which the trafiic lights may be controlled. The central processor is often a computer or other complex device for performing calculations and storing data. When the traffic lights are controlled directly by the central processor, a great deal of time and apparatus of the central processor is used to generate control signals to actuate the traffic lights.

Accordingly, it is an object of the present invention to provide an improved traffic control system wherein the traffic lights require less of the central processors time and apparatus.

It is a further object of the present invention to provide a traffic control system having suflicient flexibility to accommodate changes in traffic density and direction of flow.

Still another object of the present invention is to provide a traflic control system employing a minimum amount of control circuitry and other apparatus.

It is another object of the present invention to provide a trafiic control system capable of automatically synchronizing the operation of the trafiic lights with the control system.

These and other objects of the present invention are accomplished by providing a buffer controller located between each trafiic light and the central processor. The buffer controller stores commands sent by the central processor and guides the operation of the associated traffic light. The same repetitive operation is performed until a new command is sent from the central processor.

Since the central process-or provides command signals only when an adjustment is needed, most of the time of a central processor is spent computing new sets of trafiic light operations which provide the optimum control over the tratlic flow.

In accordance with the present invention a number of registers, one for each light energizing period (hereinafter called period) of the light cycle are included in the buffer controllers. The registers store signals supplied by the central processor and are read out one by one in a sequential fashion. The values stored in each register determine the length of the red, green and amber periods of the traflic light.

In accordance with another aspect of the present invention signals are fed back from the trafiic light to the associated buffer controller indicating the present period of the trafiic light. These signals are compared with the operation of the buffer controller to determine whether both are synchronized in operation. If not, the buffer controller automatically provides a series of signals to advance the operation of the trafiic light until synchronism is achieved.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIG. 1 is a block diagram illustrating the general op eration of a trafiic control system employing the present invention.

FIG. 2 is a detailed block diagram illustrating the contents of the buffer controllers shown in FIG. 1.

A traffic control system is shown in FIG. 1. Three traffic lights Ila-c are controlled by three bufier controllers 13a-c. The butter controllers 13a-c receive commands from a central processor 15 through a group of connections 17a-c, 1311-6, 1941-0, 200-0 and 21.

The bufiier controllers 13a-c store the commands from central processor 15 and provide signals on a group of lines 23a-c which are connected to stepper switches ZSa-c respectively. Stepper switches 25a-c advance the operation of trafiic lights Ila-c respectively in response to the signals on lines 23a-c.

The cycle of operation of trafiic lights Ila-c includes three periods. During the first period, the red indicators designated by the letter R as shown in FIG. 1 are illuminated. During the second and third periods the amber and green indicators designated by A and G are illuminated. Stepper switches ZSa-c advance the operation of the associated trafiic lights. Ila-c so that the indicators are illuminated in a sequential fashion, i.e., green, amber, red, green, etc. A group of connections 27a-c feed back signals identifying which indicatorin the associated traffic light Ila-c is illuminated. The signals in connections 27a-c are used to synchronize the operation of butter controllers 13a-c with the operation of trafiic lights Ila-c in a manner to be described in detail with reference to FIG. 2.

FIG. 2 illustrates the details of the butter controllers 13a-c shown in FIG. 1. The same designations are applied to the connections shown in FIGS. 1 and 2 with the exception of the letter designations a-c which are omitted in FIG. 2 since all three buffer controllers 13a-c are identical.

Three registers 31-33 are shown in FIG. 2 which store 6-bit binary numbers representing the time duration of the red period, green period and amber period of the traffic light cycle. Each of the registers 31-33 contain six conventional triggers arranged to turn on and off in response to six inputs as shown in FIG. 2. Each of the triggers in registers 31-33 provides an output indicating whether the trigger is on or oil.

Registers 31-33 are supplied with inputs via a group of AND gates 41-43 which are opened one at a time by signals on connector 18 from the central processor 15. Each of the AND gates 41-43 includes six AND gates, one for each line in connector 17. When one of the AND gates 41-43 is opened the signals on connector 17 are fed to the associated one of the registers 31-33.

In operation when the time interval of one of the periods of the traffic light cycle is to be expanded or reduced, commands are sent from the central processor 15 via connection 18 to open the corresponding one of the AND gates 41-43. At the same time signals are supplied via connection 17 setting the six triggers in one of the registers 31-33 corresponding to the particular period to be adjusted.

There are 2 or 64 different possible settings of the six triggers in each of the registers 31-33. Therefore the interval of each of the periods can be made to vary between 1 and 64 units of time. The number of triggers in each of the registers 31-33 can be expanded or contracted to suit the requirements of the trafiic control system. Also a variety of binary codes can be used to convert each period duration into a particular set of trigger conditions.

The outputs of registers 31-33 are fed through a group of AND gates 51-53 which are opened one at a time in a manner to be described later in the specification. Each of the AND gates 51-53 includes six AND gates, one for each trigger in the register connected thereto. The output of AND gates 51-53 is fed to an OR gate 55 which provides the input to a counter 57. The counter 57 includes six conventional triggers arranged to receive the output of one of the registers 31-33, depending upon which one of the AND gates 51-53 is open. The counter 57 also receives a series of clock pulses on a line 21' originating on line 21 from a central processor in a manner to be described in detail later in the specification.

The interconnections between the six triggers in counter 57 are arranged so that the clock pulses on line 21 cause the triggers to return to the off state after a number of clock pulses are received equal to the units of time represented by the trigger setting initially placed in counter 57. For example where a conventional binary weighted code is assigned to each position of the registers 31-33 the fifth trigger (designated 5) is assigned a weight of 32 units of time. Therefore when the value 32 is received by counter 57 the fifth trigger (designated 5) is turned on while the remaining triggers are turned off. After 16 clock pulses are received on line 21 all of the triggers are turned to the off state. The specific interconnections between the six triggers in counter 57 for accomplishing this function are well known in the art and are not shown herein. It is also apparent that other weights may be assigned to the trigger positions in counter 57 so that various other interconnections between the six triggers in counter 57 may be employed to perform the function of counting the number of clock pulses on line 21' corresponding to the number of units of time represented by the particular initial setting of the six binary triggers in counter 57.

Each of the six triggers in counter 57 supplies an output when the trigger is off. When all of the triggers in counter 57 are off, an AND gate 59 provides a pulse on a line 61. The pulse passes through an OR gate 63 to line 23 connected to a stepper switch 25 which advances a traffic light 11 as described above with reference to FIG. 1.

The pulse on line 61 is also fed to a ring circuit 65 having three stages designated 1, 2 and 3. The stages are operated in a sequential manner in response to the pulses on line 61, i.e. stages 1, 2, 3, 1, etc. The output of stages 1-3 of ring circuit 65 are connected to AND gates 51-53 respectively. In operation each time a pulse is applied to line 61 ring circuit 65 advances to the next stage opening another one of AND gates 51-53 and placing the contents of one of the registers 31-33 into counter 57. After counter 57 counts an equivalent number of clock pulses on line 21, AND gate 59 provides a pulse on line 61 thereby advancing ring circuit 65 resulting in the transfer of the contents of another one of the registers 31-33 into counter 57. Each time the ring circuit 65 advances a signal appears on line 23 advancing the associated traffic light 11.

Ofiset operation Frequently it is desirable to offset the operation of one traffic light with respect to another. That is, in order to keep a vehicle moving along a road through a plurality of intersections the traflic lights are timed so that when the vehicle arrives at each intersection the associated traffic light is in the green period of the operating cycle. This is accomplished by delaying the beginning of the cycle of each traffic light an interval of time equal to the time taken for the vehicle to travel from one intersection to the next intersection.

In order to provide an ofiset in the operation of the bufier controller 13 shown in FIG. 2 the clock pulses applied on line 21 are delayed before arriving at counter 57 via line 21. The offset is needed only once at the beginning of the operation of the buffer controller 13 and need not be repeated each time the buffer 13 completes a cycle of operation.

A counter 57 identical to counter 57 is provided in FIG. 2 to perform the offset operation. The value of the offset is set into counter 57' via connection 19. At the same time the clock pulses on line 21 are blocked from counter 57 by a signal on line 20 which resets a trigger 67 inhibiting an AND gate 69 from passing the clock pulses on line 21 to the input of counter 57 via line 21' The clock pulses on line 21 are applied to the input of counter 57'. After a number of clock pulses are counted equal to the offset value supplied via connection 19, AND gate 59 is conditioned providing an output which sets trigger 67 thereby opening AND gate 69. The clock pulses on line 21 pass through AND gate 69 at this time causing the counter 57 to begin operating in the manner described above. The delayed commencement of operation of counter 57 provides the ofiset necessary to permit continuous flow of traffic through a plurality of innersections.

Synchronizing operation When one of the buffer controllers 13 assumes control over a traffic light 11 the operation of the traffic light must be synchronized with the operation of the ring circuit 65 shown in FIG. 2. After this is accomplished the registers 31-33 control the duration of the red, amber and green indicators in the corresponding traffic light 11.

As described in connection with FIG. 1 signals from the traffic light are fed back through connection 27 to the buffer controller 13 identifying the indicator in traflic light 11 which is illuminated. As shown in FIG. 2 connector 27 includes three lines 27R, 276 and 27A which provide signals to a group of AND gates 71R, 71G, 71A when the red, green or amber indicators are illuminated respectively. Stages 1-3 of ring circuit 65 supply a second input to AND gates 71R, 71G and 71A, respectively. The output of AND gates 71 is applied to a three-way exclusive OR circuit 73 which provides an output whenever only one input is provided by AND gates 71.

An inverter '75 supplies OR gate 63 with an inverted form of the output of exclusive OR circuit 73. In operation inverter 75 supplies a signal to OR gate 63 which in turn advances the operation oftraffic light 11 when the ring 65 and traffic light 1.1 are out of synchronism. For example the first stage of ring circuit 65 supplies a signal to AND gate 71R while the green indicator of trafiic light 11 is illuminated causing a signal to be applied to AND gate 71G. At this time none of the AND gates '71 supplies a signal to exclusive OR circuit 73 and no output signal is supplied to inverter 75. A signal is provided at the output of inverter 75 which passes through OR gate 63 advancing the operation of trafiic light 11 from green to amber.

With traffic light 11 now in the amber period AND gate 71A receives a signal from line 27A and inverter 75 supplies a signal to OR gate 63 causing stepper switch 25 to continue advancing thereby changing traffic light 11 from the amber period to the red period. With the ring circuit 65 remaining in the first stage and trafiic light 11 in the red period both inputs to AND gate 71R are present and a signal is applied to exclusive OR circuit 73. At this time the exclusive OR circuit 73 provides a signal to inverter 75 which in turn inverts the signal causing the absence of a signal at OR gate 63 thereby permitting traffic light 11 to rest in the red period until counter 57 supplies a signal to OR gate 63.

In summary, what has been shown is a buffer controller circuit 13 which relieves the central processor 15 from the continuous control of traflic lights 11. Once the central processor has computed the proper traffic light cycle, the individual period duration values are set into the registers 31-33 shown in FIG. 2 along with the particular offset value which is set into counter 57'.

Once the period duration values and offset values are set into the bufler controllers 13 the central processor 15 merely supplies clock pulses on lines 21 causing the buffer controllers 13 to guide the trafiic lights 11 through the same operating cycle in a repetitive manner until adjustments of the period duration values become necessary. Further the buffer cont-rollers 13 may be arranged to supply their own clock pulses thereby achieving completely independent operation.

The buffer controllers 13 may be located near the central processor 15 while the stepper switches 25 may be located near the traffic light-s 11 in accordance with the preferred embodiment of the present invention.

To prevent failure of the traffic lights 11 the stepper switches 25 may be provided with an internal control which causes the switches to advance the trafiic lights 11 in a predetermined manner should the advance signals on lines 23 fail to arrive after a certain interval of time. However when the buflfer controllers 13 resume control over the traffic lights 11 automatic synchronization is accomplished by AND gates 71, exclusive OR circuit 73 and inverter 75 in the manner described above with regard to FIG. 2.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. In a traflic light control system, controller means and stepping switch means, said controller means actuating said switch means for advancing a traflic light display through a cycle including a plurality of light energizing periods in response to a series of clock pulses, said controller means comprising:

a plurality of registers, each one capable of storing numbers representing the duration of a light energizing period of said cycle; and

counting means for counting a number of said clock pulses corresponding to the number stored in each one of said registers and for providing a control sig nal to advance said traflic light dislay at the completion of each clock pulse count corresponding to said numbers stored in said registers.

2. In a traffic light control system, controller means and stepping switch means, said controller means actuating said switch means for advancing a trafiic light display through a cycle including a plurality of light energizing periods in response to a series of clock pulses, said controller means comprising:

a plurality of registers, each one capable of storing numbers representing the duration of a light energizing period of said cycle;

counting means capable of counting a number of said clock pulses corresponding to numbers applied thereto and providing a control signal to advance said trafiic light display after a number of clock pulses corresponding to the number applied thereto has been counted; and

gating means for applying the number stored in each 5 register to said counting means one by one in a sequential fashion.

3. Apparatus as defined in claim 2 wherein said gating means includes further means for applying the number stored in each one of said registers to said counting means in response to said control signal.

4. In a traflic light control system, controller means and stepping switch means, said controller means actuating said switch means for advancing a t-rafiic light display through a cycle including a plurality of light energizing periods in response to a series of clock pulses, said controller means comprising:

a plurality of registers, each one capable of storing numbers representing the duration of a light energizing period of said cycle;

counting means capable of counting a number of said clock pulses corresponding to the number applied thereto;

sensing means for sensing the end of said count and for providing a control signal to advance said traffic light display; and

gating means for applying the number stored in each register to said counting means one by one in a sequential fashion.

5. Apparatus as defined in claim 4 wherein said gating means includes means for applying the number stored in each one of said registers to said counting means in response to said control signal.

6. Apparatus as defined in claim 5 further characterized by the addition of offset means for inhibiting the operation of said counting means for a certain number of clock pulses at the beginning of said series of clock pulses, whereby the cycle of said traffic light display is delayed.

7. In a traflic light control system for controlling the operation of a traflic light display containing a plurality of indicators, means for synchronizing the operation of said controller and said trafiic light display, said means comprising:

timing means having a plurality of stages, each stage corresponding to a different one of said indicators,

45 for determining the interval of time between control pulses;

a plurality of AND gates each one having two inputs and an output, one of said inputs being energized by the operation of one of said indicators and the other being energized by the corresponding timing means stage;

exclusive OR means having inputs connected to said AND gate outputs and having an output signal;

stepping switch means for sequentially actuating said indicators in response to said output signal, whereby said tralfic light display is advanced until the indicators and the corresponding timing means stages are synchronized in operation.

References Cited by the Examiner UNITED STATES PATENTS 65 NEIL C. READ, Primary Examiner.

THOMAS B. HABECKER, Examiner.

Claims (1)

1. IN A TRAFFIC LIGHT CONTROL SYSTEM, CONTROLLER MEANS AND STEPPING SWITCH MEANS, SAID CONTROLLER MEANS ACTUATING SAID SWITCH MEANS FOR ADVANCING A TRAFFIC LIGHT DISPLAY THROUGH A CYCLE INCLUDING A PLURALITY OF LIGHT ENERGIZING PERIODS IN RESPONSE TO A SERIES OF CLOCK PULSES, SAID CONTROLLER MEANS COMPRISING: A PLURALITY OF REGISTERS, EACH ONE CAPABLE OF STORING NUMBERS REPRESENTING THE DURATION OF A LIGHT ENERGIZING PERIOD OF SAID CYCLE; AND COUNTING MEANS FOR COUNTING A NUMBER OF SAID CLOCK PULSES CORRESPONDING TO THE NUMBER STORED IN EACH ONE OF SAID REGISTERS AND FOR PROVIDING A CONTROL SIGNAL TO ADVANCE SAID TRAFFIC LIGHT DISPLAY AT THE COMPLETION OF EACH CLOCK PULSE COUNT CORRESPONDING TO SAID NUMBERS STORED IN SAID REGISTERS.

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