GB1177021A - Arrangement for Use in Writing in or Reading from Memory Means of a Data Processing Machine - Google Patents

Arrangement for Use in Writing in or Reading from Memory Means of a Data Processing Machine

Info

Publication number
GB1177021A
GB1177021A GB1417767A GB1417767A GB1177021A GB 1177021 A GB1177021 A GB 1177021A GB 1417767 A GB1417767 A GB 1417767A GB 1417767 A GB1417767 A GB 1417767A GB 1177021 A GB1177021 A GB 1177021A
Authority
GB
United Kingdom
Prior art keywords
word
bits
address
instruction
data memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1417767A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of GB1177021A publication Critical patent/GB1177021A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54533—Configuration data, translation, passwords, databases

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Communication Control (AREA)
  • Complex Calculations (AREA)
  • Package Closures (AREA)
  • Containers And Plastic Fillers For Packaging (AREA)

Abstract

1,177,021. Indirect addressing. TELEFONAKTIEBOLAGET L. M. ERICSSON. 28 March, 1967 [25 March, 1966], No. 14177/67. Heading G4A. An indirect addressing scheme in a computer uses a stored table of addresses associated with stored indications of field lengths in different memory blocks. A first instruction accesses a data memory to obtain the number of a connection device (electromagnetic relays) in a telephone network, the number being then placed in a register specified by two bits of a second instruction. Eight further bits of the second instruction are added to 0000000100000000, the result being used to address the data memory to obtain a word in a table therein. Twelve bits of this word, with 0000 following them, constitute the base address of a data memory block containing information about the connection device among others, and the other four bits of the word specify the number of bits (always a non- ,negative integral power of 2) devoted to each connection device in this block. The device number (see above) is shifted under control of these latter four bits (thus effectively multiplying it) to obtain the relative word address of the connection device information with the block. The relative address is added to the base address referred to the word part of the result being placed in a register specified by two further bits of the second instruction (see above), the address of the device field within the word being retained in the arithmetic unit. A third instruction uses the word part to address the data memory and the field-withinword part to select the connection device information from the word thereby read from the data memory.
GB1417767A 1966-03-25 1967-03-28 Arrangement for Use in Writing in or Reading from Memory Means of a Data Processing Machine Expired GB1177021A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE397466A SE331921B (en) 1966-03-25 1966-03-25

Publications (1)

Publication Number Publication Date
GB1177021A true GB1177021A (en) 1970-01-07

Family

ID=20263253

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1417767A Expired GB1177021A (en) 1966-03-25 1967-03-28 Arrangement for Use in Writing in or Reading from Memory Means of a Data Processing Machine

Country Status (8)

Country Link
BE (1) BE695956A (en)
DE (1) DE1549549A1 (en)
FI (1) FI45504C (en)
FR (1) FR1515455A (en)
GB (1) GB1177021A (en)
NL (1) NL6704242A (en)
NO (1) NO118945B (en)
SE (1) SE331921B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2472231A1 (en) * 1979-12-20 1981-06-26 Cii Honeywell Bull DEVICE FOR ADDRESSING INFORMATION ELEMENTS IN A TABLE WITH SEVERAL INPUTS, RECORDED IN A MEMORY
EP0072927A2 (en) * 1981-08-21 1983-03-02 International Business Machines Corporation Device for addressing a memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2472231A1 (en) * 1979-12-20 1981-06-26 Cii Honeywell Bull DEVICE FOR ADDRESSING INFORMATION ELEMENTS IN A TABLE WITH SEVERAL INPUTS, RECORDED IN A MEMORY
EP0032075A1 (en) * 1979-12-20 1981-07-15 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Device for addressing data elements in a multiple-entry table stored in a memory
EP0072927A2 (en) * 1981-08-21 1983-03-02 International Business Machines Corporation Device for addressing a memory
EP0072927B1 (en) * 1981-08-21 1988-10-12 International Business Machines Corporation Device for addressing a memory

Also Published As

Publication number Publication date
FI45504B (en) 1972-02-29
DE1549549A1 (en) 1971-02-18
FI45504C (en) 1972-06-12
NO118945B (en) 1970-03-02
FR1515455A (en) 1968-03-01
SE331921B (en) 1971-01-18
BE695956A (en) 1967-09-01
NL6704242A (en) 1967-09-26

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