GB1166593A - Data Processing Apparatus - Google Patents
Data Processing ApparatusInfo
- Publication number
- GB1166593A GB1166593A GB720168A GB720168A GB1166593A GB 1166593 A GB1166593 A GB 1166593A GB 720168 A GB720168 A GB 720168A GB 720168 A GB720168 A GB 720168A GB 1166593 A GB1166593 A GB 1166593A
- Authority
- GB
- United Kingdom
- Prior art keywords
- dividend
- register
- divisor
- flop
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/4915—Multiplying; Dividing
- G06F7/4917—Dividing
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
1,166,593. Subtraction for division. INTERNATIONAL BUSINESS MACHINES CORP. 14 Feb., 1968 [2 March, 1967], No. 7201/68. Heading G4A. Data processing apparatus for the iterative subtraction of a stored divisor from a stored dividend comprises two dividend stores, arithmetic means for performing subtraction operations, reading means for reading data from the dividend stores alternately in succeeding subtraction iterations and for writing the result of each subtraction into the store other than that from which data was read for that iteration, and means for inhibiting the reading means so that when the results of succeeding subtractions change from positive to negative the reading means next reads from the dividend store which was read for the last iteration. For binary-coded-decimal division by iterated subtraction, a store 3, addressed by register 4, initially holds the dividend twice and the divisor once. The register 4 can be set via lines 17 with the divisor address or with the common part of the two dividend addresses, the rest of the latter (a single bit) being supplied by flipflop 20. In each iteration, one of the dividend locations is read out through gates 6, parallel adder 1 to register 2, the address register receiving the state of flip-flop 20 in true form. Then the divisor location is read out via complementer 7 to adder 1 at the same time as register 2 is gated to adder 1 by gates 9, the remainder being passed via register 2 to the other dividend location in store 3, the address register 4 having received the state of flip-flop 20 in inverse form for this. If the remainder was positive, AND gate 44 reverses flip-flop 20 and increments quotient counter 5, the next iteration proceeding as before except that due to the reversal of flip-flop 20 the other dividend location is read out (i.e. the location which received the remainder from the previous iteration). If the remainder was negative, absence of a high order carry from adder 1 sets flip-flop 45 preventing reversal of flip-flop 20 and incrementing of quotient counter 5 but instead gating the quotient count to a quotient register 12, passing the divisor from store 3, via a shifter 8 (which shifts it by one decimal digit), adder 1 and register 2 back to store 3, resetting the quotient counter 5 and flip-flop 45, and shifting quotient register 12 in preparation for reception of the next decimal digit from quotient counter 5. The dividend and divisor could be stored in three separate registers rather than a store 3. Processing may be serial by byte rather than parallel as above. Binary operands may be used. A multiple of the divisor could be subtracted instead of the divisor.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEJ0033105 | 1967-03-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1166593A true GB1166593A (en) | 1969-10-08 |
Family
ID=7204662
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB720168A Expired GB1166593A (en) | 1967-03-02 | 1968-02-14 | Data Processing Apparatus |
Country Status (3)
Country | Link |
---|---|
AT (1) | AT275922B (en) |
DE (1) | DE1549461B2 (en) |
GB (1) | GB1166593A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0056525A1 (en) * | 1980-12-24 | 1982-07-28 | Honeywell Information Systems Inc. | Division system |
GB2239536A (en) * | 1989-11-15 | 1991-07-03 | United Technologies Corp | Binary division of signed operands |
GB2306711A (en) * | 1995-10-31 | 1997-05-07 | Samsung Electronics Co Ltd | Division circuit |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58132837A (en) * | 1982-02-03 | 1983-08-08 | Hitachi Ltd | Divider |
-
1967
- 1967-03-02 DE DE19671549461 patent/DE1549461B2/en active Granted
-
1968
- 1968-02-14 GB GB720168A patent/GB1166593A/en not_active Expired
- 1968-02-29 AT AT198068A patent/AT275922B/en active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0056525A1 (en) * | 1980-12-24 | 1982-07-28 | Honeywell Information Systems Inc. | Division system |
GB2239536A (en) * | 1989-11-15 | 1991-07-03 | United Technologies Corp | Binary division of signed operands |
GB2239536B (en) * | 1989-11-15 | 1994-05-11 | United Technologies Corp | Binary division of signed operands |
GB2306711A (en) * | 1995-10-31 | 1997-05-07 | Samsung Electronics Co Ltd | Division circuit |
GB2306711B (en) * | 1995-10-31 | 2000-04-26 | Samsung Electronics Co Ltd | A parallel processing division circuit |
Also Published As
Publication number | Publication date |
---|---|
DE1549461A1 (en) | 1971-02-04 |
DE1549461C3 (en) | 1974-10-03 |
AT275922B (en) | 1969-11-10 |
DE1549461B2 (en) | 1974-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB1104975A (en) | Compiling system | |
GB1098329A (en) | Data processing device | |
GB1063014A (en) | Improvements in or relating to electronic digital computers | |
ES362185A1 (en) | Instruction retry byte counter | |
GB890323A (en) | Improvements in or relating to electronic data processing apparatus | |
US3553445A (en) | Multicipher entry | |
GB1364215A (en) | Divider | |
FR1278634A (en) | Data processing system | |
US3378677A (en) | Serial divider | |
GB1166593A (en) | Data Processing Apparatus | |
US3391391A (en) | Computation with variable fractional point readout | |
GB1049680A (en) | Digital divider | |
GB1078175A (en) | High speed divider for a digital computer | |
GB1166646A (en) | Electronic Digital Data Processing Machine | |
GB1179274A (en) | An Improvement relating to the Justification of Operands in an Arithmetic Unit. | |
GB1241983A (en) | Electronic computer | |
GB1512362A (en) | Digital data processing apparatus | |
GB1116675A (en) | General purpose digital computer | |
GB991734A (en) | Improvements in digital calculating devices | |
GB1388593A (en) | Output format control for electronic computers | |
GB1517397A (en) | Data processing system | |
US3500027A (en) | Computer having sum of products instruction capability | |
GB898594A (en) | Improvements in and relating to arithmetic devices | |
GB1053686A (en) | ||
GB1189148A (en) | Computer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |