GB1166593A - Data Processing Apparatus - Google Patents

Abstract

1,166,593. Subtraction for division. INTERNATIONAL BUSINESS MACHINES CORP. 14 Feb., 1968 [2 March, 1967], No. 7201/68. Heading G4A. Data processing apparatus for the iterative subtraction of a stored divisor from a stored dividend comprises two dividend stores, arithmetic means for performing subtraction operations, reading means for reading data from the dividend stores alternately in succeeding subtraction iterations and for writing the result of each subtraction into the store other than that from which data was read for that iteration, and means for inhibiting the reading means so that when the results of succeeding subtractions change from positive to negative the reading means next reads from the dividend store which was read for the last iteration. For binary-coded-decimal division by iterated subtraction, a store 3, addressed by register 4, initially holds the dividend twice and the divisor once. The register 4 can be set via lines 17 with the divisor address or with the common part of the two dividend addresses, the rest of the latter (a single bit) being supplied by flipflop 20. In each iteration, one of the dividend locations is read out through gates 6, parallel adder 1 to register 2, the address register receiving the state of flip-flop 20 in true form. Then the divisor location is read out via complementer 7 to adder 1 at the same time as register 2 is gated to adder 1 by gates 9, the remainder being passed via register 2 to the other dividend location in store 3, the address register 4 having received the state of flip-flop 20 in inverse form for this. If the remainder was positive, AND gate 44 reverses flip-flop 20 and increments quotient counter 5, the next iteration proceeding as before except that due to the reversal of flip-flop 20 the other dividend location is read out (i.e. the location which received the remainder from the previous iteration). If the remainder was negative, absence of a high order carry from adder 1 sets flip-flop 45 preventing reversal of flip-flop 20 and incrementing of quotient counter 5 but instead gating the quotient count to a quotient register 12, passing the divisor from store 3, via a shifter 8 (which shifts it by one decimal digit), adder 1 and register 2 back to store 3, resetting the quotient counter 5 and flip-flop 45, and shifting quotient register 12 in preparation for reception of the next decimal digit from quotient counter 5. The dividend and divisor could be stored in three separate registers rather than a store 3. Processing may be serial by byte rather than parallel as above. Binary operands may be used. A multiple of the divisor could be subtracted instead of the divisor.