GB1164000A - Data Processing System with Controls to Deal with Requests from Subsystem for Prohibited Operations - Google Patents
Data Processing System with Controls to Deal with Requests from Subsystem for Prohibited OperationsInfo
- Publication number
- GB1164000A GB1164000A GB23874/67A GB2387467A GB1164000A GB 1164000 A GB1164000 A GB 1164000A GB 23874/67 A GB23874/67 A GB 23874/67A GB 2387467 A GB2387467 A GB 2387467A GB 1164000 A GB1164000 A GB 1164000A
- Authority
- GB
- United Kingdom
- Prior art keywords
- address
- memory
- access
- sub
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015654 memory Effects 0.000 abstract 8
- 230000004075 alteration Effects 0.000 abstract 1
- 238000001514 detection method Methods 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 230000011664 signaling Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30054—Unconditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3875—Pipelining a single stage, e.g. superpipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4818—Priority circuits therefor
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Programmable Controllers (AREA)
- Computer And Data Communications (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Accessory Devices And Overall Control Thereof (AREA)
- Electrophonic Musical Instruments (AREA)
- Mobile Radio Communication Systems (AREA)
- Executing Machine-Instructions (AREA)
- Logic Circuits (AREA)
- Hardware Redundancy (AREA)
- Storage Device Security (AREA)
- Debugging And Monitoring (AREA)
Abstract
1,164,000. Data processing. GENERAL ELECTRIC CO. 23 May, 1967 [25 May, 1966], No. 23874/67. Heading G4A. In a data processing system, an attempted prohibited action by one of a plurality of subsystems at the controller causes supply of a code to all the sub-systems and a pulse to the one sub-system. Memories have associated memory controllers which can receive commands from various subsystems, viz. processors and input/output controllers, on a priority basis. The command code from the selected sub-system to a given memory controller may be accompanied by a memory address and a data word. The command code is decoded in the memory controller and may cause one of the usual types of memory access or may load the data word into either an upper or a lower file protect register. In the case of a memory access, a portion of the address is decoded to select one of a matrix of AND gates which also receives a corresponding bit from one of the file protect registers to produce a signal indicating whether the address is protected or not. An access involving alteration of stored data (or any access) to a protected address is a prohibited action. Other prohibited actions arise on (a) detection of parity error in data accessed from memory, (b) attempted access to a non-existent address, (c) a command only allowable from a particular (variable) processor coming from another processor, or coming from the right processor but when the latter is in the wrong mode. Any prohibited action causes a code identifying it to be sent to all sub-systems and a pulse to be sent to the selected sub-system, the pulse causing the latter to respond to the code by repeating the request, stopping and registering the prohibited action, or signalling the prohibited action and continuing with other processing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US55298166A | 1966-05-25 | 1966-05-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1164000A true GB1164000A (en) | 1969-09-10 |
Family
ID=24207624
Family Applications (10)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB23867/67A Expired GB1142290A (en) | 1966-05-25 | 1967-05-23 | Data processing system with improved subsystem communication |
| GB23875/67A Expired GB1177109A (en) | 1966-05-25 | 1967-05-23 | Communication and Control Apparatus in a Computer System |
| GB23866/67A Expired GB1137784A (en) | 1966-05-25 | 1967-05-23 | Data processing system with improved memory |
| GB23874/67A Expired GB1164000A (en) | 1966-05-25 | 1967-05-23 | Data Processing System with Controls to Deal with Requests from Subsystem for Prohibited Operations |
| GB23876/67A Expired GB1174069A (en) | 1966-05-25 | 1967-05-23 | Data Processing System with Access Control for Subsystems |
| GB23869/67A Expired GB1173356A (en) | 1966-05-25 | 1967-05-23 | Apparatus for handling data records in a computer system |
| GB23865/67A Expired GB1186414A (en) | 1966-05-25 | 1967-05-23 | Input/Output Control Apparatus in a Computer System |
| GB23873/67A Expired GB1167945A (en) | 1966-05-25 | 1967-05-23 | Data Processing System with Acces Control for Subsystems. |
| GB23872/67A Expired GB1154516A (en) | 1966-05-25 | 1967-05-23 | Information shift apparatus in a computer system. |
| GB23868/67A Expired GB1150489A (en) | 1966-05-25 | 1967-05-23 | Dual Control Apparatus in Data Processing Equipment |
Family Applications Before (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB23867/67A Expired GB1142290A (en) | 1966-05-25 | 1967-05-23 | Data processing system with improved subsystem communication |
| GB23875/67A Expired GB1177109A (en) | 1966-05-25 | 1967-05-23 | Communication and Control Apparatus in a Computer System |
| GB23866/67A Expired GB1137784A (en) | 1966-05-25 | 1967-05-23 | Data processing system with improved memory |
Family Applications After (6)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB23876/67A Expired GB1174069A (en) | 1966-05-25 | 1967-05-23 | Data Processing System with Access Control for Subsystems |
| GB23869/67A Expired GB1173356A (en) | 1966-05-25 | 1967-05-23 | Apparatus for handling data records in a computer system |
| GB23865/67A Expired GB1186414A (en) | 1966-05-25 | 1967-05-23 | Input/Output Control Apparatus in a Computer System |
| GB23873/67A Expired GB1167945A (en) | 1966-05-25 | 1967-05-23 | Data Processing System with Acces Control for Subsystems. |
| GB23872/67A Expired GB1154516A (en) | 1966-05-25 | 1967-05-23 | Information shift apparatus in a computer system. |
| GB23868/67A Expired GB1150489A (en) | 1966-05-25 | 1967-05-23 | Dual Control Apparatus in Data Processing Equipment |
Country Status (6)
| Country | Link |
|---|---|
| JP (3) | JPS45236860B1 (en) |
| CH (7) | CH506132A (en) |
| DE (8) | DE1298318B (en) |
| FR (6) | FR1564478A (en) |
| GB (10) | GB1142290A (en) |
| SE (5) | SE329287B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999624A (en) * | 1994-06-30 | 1999-12-07 | Compaq Computer Corporation | Remote financial transaction system |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3675209A (en) * | 1970-02-06 | 1972-07-04 | Burroughs Corp | Autonomous multiple-path input/output control system |
| FR2289003A1 (en) * | 1974-02-01 | 1976-05-21 | Honeywell Bull Soc Ind | CONTROL DEVICE FOR DATA TRANSFERS BETWEEN THE CENTRAL MEMORY AND THE PERIPHERAL UNITS OF A COMPUTER SYSTEM |
| US4209839A (en) * | 1978-06-16 | 1980-06-24 | International Business Machines Corporation | Shared synchronous memory multiprocessing arrangement |
| US4306287A (en) * | 1979-08-31 | 1981-12-15 | Bell Telephone Laboratories, Incorporated | Special address generation arrangement |
| GB2092341B (en) * | 1981-02-02 | 1984-09-12 | Picker Int Ltd | Computer peripheral selection |
| GB2147126B (en) * | 1983-09-29 | 1987-01-07 | Memory Ireland Limited | Improvements in and relating to computers |
-
1967
- 1967-05-23 GB GB23867/67A patent/GB1142290A/en not_active Expired
- 1967-05-23 GB GB23875/67A patent/GB1177109A/en not_active Expired
- 1967-05-23 GB GB23866/67A patent/GB1137784A/en not_active Expired
- 1967-05-23 GB GB23874/67A patent/GB1164000A/en not_active Expired
- 1967-05-23 GB GB23876/67A patent/GB1174069A/en not_active Expired
- 1967-05-23 GB GB23869/67A patent/GB1173356A/en not_active Expired
- 1967-05-23 GB GB23865/67A patent/GB1186414A/en not_active Expired
- 1967-05-23 GB GB23873/67A patent/GB1167945A/en not_active Expired
- 1967-05-23 GB GB23872/67A patent/GB1154516A/en not_active Expired
- 1967-05-23 GB GB23868/67A patent/GB1150489A/en not_active Expired
- 1967-05-24 DE DEG50172A patent/DE1298318B/en active Pending
- 1967-05-24 DE DE19671549431 patent/DE1549431A1/en active Pending
- 1967-05-24 DE DE19671549428 patent/DE1549428B2/en active Pending
- 1967-05-24 DE DE19671549424 patent/DE1549424A1/en active Pending
- 1967-05-24 DE DE19671549426 patent/DE1549426A1/en active Pending
- 1967-05-24 DE DE19671549429 patent/DE1549429A1/en active Pending
- 1967-05-24 DE DE1967G0050164 patent/DE1549422B2/en active Granted
- 1967-05-24 DE DE19671549423 patent/DE1549423A1/en active Pending
- 1967-05-25 CH CH736467A patent/CH506132A/en not_active IP Right Cessation
- 1967-05-25 CH CH736667A patent/CH495014A/en not_active IP Right Cessation
- 1967-05-25 FR FR1564478D patent/FR1564478A/fr not_active Expired
- 1967-05-25 FR FR1564477D patent/FR1564477A/fr not_active Expired
- 1967-05-25 JP JP3306967A patent/JPS45236860B1/ja active Pending
- 1967-05-25 SE SE07357/67A patent/SE329287B/xx unknown
- 1967-05-25 SE SE07355/67A patent/SE329517B/xx unknown
- 1967-05-25 CH CH737067A patent/CH495016A/en not_active IP Right Cessation
- 1967-05-25 SE SE07352/67A patent/SE329279B/xx unknown
- 1967-05-25 FR FR107783A patent/FR1545594A/en not_active Expired
- 1967-05-25 CH CH736567A patent/CH486738A/en not_active IP Right Cessation
- 1967-05-25 FR FR107785A patent/FR1545595A/en not_active Expired
- 1967-05-25 JP JP3306667A patent/JPS4510707B1/ja active Pending
- 1967-05-25 JP JP3306167A patent/JPS5323059B1/ja active Pending
- 1967-05-25 FR FR107790A patent/FR1528181A/en not_active Expired
- 1967-05-25 SE SE07356/67A patent/SE329282B/xx unknown
- 1967-05-25 SE SE07353/67A patent/SE340192B/xx unknown
- 1967-05-25 CH CH736767A patent/CH489847A/en not_active IP Right Cessation
- 1967-05-25 CH CH736867A patent/CH505430A/en not_active IP Right Cessation
- 1967-05-25 CH CH736967A patent/CH493886A/en not_active IP Right Cessation
- 1967-05-25 FR FR1564476D patent/FR1564476A/fr not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5999624A (en) * | 1994-06-30 | 1999-12-07 | Compaq Computer Corporation | Remote financial transaction system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PE | Patent expired |