GB1054797A - - Google Patents
Info
- Publication number
- GB1054797A GB1054797A GB1054797DA GB1054797A GB 1054797 A GB1054797 A GB 1054797A GB 1054797D A GB1054797D A GB 1054797DA GB 1054797 A GB1054797 A GB 1054797A
- Authority
- GB
- United Kingdom
- Prior art keywords
- holes
- sheet
- pattern
- solution
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
Abstract
1,054,797. Printed circuits. NORTH AMERICAN AVIATION Inc. Sept. 12, 1963 [Sept. 24, 1962], No. 36017/63. Heading H1R. A multilayer printed circuit board having internal interconnections between printed wiring at different levels is made thus, starting with an insulating substrate 12 of epoxy resin impregnated glass cloth clad on both sides with copper sheets 10, 11. Holes 16<SP>1</SP> ... 19<SP>1</SP> are formed in copper sheet 11 by a photo-etch process using FeCl 3 solution as etchant; then registering holes 1611, 17<SP>11</SP> &c. are etched in substrate 12 using an etchant composed of a solution of H 2 SO 4 and HF. The walls of the holes and the exposed surfaces of sheets 10, 11 are electroless-plated with Cu, which coating is oxidized and then reduced with formaldehyde solution to form a rough surface on the walls of the holes; the Cu coating is removed from sheet 11, as by abrading. Next the whole is electroplated with Cu; then the holes are filled with conductive material to connect plates 10 and 11 together. The conductive filler may be a mixture of Cu, Ag, or Au and resin, or an alloy of Ga, In, Hg &c. with Cu, Au, Ag, &c. A preferred filler comprises a eutectic of Ga and In mixed with Au, and may be applied to the holes by squeezing in the plastic state; alternatively, equal weights of powdered In and Au are placed in the holes and heated to alloy; or a sphere of a mixture of powdered metals such as Au, Pb and Sn is placed over each hole and heated. Preferably the assembly is again electroplated with Cu. A wiring pattern is formed in Cu sheet 11 by photo-etching; if desired a pattern may be formed in sheet 10 simultaneously or subsequently. A further sheet of insulating material clad with a third conductive sheet is laminated over the pattern formed in sheet 11 and the process is repeated; and so on, for all subsequent layers.
Publications (1)
Publication Number | Publication Date |
---|---|
GB1054797A true GB1054797A (en) |
Family
ID=1758327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1054797D Active GB1054797A (en) |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1054797A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0213805A1 (en) * | 1985-08-12 | 1987-03-11 | Interconnect Technology Inc. | Multilayer circuit board |
GB2263818A (en) * | 1992-01-30 | 1993-08-04 | Nippon Cmk Kk | Method of manufacturing a printed wiring board |
-
0
- GB GB1054797D patent/GB1054797A/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0213805A1 (en) * | 1985-08-12 | 1987-03-11 | Interconnect Technology Inc. | Multilayer circuit board |
GB2263818A (en) * | 1992-01-30 | 1993-08-04 | Nippon Cmk Kk | Method of manufacturing a printed wiring board |
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